KR100884360B1 - Nickel silicide producing method - Google Patents

Nickel silicide producing method Download PDF

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KR100884360B1
KR100884360B1 KR1020070096454A KR20070096454A KR100884360B1 KR 100884360 B1 KR100884360 B1 KR 100884360B1 KR 1020070096454 A KR1020070096454 A KR 1020070096454A KR 20070096454 A KR20070096454 A KR 20070096454A KR 100884360 B1 KR100884360 B1 KR 100884360B1
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nickel
nickel silicide
method
layer
nm
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KR1020070096454A
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Korean (ko)
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송오성
윤기정
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서울시립대학교 산학협력단
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS

Abstract

A method for producing nickel silicide is provided to reduce contact resistance at a low or high temperature by performing a rapid thermal process after depositing ruthenium and nickel on a signal crystal silicon wafer or a poly crystal silicon thin film with predetermined thickness successively. A ruthenium layer(20) is formed on a substrate(10). A nickel layer(30) is formed on the ruthenium layer. The nickel silicide(40) is formed by thermally processing the ruthenium layer and the nickel layer. The substrate is one of single crystal silicon substrate or the silicon polycrystalline substrate. The ruthenium layer and the nickel layer are formed by using the physical vapor deposition or the chemical vapor deposition.

Description

Nickel Silicide Producing Method

The present invention relates to a method for manufacturing nickel silicide for lowering contact resistance in a CMOS semiconductor process, and more particularly, by sequentially depositing ruthenium and nickel in a predetermined thickness on a single crystal silicon wafer or a polycrystalline silicon thin film, and then performing rapid heat treatment. It relates to a nickel silicide manufacturing method for improving the operation speed of the device by lowering the contact resistance value at high temperature as well as low temperature.

Metal silicide is a compound in which a metal is additionally bonded to a silicon atom and is widely used to reduce contact resistance between a source and a drain and a gate and a metal wiring line in a semiconductor manufacturing process.

As a method of preparing the metal silicide, a metal is deposited by physical vapor deposition (PVD), or the like, and then a metal silicide is formed by reacting the metal with silicon using a rapid thermal annealing (RTA) method. The method of forming the is widely adopted. Of course, a method using chemical vapor deposition (CVD) instead of physical vapor deposition is also possible. However, the chemical vapor deposition method has a disadvantage in that it is difficult to secure a stable source region and it is difficult to form a thin silicide thin film.

On the other hand, recently, as a nano-class MOSFET having a minimum line width of 65 nm or less is attracting attention, development of a nano-class metal silicide having excellent high temperature stability and a low resistance, which is thinner than a conventional metal silicide, is about 50 nm thick.

Examples of the metal silicides currently being applied or being developed for the actual semiconductor manufacturing process include titanium silicide, cobalt silicide and nickel silicide, but there are limitations in applying them to the nanoscale MOSFET manufacturing process.

In particular, nickel silicide is evaluated to have a low resistance value, low silicon consumption, and stable silicide to be applied to nano-class MOSFETs more easily than titanium silicide and cobalt silicide. However, nickel silicide has a problem in that when the heat treatment temperature is 700 ° C. or higher, a nickel disilicide (NiSi 2 ) having a high resistance value is formed.

Accordingly, the present invention has been made to solve the above-described problems of the prior art, by sequentially depositing ruthenium and nickel to a predetermined thickness on a single crystal or polycrystalline silicon, and then performing a heat treatment to improve the characteristics of low resistance in a wide heat treatment temperature range The eggplant aims to provide a method for producing nickel silicide.

In order to achieve the above object, the nickel silicide manufacturing method according to the present invention comprises the steps of (a) forming a ruthenium layer on a substrate; (b) forming a nickel layer on the ruthenium layer; And (c) heat treating the ruthenium layer and the nickel layer.

The substrate may be either a silicon single crystal substrate or a silicon polycrystalline substrate.

The ruthenium layer and the nickel layer may be formed using physical vapor deposition or chemical vapor deposition.

The thickness of the ruthenium layer may be 1/10 or less of the thickness of the nickel layer.

The heat treatment method in (c) may be a rapid thermal annealing (RTA) method.

In (c), the heat treatment temperature may be 300 to 1100 ° C.

In (c), the heat treatment time may be 40 seconds.

The method may further include removing the metal remaining after the step (c).

The metal may be removed by soaking the substrate in a sulfuric acid solution for a certain time.

The nickel silicide may have a surface roughness of 12 nm or less.

The nickel silicide may be nickel monosilicide.

Nickel silicide according to the present invention has a low resistance value even when the heat treatment temperature is high temperature as well as low temperature.

In addition, according to the present invention, nickel silicide has an effect of lowering the contact resistance between the source, the drain, and the gate and the metal wiring when applied to the nano-class MOSFET, thereby increasing the operation of the MOSFET.

In addition, according to the present invention, since nickel silicide has a surface roughness value of 12 nm or less, there is an effect that can be applied to a nano-class MOSFET.

DETAILED DESCRIPTION OF THE INVENTION The following detailed description of the invention is described with reference to the accompanying drawings, which show by way of illustration specific embodiments in which the invention may be practiced. These examples are described in sufficient detail to enable those skilled in the art to easily practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein may be embodied in other embodiments without departing from the spirit and scope of the invention with respect to one embodiment. In addition, it is to be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.

Nickel Silicide Manufacturing Process

1A is a view illustrating a nickel silicide manufacturing process according to an embodiment of the present invention.

As shown, the nickel silicide manufacturing method according to the present invention comprises the steps of forming a ruthenium layer 20 on the single crystal silicon wafer 10, forming a nickel layer 30 on the ruthenium layer 20, and And heat treating the ruthenium layer 20 and the nickel layer 30.

1B is a view illustrating a nickel silicide manufacturing process according to another embodiment of the present invention.

As shown, the nickel silicide manufacturing method according to the present invention comprises the steps of forming a silicon oxide film 11 on the single crystal silicon wafer 10, forming a polycrystalline silicon film 12 on the silicon oxide film 11, Forming a ruthenium layer 20 on the polycrystalline silicon film 12, forming a nickel layer 30 on the ruthenium layer 20, and heat-treating the ruthenium layer 20 and the nickel layer 30. Steps.

The difference between the nickel silicide manufacturing method shown in FIGS. 1A and 1B is whether the ruthenium layer is deposited on single crystal silicon or polycrystalline silicon. FIG. 1A assumes the case where nickel silicide is formed on the source and the drain of the MOSFET, and FIG. 1B assumes the case where nickel silicide is formed on the gate of the MOSFET. Hereinafter, a method of manufacturing nickel silicide shown in FIGS. 1A and 1B will be described in detail.

First, as the single crystal silicon substrate 10, a p-type 100 single crystal silicon wafer 10 having a diameter of 100 mm and a thickness of 550 μm was used.

Next, a silicon oxide film (SiO 2 ; 11) was formed by thermally oxidizing the single crystal silicon substrate 10. In the present invention, a silicon oxide film 12 having a thickness of 200 nm is used.

Next, the polycrystalline silicon film 12 was formed using a low pressure chemical vapor phase (Low Pressure CVD) method, and in the present invention, a polycrystalline silicon film 12 having a thickness of 30 nm or 70 nm was used. Here, the 30 nm polycrystalline silicon film 12 assumes a FUSI (fully silicide silicon) gate.

Next, the ruthenium layer 20 and the nickel layer 30 are successively formed on the single crystal silicon wafer 10 or the polycrystalline silicon film 12. The ruthenium layer 20 and the nickel layer 30 may be formed by a physical vapor deposition method such as thermal evaporation, an E-beam evaporation method or a sputtering method, or a low pressure chemical vapor deposition method or a plasma chemical vapor deposition method. It can be formed using the same chemical vapor deposition method. In the present invention, the ruthenium layer 20 and the nickel layer 30 were formed by thermal evaporation. At this time, the ruthenium layer 20 is preferably formed before the natural oxide film is formed on the single crystal silicon wafer 10 or the polycrystalline silicon film 20. In addition, it is preferable that the thickness of the ruthenium layer 20 is one tenth or less of the thickness of the nickel layer 30.

Thus, the three specimen structures prepared for nickel silicide formation in the present invention are single crystal Si (550 μm) / Ru (1 nm) / Ni (10 nm), single crystal Si (550 μm) / SiO 2 (200 nm) / polycrystal. Si (30 nm) / Ru (1 nm) / Ni (10 nm), and single crystal Si (550 μm) / SiO 2 (200 nm) / polycrystalline Si (70 nm) / Ru (1 nm) / Ni (10 nm) )to be.

Next, the ruthenium layer 20 and the nickel layer 30 are heat-treated to form nickel silicide 40. In the present invention, the heat treatment method uses a rapid thermal annealing (RTA) method. The heat processing temperature was 300, 450, 500, 700, 800, 900, 1000, 1100 degreeC, and heat processing time was 40 second. In this case, the time taken for the temperature to rise to the heat treatment temperature was about 20 seconds, and the overshoot of about 40 to 100 ° C. occurred, and the time required for the temperature to fall to the heat treatment temperature was about 10 seconds.

Next, the excess metal (nickel or ruthenium) that did not become nickel silicide was removed during the heat treatment. In the present invention, the excess metal was removed by soaking the specimen in a 30% sulfuric acid solution for about 10 minutes while the temperature is maintained at 80 ℃ after the heat treatment.

Properties of Nickel Silicide

Sheet resistance measurement, X-ray diffraction analysis, and surface roughness measurement were performed to understand the characteristics of the nickel silicide manufactured through the above-described manufacturing process.

First, the sheet resistance R s was measured using a four point probe. In general, the sheet resistance can be determined by measuring a current flowing through the sample after applying a constant voltage to the sample. The sheet resistance is proportional to the applied voltage (V) and the length (L) of the sample. Inversely proportional to the width (W).

In addition, the phase of nickel silicide was confirmed using high resolution X-ray diffraction analysis. At this time, the X-ray source was CuKα radiation obtained by passing through a nickel filter, the wavelength was 1.5406 mA, the filament current was 30 mA, and the acceleration voltage was 40 mA. The X-ray scan area was made to have a 2θ value in the range of 20 ° to 80 ° in consideration of the data of nickel silicide shown on the Joint Committee Powder Diffraction Standards (JCPDS) card.

In addition, surface roughness to surface roughness were measured using the scanning probe microscope (SPM). At this time, the surface roughness (root mean square, RMS) was measured by scanning analysis of the 5 × 5 ㎛ 2 range of nickel silicide in the contact mode. Final surface roughness values were determined as their average values by setting five horizontal lines.

Figure 2 is a graph showing the change in sheet resistance with the heat treatment temperature of the nickel silicide formed on the single crystal silicon in accordance with the present invention.

Referring to FIG. 2, circle marks indicate sheet resistance values according to heat treatment temperatures of nickel silicide formed without adding ruthenium. As is already known, the conventional nickel silicide exhibits a high resistance tendency to form a Ni 2 Si phase at 450 ° C. or lower to increase resistance, a NiSi phase is formed at 450 to 700 ° C., and a low resistance tendency at 700 ° C. or higher. It can be seen that the two phases are formed, indicating a high resistance tendency to increase the resistance again.

On the other hand, in FIG. 2, the se- mono posh shows the sheet resistance value according to the heat treatment temperature of the nickel silicide formed by adding ruthenium according to the present invention. As shown, the nickel silicide of the present invention exhibits a stable low resistance tendency in and around 35 Ω / sq, unlike the conventional nickel silicide even at a low temperature of less than 450 ℃ and a high temperature of 700 to 1100 ℃. This indicates that the formation of high resistance phase nickel disilicide (Ni 2 Si and NiSi 2 ) is suppressed by adding ruthenium during nickel silicide formation. Therefore, the addition of ruthenium during nickel silicide formation can significantly extend the temperature at which the low resistance phase nickel monosilicide becomes a stable phase to a range of 300 to 1100 ° C.

3 is a graph showing the change of the surface resistance value according to the heat treatment temperature of the nickel silicide formed on the polycrystalline silicon in accordance with the present invention.

Referring to FIG. 3, the square display shows sheet resistance values according to heat treatment temperatures of nickel silicide formed without adding ruthenium. As shown in the figure, the low resistance of about 35 Ω / sq is maintained in the temperature range of 300 to 700 ° C., whereas the sheet resistance value is rapidly increased by several kΩ / sq in the temperature range of 700 ° C. or higher. .

On the other hand, referring to Figure 3, the circle indicates the sheet resistance value according to the heat treatment temperature of the nickel silicide (formed on the 30 nm polycrystalline silicon film) formed by the addition of ruthenium according to the present invention. As shown, in the temperature range of 450 ° C or less, as the temperature decreases at, the sheet resistance value increases to around 100 Ω / sq, but in general, when the sheet resistance is 100 Ω / sq or less, there is no big problem in performing the role of silicide. In addition, in the temperature range of 450-1000 degreeC, the sheet resistance value about 10 ohm / sq is maintained. Therefore, the nickel silicide formed in the polycrystalline Si (30 nm) / Ru (1 nm) / Ni (10 nm) structure also breaks down to a temperature range of 300 to 1000 ° C. in which the low resistance phase nickel monosilicide becomes stable by ruthenium addition. You can see that it expands to.

In addition, referring to FIG. 3, the triangle display shows the sheet resistance value according to the heat treatment temperature of the nickel silicide (formed on the 70 nm polycrystalline silicon film) formed by the addition of ruthenium according to the present invention. As shown, the nickel silicide formed in the polycrystalline Si (70 nm) / Ru (1 nm) / Ni (10 nm) structure is formed in the polycrystalline Si (30 nm) / Ru (1 nm) / Ni (10 nm) structure. Unlike nickel silicide, the surface resistance of about 10 Ω / sq is maintained only in the temperature range of 450 to 700 ° C. Therefore, from the result of FIG. 3, when forming nickel silicide on a polycrystalline silicon film, it can be said that it is desirable to make the thickness of a polycrystalline silicon film 70 nm or less.

4 is a graph showing the results of X-ray diffraction analysis of nickel silicide formed on single crystal silicon according to the present invention. As shown, in the case of single crystal Si (550 μm) / Ru (1 nm) / Ni (10 nm), the (112) diffraction peak of NiSi, which is low resistance, at both the heat treatment temperatures of 700 ° C. and 1000 ° C., is 2θ = 45.839 °. And 2θ = 47.332 °. The X-ray diffraction analysis results are consistent with the results of the sheet resistance values of FIG. 2 described above.

5 is a graph showing the results of X-ray diffraction analysis of nickel silicide formed on polycrystalline silicon according to the present invention. As shown, in the case of polycrystalline Si (30 nm) / Ru (1 nm) / Ni (10 nm), the (211) diffraction peak of NiSi, which is low resistance at both the heat treatment temperatures of 700 ° C. and 1000 ° C., is 2θ = 45.839 °. And 2θ = 47.332 °. On the other hand, in the case of polycrystalline Si (70 nm) / Ru (1 nm) / Ni (10 nm), the (211) diffraction peaks of the low-resistance NiSi (211) were obtained at 2θ = 45.839 ° and 2θ = 47.332 ° at a heat treatment temperature of 700 ° C. Although observed, the (220) diffraction peak (reversed square display) of NiSi 2 , which is a high resistance phase, was observed at a heat treatment temperature of 1000 ° C. at 2θ = 47.637 °. The X-ray diffraction analysis results are consistent with the results of the sheet resistance values of FIG. 3 described above.

6 is a graph showing the change of the surface roughness value according to the heat treatment temperature of nickel silicide according to the present invention. As shown, in the case of single crystal Si (550 μm) / Ru (1 nm) / Ni (10 nm), the surface roughness value was in the range of 5.2776 nm (700 ° C.) to 15.05 nm (1000 ° C.). In the case of polycrystalline Si (30 nm) / Ru (1 nm) / Ni (10 nm), the surface roughness values were in the range of 8.5144 nm (700 ° C.) to 12.292 nm (1000 ° C.). In the case of polycrystalline Si (70 nm) / Ru (1 nm) / Ni (10 nm), the surface roughness values were in the range of 9.4482 nm (1000 ° C.) to 11.202 nm (700 ° C.). From the results of FIG. 6, it can be seen that nickel silicide prepared by adding ruthenium according to the present invention generally has a surface roughness of 12 nm or less that can be applied to nanoscale MOSFETs.

In the present invention as described above has been described by the specific embodiments, such as specific components and limited embodiments and drawings, but this is provided to help a more general understanding of the present invention, the present invention is not limited to the above embodiments. In the art, various modifications and variations are possible to those skilled in the art. Therefore, the spirit of the present invention should not be limited to the described embodiments, and all of the equivalents and equivalents of the claims, as well as the following claims, will fall within the scope of the present invention. .

1A is a view illustrating a nickel silicide manufacturing process according to an embodiment of the present invention.

Figure 1b is a view showing a nickel silicide manufacturing process according to another embodiment of the present invention.

2 is a graph showing the change of the surface resistance value according to the heat treatment temperature of nickel silicide formed on single crystal silicon according to the present invention.

3 is a graph showing the change of the surface resistance value according to the heat treatment temperature of nickel silicide formed on polycrystalline silicon according to the present invention.

4 is a graph showing the results of X-ray diffraction analysis of nickel silicide formed on single crystal silicon according to the present invention.

5 is a graph showing the results of X-ray diffraction analysis of nickel silicide formed on polycrystalline silicon according to the present invention.

Figure 6 is a graph showing the change in surface roughness value according to the heat treatment temperature of nickel silicide according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: substrate (silicon wafer)

11: silicon oxide film

12: polycrystalline silicon film

20: ruthenium layer

30: nickel layer

40: nickel silicide

Claims (12)

  1. (a) forming a ruthenium layer on the substrate;
    (b) forming a nickel layer on the ruthenium layer; And
    (c) heat treating the ruthenium layer and the nickel layer to form nickel silicide
    Nickel silicide manufacturing method comprising a.
  2. The method of claim 1,
    The substrate is a nickel silicide manufacturing method, characterized in that any one of a silicon single crystal substrate or a silicon polycrystalline substrate.
  3. The method of claim 1,
    The ruthenium layer and the nickel layer is nickel silicide manufacturing method, characterized in that formed using physical vapor deposition or chemical vapor deposition.
  4. The method of claim 1,
    The thickness of the ruthenium layer is nickel silicide manufacturing method, characterized in that less than 1/10 of the thickness of the nickel layer.
  5. The method of claim 1,
    The heat treatment method in (c) is nickel silicide manufacturing method characterized in that the Rapid Thermal Annealing (RTA) method.
  6. The method of claim 5,
    Nickel silicide manufacturing method characterized in that the heat treatment temperature in (c) is 300 to 1100 ℃.
  7. The method of claim 6,
    Nickel silicide manufacturing method characterized in that the heat treatment time in (c) is 40 seconds.
  8. The method of claim 1,
    Nickel silicide manufacturing method further comprises the step of removing the metal remaining after the step (c).
  9. The method of claim 8,
    The method of claim 9, wherein the metal is removed by immersing the substrate in a sulfuric acid solution for a predetermined time.
  10. The method of claim 1,
    The nickel silicide has a surface roughness of 12 nm or less nickel silicide manufacturing method.
  11. The method of claim 1,
    The nickel silicide is nickel monosilicide manufacturing method, characterized in that the nickel monosilicide.
  12. Nickel silicide prepared by the method of claim 1.
KR1020070096454A 2007-09-21 2007-09-21 Nickel silicide producing method KR100884360B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10319995B2 (en) 2013-12-27 2019-06-11 Hyundai Motor Company Silicon nanowire structure embedded in nickel silicide nanowires for lithium-based battery anodes

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990013586A (en) * 1997-07-03 1999-02-25 월리엄 비 캠플러 The method of forming a silicide layer using the amorphous-metallic impurities and pre
KR20050101669A (en) * 2004-04-19 2005-10-25 삼성전자주식회사 Semiconductor device having a metallic silicide layer and method of forming a metallic silicide layer
KR20050117138A (en) * 2004-06-09 2005-12-14 삼성전자주식회사 Salicide process using bi-metal layer and method of fabricating a semiconductor device using the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990013586A (en) * 1997-07-03 1999-02-25 월리엄 비 캠플러 The method of forming a silicide layer using the amorphous-metallic impurities and pre
KR20050101669A (en) * 2004-04-19 2005-10-25 삼성전자주식회사 Semiconductor device having a metallic silicide layer and method of forming a metallic silicide layer
KR20050117138A (en) * 2004-06-09 2005-12-14 삼성전자주식회사 Salicide process using bi-metal layer and method of fabricating a semiconductor device using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10319995B2 (en) 2013-12-27 2019-06-11 Hyundai Motor Company Silicon nanowire structure embedded in nickel silicide nanowires for lithium-based battery anodes

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