KR100871741B1 - Fabricating method of metal wire in semiconductor - Google Patents
Fabricating method of metal wire in semiconductor Download PDFInfo
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- KR100871741B1 KR100871741B1 KR1020070051257A KR20070051257A KR100871741B1 KR 100871741 B1 KR100871741 B1 KR 100871741B1 KR 1020070051257 A KR1020070051257 A KR 1020070051257A KR 20070051257 A KR20070051257 A KR 20070051257A KR 100871741 B1 KR100871741 B1 KR 100871741B1
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000002184 metal Substances 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000001020 plasma etching Methods 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 16
- 238000001312 dry etching Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/8232—Field-effect technology
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Abstract
본 발명은 반도체 소자의 금속 배선 형성 기술에 관한 것으로, 반도체 기판상에 절연막을 증착하고, 절연막 상부에 제1 산화막을 형성하며, 제1 산화막에 콘택홀을 형성하고, 콘택홀의 측벽에 베리어 메탈(BM)을 증착하고, 상기 콘택홀을 전도성 물질로 채우며, 제1 산화막 및 콘택홀 상부에 층간 절연막을 증착하고, 상기 층간 절연막 상부에 제2 산화막을 형성하고, 전도성 물질의 심 주변을 제외한 상기 제2 산화막 상부에 포토레지스트를 증착하고, 상기 전도성 물질의 심 영역에 마스크를 추가로 증착하며, 증착된 포토레지스트 및 마스크를 이용하여 건식 식각을 수행하고, 건식 식각 후 기존 조건(POR) 보다 오버 식각 시간(over etch time)을 소정의 시간만큼 증가시켜 반응성 이온 식각(RIE) 공정을 수행하는 것을 특징으로 한다. 본 발명에 의하면, W-seam의 주변 산화막 부분만 선택적으로 식각하고, 반응성 이온 식각 공정 시 오버 식각 시간을 증가시켜 트렌치의 깊이를 낮춤으로서, M1의 저항을 개선할 수 있다.
반도체, BEOL, RIE, W-seam
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for forming metal wirings in a semiconductor device, wherein an insulating film is deposited on a semiconductor substrate, a first oxide film is formed over the insulating film, a contact hole is formed in the first oxide film, and a barrier metal (or metal) is formed on the sidewall of the contact hole. Depositing a BM), filling the contact hole with a conductive material, depositing an interlayer insulating film over the first oxide film and the contact hole, forming a second oxide film over the interlayer insulating film, and forming the second oxide film over the seam of the conductive material. A photoresist is deposited on the oxide layer, a mask is further deposited on the core region of the conductive material, dry etching is performed using the deposited photoresist and mask, and after etching, over etching is performed over the conventional condition (POR). It is characterized in that the reactive ion etching (RIE) process is performed by increasing the over etch time by a predetermined time. According to the present invention, only the peripheral oxide film portion of the W-seam is selectively etched, and the over-etching time is increased during the reactive ion etching process to decrease the depth of the trench, thereby improving the resistance of M1.
Semiconductor, BEOL, RIE, W-seam
Description
도 1은 본 발명의 바람직한 실시예에 따른 D1 반응성 이온 식각 전 추가로 제작된 마스크를 이용하여 포토 공정을 진행하는 공정 단면도, 1 is a cross-sectional view of a process of performing a photo process using a mask additionally prepared before D1 reactive ion etching according to a preferred embodiment of the present invention;
도 2는 본 발명의 바람직한 실시예에 따른 건식 식각 후 W-심 주변의 식각된 영역의 두께를 측정하는 공정 단면도, FIG. 2 is a cross-sectional view illustrating a thickness of an etched region around a W-seam after dry etching according to a preferred embodiment of the present invention; FIG.
도 3은 본 발명의 바람직한 실시예에 따른 D1 반응성 이온 식각 시 기존 조건보다 오버 식각 시간을 증가하여 진행한 공정 단면도. Figure 3 is a cross-sectional view of the process proceeded by increasing the over-etching time than the existing conditions during the D1 reactive ion etching in accordance with a preferred embodiment of the present invention.
본 발명은 0.13um FCT(Foundry Compatible Technology)에서의 Cu 배선공정(BEOL) 기술에 관한 것으로서, 특히 M1 저항(Rs)을 개선하는데 적합한 반도체 소자의 제조방법에 관한 것이다. The present invention relates to a Cu wiring process (BEOL) technology in 0.13um FCT (Foundry Compatible Technology), and more particularly, to a method of manufacturing a semiconductor device suitable for improving M1 resistance (Rs).
일반적으로 0.13 FCT의 Cu BEOL 공정상에서 D1 반응성 이온 식각(reactive ion etching, 이하 RIE라 한다)시에 오버 식각 시간(Over Etch Time)동안 원하는 트렌치 깊이까지 식각을 진행하고 있으며, 이때, M1 저항에 영향을 많이 주고 있는 부분은 트렌치 깊이(Trench Depth)이다. 현재 0.13um FCT의 M1 저항 타겟(Metal 1 Rs Target)은 82 mohm / sq 이다. 여기서, D1은 평탄화층의 적층 두께로서, 평탄화층은 층간 절연막과 산화막을 포함한다.Generally, during the 0.13 FCT Cu BEOL process, the etching process is performed to the desired trench depth during the over etching time during D1 reactive ion etching (hereinafter referred to as RIE). The part that gives a lot is the trench depth. The 0.11um FCT M1 resistance target (Metal 1 Rs Target) is 82 mohm / sq. Here, D1 is a stack thickness of the planarization layer, and the planarization layer includes an interlayer insulating film and an oxide film.
상기한 바와 같이 동작하는 종래 기술에 의한 RIE 식각 공정에 있어서는, 종래의 식각 시간(Etch Time)으로 M1 저항 타겟을 제어하기에는 매우 어렵다. 그 이유는 추가로 오버 식각(Over Etch)을 진행하게 될 경우 트랜지스터(Tr: Transister)와 메탈 계층을 연결하는 W-심(seam)도 식각됨으로써, D1 랜딩 이슈(landing issue)가 발생하여 소자 성능 테스트(PCM & Probe Test)시 오픈/쇼트 불량(Open / Short Failure)이 발생하게 되는 문제점이 있었다.In the RIE etching process according to the prior art operating as described above, it is very difficult to control the M1 resistance target with a conventional etching time. The reason for this is that when the over etching process is performed, the W-seam connecting the transistor (Tr) and the metal layer is also etched, resulting in a D1 landing issue, resulting in device performance. There was a problem that an open / short failure occurred during the test (PCM & Probe Test).
본 발명은 상술한 종래 기술의 한계를 극복하기 위한 것으로, 배선 공정의 반응성 이온 식각 전에 W-심위에 마스크를 증착하여 W-심을 보호하며, W-심 주변에 건식식각을 수행한 후 D1 RIE 진행 시 기존 조건 보다 더 오버 식각 시간을 수행함으로써, M1의 저항을 개선할 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다. The present invention is to overcome the above-mentioned limitations of the prior art, to protect the W-core by depositing a mask on the W-core before the reactive ion etching of the wiring process, D1 RIE after performing dry etching around the W-core It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of improving the resistance of M1 by performing an over-etching time more than existing conditions.
본 발명의 다른 목적은, 0.13um FCT의 구리 배선공정에서 M1 저항을 개선하기 위해 반응성 이온 식각 진행 전에 추가로 W-심 위에 마스크를 증착한 후, 그 주변을 건식 식각으로 대략 200Å 정도 식각하고, 반응성 이온 식각의 진행 시 기존 조건 보다 더 오버 식각 시간을 진행함으로써, M1의 저항을 개선할 수 있는 방법을 제공하는데 있다.Another object of the present invention, in order to improve the M1 resistance in the copper wiring process of 0.13um FCT, after further depositing a mask on the W- shim before the reactive ion etching proceeds, the surroundings are etched by dry etching about 200Å, The present invention provides a method of improving the resistance of M1 by performing an over-etching time more than conventional conditions in the process of reactive ion etching.
이와 같은 목적을 실현하기 위한 본 발명은 반도체 소자의 금속 배선 형성 방법으로서, 반도체 기판상에 절연막을 증착하는 단계와, 상기 절연막 상부에 제1 산화막을 형성하는 단계와, 상기 제1 산화막에 콘택홀을 형성하는 단계와, 상기 콘택홀의 측벽에 베리어 메탈(BM)을 증착하고, 상기 콘택홀을 전도성 물질로 채우는 단계와, 상기 제1 산화막 및 콘택홀 상부에 층간 절연막을 증착하고, 상기 층간 절연막 상부에 제2 산화막을 형성하는 단계와, 전도성 물질의 심 주변을 제외한 상기 제2 산화막 상부에 포토레지스트를 증착하고, 상기 전도성 물질의 심 영역에 마스크를 추가로 증착하는 단계와, 상기 증착된 포토레지스트 및 마스크를 이용하여 건식 식각을 수행하는 단계와, 상기 건식 식각 후 기존 조건(POR) 보다 오버 식각 시간(over etch time)을 소정의 시간만큼 증가시켜 반응성 이온 식각(RIE) 공정을 수행하는 단계를 포함한다. According to an aspect of the present invention, there is provided a method for forming a metal wiring of a semiconductor device, the method comprising: depositing an insulating film on a semiconductor substrate, forming a first oxide film on the insulating film, and forming a contact hole in the first oxide film Forming a barrier layer, depositing a barrier metal (BM) on the sidewalls of the contact hole, filling the contact hole with a conductive material, depositing an interlayer insulating layer on the first oxide layer and the contact hole, and forming an upper portion of the interlayer insulating layer. Forming a second oxide layer on the second oxide layer, depositing a photoresist on the second oxide layer except for the periphery of the conductive material, and further depositing a mask on the core region of the conductive material; And performing dry etching using a mask, and overetch time after the dry etching. Increasing by time to perform a reactive ion etching (RIE) process.
이하 첨부된 도면을 참조하여 본 발명의 동작 원리를 상세히 설명한다. 하기에서 본 발명을 설명함에 있어서 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다. 그리고 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 관례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. Hereinafter, the operating principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, when it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.
본 발명은 배선 공정의 반응성 이온 식각 전에 W-심 위에 마스크를 증착하여 W-심을 보호하고, W-심 주변에 건식식각을 수행한 후 D1 RIE 진행 시 기존 조건 보 다 오버 식각 시간을 증가시켜 수행함으로써, M1의 저항을 개선하는 것이다.The present invention protects the W-sim by depositing a mask on the W-seam before the reactive ion etching of the wiring process, and performs the dry etching around the W-sea, and then increases the over-etch time than the existing conditions during the D1 RIE. This improves the resistance of M1.
이때, W-심 주변을 건식 식각으로 식각하고, 반응성 이온 식각의 진행 시 기존 조건 보다 오버 식각 시간을 증가시켜 진행함으로써, 기존의 트렌치 깊이인 2800Å보다 더 낮은 2400Å ~ 2500Å의 트렌치 깊이를 형성함으로써, M1의 저항을 개선한다.At this time, by etching the dry around the W- seam, and proceeds by increasing the over-etching time than the existing conditions when the reactive ion etching proceeds, by forming a trench depth of 2400Å ~ 2500 더 lower than the conventional trench depth 2800Å, Improve the resistance of M1.
도 1은 본 발명의 바람직한 실시예에 따른 D1 반응성 이온 식각 전 추가로 제작된 마스크를 이용하여 포토 공정을 진행하는 공정 단면도이다. 1 is a cross-sectional view illustrating a process of performing a photo process using a mask additionally manufactured before D1 reactive ion etching according to a preferred embodiment of the present invention.
도 1을 참조하면, STI(shallow trench isolation)(50) 및 저농도 접합 영역(90a, 90b)이 형성되어 있는 반도체 기판(100) 위에 게이트 절연막(60a, 60b) 및 게이트 전극(70a, 70b)을 차례로 형성한다. 여기서, STI(50)는 반도체 기판(100)에 형성된 소자를 전기적으로 격리시킴으로써 오동작을 방지한다. 이어, 반도체 기판(100)과 게이트 전극(70a, 70b) 위에 게이트 전극(60a, 60b)의 손상을 방지하는 제1 산화막(105), 질화막(110)을 차례로 증착한다. Referring to FIG. 1,
그 다음, 산화막(105), 질화막(110)을 RIE 공정으로 식각하여 게이트 절연막(60a, 60b) 및 게이트 전극(70a, 70b)의 측면에 스페이서(spacer)(115)를 형성한다. 이후, 노출된 반도체 기판(100)에 n형 또는 p형 불순물 이온을 고농도로 주입하여 고농도 접합 영역(90a)을 형성한다. Next, the
다음, 반도체 기판(100), 게이트 전극(60a, 60b) 및 스페이서(115) 위에 제 2질화막(120)을 증착한 후, 증착된 제2 질화막(120) 상부에 절연막으로서 BPSG막(125)을 증착한다. 또한, BPSG막(125) 상부에 제1 SiH4-산화막(130)을 일정한 두 께로 증착한다. Next, after the
이후 증착된 BPSG막(125) 및 SiH4-산화막(130) 표면상에 M1C(Metal 1 contact:제1금속배선 콘택) 공정으로서, PEP와 RIE를 수행하여 콘택홀을 형성하고, 콘택홀의 바닥면에 정렬 되게 RIE를 수행하며, 이후 측벽에 베리어 메탈(BM: Barrier Metal)(135)을 증착시킨 후, 콘택홀 상에 W(tungesten)(140)을 채우게 된다. 이때, 베리어 메탈로는 Ti 혹은 TiN이 될 수 있다. Thereafter, as a M1C (Metal 1 contact: first metal wiring contact) process on the surfaces of the deposited
다음으로 터치업(touch-up) 공정을 수행하고, 이후 화학기상증착법(Chemical Vapor Deposition: CVD)으로 층간 절연막으로서 대략 1300Å 두께의 FSG(145)를 형성하고, 형성된 FSG(145) 상부에 1500Å 두께의 제2 SiH4-산화막(150)을 형성한다. 이후 D1(제2 SiH4(150), FSG(145)) 포토공정(PEP: Photo Engraving Process)을 수행하기 전에 제2 SiH4-산화막(150) 상부에 포토레지스트(155) 및 추가로 제작된 마스크(160)를 이용하여 제2 SiH4(150), FSG(145), 제1 SiH4(130)을 제거하는 포토 공정을 수행하게 된다. 즉, 마스크(160)를 이용하여 W-심(140)은 보호하고, 그 주변을 식각하는 것이다. Next, a touch-up process is performed, followed by chemical vapor deposition (CVD), to form an approximately 1300 µs thick? FSG 145 as an interlayer insulating film, and a 1500 µm thick over the formed FSG 145. A second SiH 4 -
도 2는 본 발명의 바람직한 실시예에 따른 건식 식각 후 W-심 주변의 식각된 영역의 두께를 측정하는 공정 단면도이다. 2 is a cross-sectional view illustrating a thickness of an etched region around a W-seam after dry etching according to a preferred embodiment of the present invention.
도 2를 참조하면, W-심(140) 주변은 건식 식각을 수행하고, 건식 식각 후 주변에 식각된 영역(SiH4(150), FSG(145), SiH4(130))의 두께를 측정한다. 이때, 식각된 두께는 SiH4(150) 1500Å FSG(145) 1300Å SiH4(130) 200Å 정도가 되도록 한다.Referring to FIG. 2, dry etching is performed around the W-
도 3은 본 발명의 바람직한 실시예에 따른 D1 반응성 이온 식각 시 기존의 조건보다 오버 식각 시간을 증가하여 식각을 진행한 공정 단면도이다. 3 is a cross-sectional view illustrating a process of etching by increasing an over-etching time compared to a conventional condition when etching D1 reactive ions according to a preferred embodiment of the present invention.
도 3을 참조하면, D1 RIE를 수행하는 것으로서, D1 RIE 시 기존의 공정 조건(Process of recording, 이하 POR이라 한다)(Main Etch 60sec / Over Etch 28sec)보다 소정의 오버 식각 시간을 증가시킨 조건(Main Etch 60sec / Over Etch 32sec)으로 진행한다. 즉, 소정의 오버 식각 시간은 POR 조건보다 3~5sec 정도의 시간이 될 수 있다. Referring to FIG. 3, as a D1 RIE, a condition in which a predetermined over-etch time is increased from a conventional process condition (hereinafter referred to as POR) (Main Etch 60sec / Over Etch 28sec) during D1 RIE ( Main Etch 60sec / Over Etch 32sec). That is, the predetermined over-etching time may be about 3 to 5 sec longer than the POR condition.
기존의 D1 RIE의 POR 조건에서 W-심의 두께는 500Å이나 추가된 마스크를 이용한 포토 공정을 통해 W-심 주변을 선택적으로 SiH4(150)(1500Å), FSG(145)(1300Å), SiH4(130)(200Å) 정도 식각함으로써, W-심의 두께를 700Å로 만들어 놓은 상태에서 D1 RIE 진행 시 오버 식각 시간을 증가시켜 기존의 W-심 POR 조건인 500Å으로 유지하면서 트렌치 깊이는 기존의 2800Å 보다 더 낮은 2400Å ~ 2500Å으로 낮춰지므로 이로 인해 M1의 저항은 개선될 수 있다. In the POR condition of the existing D1 RIE, the thickness of the W-simb is 500Å, but the SiH4 (150) (1500Å), FSG (145) (1300Å), SiH4 (130) can be selectively selected around the W-seam through the photo process using the added mask. By etching (200Å), the trench depth is lower than the existing 2800 하면서 while maintaining the W-sim POR condition at 500Å, which increases the over-etching time during D1 RIE while maintaining the thickness of the W-seam at 700Å. This lowers the 2400 kW to 2500 kW, which may improve the resistance of M1.
이상 설명한 바와 같이, 본 발명은 배선 공정의 반응성 이온 식각 전에 W-심위에 마스크를 증착하여 W-심을 보호하고, W-심 주변에 건식식각을 수행한 후 D1 RIE 진행 시 기존 조건 보다 더 오버 식각 시간을 수행함으로써, M1의 저항을 개선한다.As described above, the present invention protects the W-sim by depositing a mask on the W-depth prior to reactive ion etching of the wiring process, and performs dry etching around the W-seed, and then performs more over-etching than the existing conditions during the D1 RIE. By performing the time, the resistance of M1 is improved.
한편 본 발명의 상세한 설명에서는 구체적인 실시예에 관해 설명하였으나, 본 발명의 범위에서 벗어나지 않는 한도 내에서 여러 가지 변형이 가능함은 물론이다. 그러므로 본 발명의 범위는 설명된 실시예에 국한되지 않으며, 후술되는 특허 청구의 범위뿐만 아니라 이 특허청구의 범위와 균등한 것들에 의해 정해져야 한다. Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the appended claims, but also by the equivalents of the claims.
이상에서 상세히 설명한 바와 같이 동작하는 본 발명에 있어서, 개시되는 발명 중 대표적인 것에 의하여 얻어지는 효과를 간단히 설명하면 다음과 같다. In the present invention operating as described in detail above, the effects obtained by the representative ones of the disclosed inventions will be briefly described as follows.
본 발명은, W-심의 주변 산화막 부분만 선택적으로 식각하고, 반응성 이온 식각 공정 시 오버 식각 시간을 증가시켜 트렌치의 깊이를 낮춤으로서, M1의 저항을 개선할 수 있는 효과가 있다. According to the present invention, only the peripheral oxide film portion of the W-simb is selectively etched and the over-etching time is increased during the reactive ion etching process to lower the depth of the trench, thereby improving the resistance of M1.
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