KR100849071B1 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR100849071B1
KR100849071B1 KR1020070053581A KR20070053581A KR100849071B1 KR 100849071 B1 KR100849071 B1 KR 100849071B1 KR 1020070053581 A KR1020070053581 A KR 1020070053581A KR 20070053581 A KR20070053581 A KR 20070053581A KR 100849071 B1 KR100849071 B1 KR 100849071B1
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South Korea
Prior art keywords
logic circuit
control signal
logic
bank
banks
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Application number
KR1020070053581A
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Korean (ko)
Inventor
김종우
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070053581A priority Critical patent/KR100849071B1/en
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Publication of KR100849071B1 publication Critical patent/KR100849071B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

Abstract

A semiconductor memory device is provided to avoid a delay phenomenon of a data signal transferred between banks in a pad by arranging a logic circuit and a pad formed in a peripheral circuit according to the characteristic of a signal. First logic circuits are disposed in the center of a central region(B) positioned between a pair of adjacent upper banks(BANK0,BAND2) and a pair of lower banks(BANK1,BANK3) symmetrical to the pair of upper banks. A second logic circuit is disposed in the center of first and second peripheral regions(A) wherein third and fourth logic circuits are symmetrically disposed on and under the second logic circuit. The first and second peripheral regions are symmetrically positioned at both sides of the central region. A first control signal transfer line is disposed to pass trough the first and second logic circuits, and a data transfer line corresponding to each bank is disposed to pass trough the third and fourth logic circuits in the first and second peripheral regions. A second control transfer line can be disposed to via a region formed in horizontally the same line of the first and third logic circuits.

Description

Semiconductor Memory Device

1 and 2 show the layout of a conventional semiconductor memory device.

3 illustrates a layout of a semiconductor memory device according to an embodiment of the present invention.

4 illustrates a layout of a semiconductor memory device according to another embodiment of the present invention.

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having an improved layout in consideration of signal transfer characteristics.

In general, a semiconductor memory device includes a bank, which is a space for storing data, and peripheral circuits required to perform this role. Here, the region in which the peripheral circuits are formed includes pads for connecting to the outside.

FIG. 1 illustrates an example in which peripheral circuits and pads are arranged in a conventional 4-bank BANK0, BANK1, BANK2, and BANK3 structure, in which banks 0 BANK0 and BANK2 are spaced at predetermined intervals. Peripheral circuits and pads are formed under the regions where bank 0 BANK0 and bank 2 are formed, and banks 1 BANK 1 and 3 BANK 3 are based on the peripheral circuits and pads. It has a structure symmetric to 2.

On the other hand, the space in which the peripheral circuits are arranged includes a central region B adjacent to each bank, and a peripheral region of both sides (between bank 0 and bank 1 and between bank 2 and bank 3) of the central region B ( It can be divided into A). In the central area B, pads related to address and control are mainly disposed, and in the peripheral area A, pads related to data input / output are mainly arranged. In addition, logic circuits 102, 106, and 110 associated with the pads are disposed under the pads of the regions A and B.

Data transmission lines S3a2, S3b2, S4a2, and S4b2 pass through the logic circuits 102 and 110 of the peripheral area A, and each of the data transmission lines S3a2, S3b2, S4a2, and S4b2 passes through the respective data input / output lines. It is connected to each bank BANK0, BANK1, BANK2, BANK3 via (S3a1, S3b2, S4a1, S4b1).

In addition, a plurality of control signal transmission lines S12, S2a2, and S2b2 pass through the logic circuit 106 of the central region B, and the dual control signal transmission lines S12, S2a2, and S2b2 pass through the control input line S11. It is connected to each of the banks BANK0, BANK1, BANK2, and BANK3 via the control signal, and the control signal transmission line S12 extends through the logic circuits 102 and 110 of the peripheral area A.

Looking at the path characteristics of the signal lines according to the arrangement in the peripheral area (A) and the central area (B) of FIG. Thus, the lengths delivered to the four banks BANK0, BANK1, BANK2, and BANK3 are equally advantageous.

Alternatively, data transmission lines are arranged between the pads. Therefore, the peripheral area A passes through the data transmission lines S3a2, S3b2, S4a2, and S4b2 of the logic circuits 102 and 110 from the four banks BANK0, BANK1, BANK2, and BANK3 when data is outputted, and then reverses thereafter. As a result, paths to the pads 100 and 108 are formed. As a result, the data transfer path of FIG. 1 has a characteristic that data transfer is delayed by an overlapping length when data is input or output.

2 shows another example of the prior art, wherein two rows of pads 202 and 214 are centrally disposed in the peripheral area A, and the pads 202 and 214 and the respective banks BANK0, BANK1, BANK2, and BANK3. The data transmission lines S3a2, S3b2, S4a2, and S4b2 constituting the logic circuits 200, 204, 212, and 216 are disposed between the circuits.

However, in this arrangement method, the logic circuits 206 and 210 having the same function are overlapped in the central region B, and the same control signal transmission lines S1a2, S2a2, S1b2, and S2b2 are disposed in the overlapped logic circuits. Should be further deployed. Therefore, the load is increased because the control signal lines are overlapped, thereby increasing the loading time.

In addition, since the power signal is transmitted from a predetermined pad, a time delay occurs when the power signal is transferred from the pad 208 in the bank 0 (BANK0) or bank 2 (BANK2) direction to the bank 1 (BANK1) or the bank 3 (BANK3). Done.

Accordingly, an object of the present invention for solving the above-described problem is to prevent the delay of a signal transmitted by differently arranging pads and logic circuits of peripheral circuits according to regions.

In addition, another object of the present invention is to improve the signal loading characteristics by allowing each bank and each signal line of different types corresponding thereto to be connected at the shortest distance.

And reducing the loading time of the system.

A semiconductor memory device according to the present invention for achieving the above object is a semiconductor memory device including a plurality of banks arranged symmetrically up and down around a predetermined area, comprising a first logic circuit disposed in the center, A central region located between the pair of upper banks and a pair of lower banks symmetrical thereto; And a second logic circuit disposed at the center and third and fourth logic circuits disposed symmetrically therebetween, the first and second peripheral regions being symmetrically positioned at both sides of the central region. A first control signal transmission line is arranged so as to pass through the first logic circuit and the second logic circuit, and to each bank so as to pass through the third and fourth logic circuits of the first and second peripheral regions, respectively. A corresponding data transmission line is arranged.

Each data transmission line may be connected to a corresponding bank through a different data input / output line.

In addition, the first control signal transmission line may be connected to each bank through a different control signal input line.

On the other hand, it is preferable that the pads are formed symmetrically with each other in the central region above and below the first logic circuit.

In addition, the first and second peripheral regions are preferably pads formed symmetrically between the second logic circuit and the third and fourth logic circuits.

In addition, a second control signal transmission line may be further arranged to pass through an area formed on the same line horizontally with the first logic circuit and the third logic circuit.

In addition, a third control signal transmission line may be further arranged to pass through an area formed on the same horizontal line of the first logic circuit and the fourth logic circuit.

Hereinafter, exemplary embodiments of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

The present invention divides peripheral circuits between banks into a central region and a peripheral region, and arranges pads and logic circuits according to regions differently for each region, thereby improving delay of data signals and control signals.

FIG. 3 shows a space in which bank 0 BANK0 and bank 2 BANK2 are spaced apart at predetermined intervals, and peripheral circuits and pads are formed under an area where bank 0 BANK0 and bank 2 BANK2 are disposed. Based on these peripheral circuits and pads, bank 1 BANK1 and bank 3 BANK3 have a structure in which bank 0 BANK0 and bank 2 BANK2 are symmetrical.

The space formed between the four banks BANK0, BANK1, BANK2, and BANK3 is a peripheral circuit composed of a peripheral area A at both ends and a central area B at the center.

In the peripheral area A, circuits related to input and output of data are mainly arranged, and in the central area B, circuits related to control are arranged. Data signal lines arranged in the peripheral area A have a local line characteristic connected to a specific bank, and control signals arranged in the central region B have a global line characteristic connected in common to adjacent banks.

Accordingly, when the peripheral area A is examined in detail, the pads 302 and 314 and the logic circuits 300, 306, 314, and 318 corresponding to upper and lower data and power signals centering on the logic circuits 304 and 316 in the center may be described. Are placed in turn.

Logic circuits 304 and 316 are logic for generating address, power and command signals, and logic circuits 300, 306, 314 and 318 are composed of logic for generating data signals.

The common control signal transmission line S12 is connected to the logic circuits 304 and 316, and the data transmission lines S3a2, S3b2, S4a2 and S4b2 are connected to the logic circuits 300, 306, 312 and 318. The transmission lines S3a2, S3b2, S4a2, and S4b2 are connected to the respective banks BANK0, BANK1, BANK2, and BANK3 through the data input / output lines S3a1, S3b1, S4a1, and S4b1.

The control signal transmission line S12 is connected to each of the banks BANK0, BANK1, BANK2, and BANK3 through the control signal input line S11.

The control signal transmission line S12 is a plurality of signal lines including address, power, and command signals, and the data transmission lines S3a2, S3b2, S4a2, and S4b2 are connected to respective banks, and a plurality of data signals to which data is input and output. Line.

Accordingly, the control signal input line S11 is formed of the first metal layer, and is connected to the control signal transmission line S12 of the second metal layer, and the data input / output lines S3a1, S3b1, S4a1, and S4b1 are formed of the first metal layer. It is formed as a line of the layer, and is connected to the data lines S3a2, S3b2, S4a2, and S4b2 of the second metal layer. Here, the line of the second metal layer is a line formed of a layer higher than the line of the first metal layer.

Meanwhile, in the central area B, a logic circuit 310 including address, command, and power logic is disposed at the center, and a pad 308 connected to a line of address, command, and power signals above and below the logic circuit 310. ).

Specifically, it can be seen that the control signal transmission line S12 is disposed in the center of the logic circuit 310 and extends to the peripheral area A. FIG. The control signal transmission line S12 includes a command signal / RAS, / CAS, / WE, CLK, an address signal, a power signal, and the like, which control when data is written or read.

Further, in the upper and lower spaces of the control signal transmission line S12, control signal transmission lines S2a2 and S2b2 including an address decoder, a buffer, and a bank selection signal are arranged in parallel with the control signal transmission line S12.

The control signal transmission line S12 is formed as a line of the second metal layer, is connected to the control input line S11 of the first metal layer, and extends to the area through the logic circuits 304 and 316. The control signal transmission lines S2a2 and S2b2 are formed as lines of the second metal layer, and are connected to the control input lines S11 of the first metal layer.

Accordingly, the logic circuits 300, 306, 312, and 318 formed in the peripheral circuits are formed adjacent to the respective banks to shorten the transfer path of the data formed when the data is inputted and outputted through the pads 302 and 314 in the banks. do.

The logic circuits 304 and 316 are disposed at the center, so that the path formed when the control signal is transmitted to each of the banks BANK0, BANK1, BANK2, and BANK3 has an even advantage.

That is, in the peripheral area A, when data is output or input, data may be transferred within a short time through the data pads 302 and 314 disposed adjacent from the four banks BANK0, BANK1, BANK2, and BANK3. The central area B is formed by the length of the control and control signals transmitted from the pad 308 to the four banks BANK0, BANK1, BANK2, and BANK3 through the respective lines S12, S2a2 and S2b2. The timing margin of the signal can be secured.

In addition, since the control signal transmission line S12 is not overlapped while being disposed in the center of the central area B, the loading time of the system is shortened.

4 is a diagram illustrating an arrangement relationship between peripheral circuits of FIG. 3 and FIG.

In FIG. 4, the arrangement relationship of each bank BANK0, BANK1, BANK2, BANK3, each logic circuit 400, 404, 406, 410, 412, 416, 418, and each pad 402, 408, 416 is shown in FIG. It is substantially similar to 3, and duplicate descriptions thereof are omitted.

The logic circuit 410 of the central area B and each of the logic circuits 400, 406, 412, 418 of the peripheral area A are collinear in a direction parallel to the control signal transmission lines S2a2 and S2b2 in FIG. 3. Is not formed in the overlapping area.

However, the logic circuit 410 of the central region B of FIG. 4 and each of the logic circuits 400, 406, 412, and 418 of the peripheral region A are the same in parallel with the control signal transmission lines S2a2 and S2b2. It has an overlapping area on the line.

Specifically, each control signal transmission line S2a2 and S2b2 of FIG. 4 is formed to cross each logic circuit 400, 410, 412 and each logic circuit 406, 410, 418.

In addition, the data transmission lines S3a2 and S3b2 pass through the data input / output lines S3a1 and S3b1 in the logic circuits 400 and 406, and the control signal transmission lines S2a2 and S2b2 are in line with the logic circuit 410. Via the control signal input line (S11) in the region of the logic circuit (400, 406) formed in the.

The operation and effect of the embodiment of FIG. 4 are the same as those of FIG. 3, when data is output or input in the peripheral area A, by data logic formed adjacent to the four banks BANK0, BANK1, BANK2, and BANK3, respectively. The path between the data transmission lines S3a2 S3b2 S4a2 S4b2 and the pads 402 and 414 is short, so that the data transfer speed is increased.

The central area B is the length to be transmitted when the control and control signals transmitted from the pad 408 are applied to the four banks BANK0, BANK1, BANK2, and BANK3 through the respective lines S12, S2a2 and S2b2. Is formed evenly to improve the timing margin of the signal. In addition, the control signal transmission line (S12) is arranged in the center of the center area (B) and do not overlap, reducing the loading time of the system.

Accordingly, the semiconductor memory device and its layout according to the present invention arrange logic pads and peripheral pads formed in peripheral circuits according to signal characteristics, thereby preventing delay of data signals transferred between pads and banks, thereby transferring data. Speed up

In addition, the control signal is evenly transmitted to each bank, thereby improving the timing margin of the signal.

And reduce the loading time of the system.

Claims (7)

A semiconductor memory device comprising a plurality of banks arranged symmetrically up and down about a predetermined area, A central region including first logic circuits disposed centrally and located between an adjacent pair of upper banks and a pair of lower banks symmetrical thereto; And Peripheral circuits are divided into a second logic circuit disposed at the center and third and fourth logic circuits arranged symmetrically therebetween, and the first and second peripheral regions symmetrically positioned at both sides of the central region. Become, A first control signal transmission line is arranged to pass through the first logic circuit and the second logic circuit, and data corresponding to each bank to pass through the third and fourth logic circuits of the first and second peripheral regions, respectively. A semiconductor memory device, characterized in that the transmission line is arranged. The method of claim 1, Wherein each data transmission line is connected to a corresponding bank through a different data input / output line. The method of claim 1, And the first control signal transmission line is connected to each bank through a different control signal input line. The method of claim 1, And the pads are symmetrically formed above and below the first logic circuit in the central region. The method of claim 1, And the pads are symmetrically formed between the second logic circuit and the third and fourth logic circuits. The method of claim 1, And a second control signal transmission line further arranged to pass through an area formed on the same horizontal line of the first logic circuit and the third logic circuit. The method of claim 1, And a third control signal transmission line further arranged to pass through an area formed on the same horizontal line of the first logic circuit and the fourth logic circuit.
KR1020070053581A 2007-05-31 2007-05-31 Semiconductor memory device KR100849071B1 (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960015588A (en) * 1994-10-27 1996-05-22 가네꼬 히사시 LOC type semiconductor memory device
US5537057A (en) 1995-02-14 1996-07-16 Altera Corporation Programmable logic array device with grouped logic regions and three types of conductors
KR980004968A (en) * 1996-06-29 1998-03-30 김주용 Method of distributing bank of semiconductor memory device
KR20030090533A (en) * 2002-05-20 2003-11-28 미쓰비시덴키 가부시키가이샤 Semiconductor circuit device adaptable to plurality of types of packages
KR20040003209A (en) * 2002-07-02 2004-01-13 삼성전자주식회사 Pad and peripheral circuit layout in semiconductor device
KR20040009861A (en) * 2002-07-26 2004-01-31 삼성전자주식회사 Semiconductor memory device with data input/output organization of a multiple of 9
KR20040026215A (en) * 2002-09-23 2004-03-30 엘지전자 주식회사 Sensing devise of opening or closing folder for folder type mobile-phone
JP2004171445A (en) * 2002-11-22 2004-06-17 Renesas Technology Corp Semiconductor data processor and data processing system

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960015588A (en) * 1994-10-27 1996-05-22 가네꼬 히사시 LOC type semiconductor memory device
US5537057A (en) 1995-02-14 1996-07-16 Altera Corporation Programmable logic array device with grouped logic regions and three types of conductors
US5598109A (en) 1995-02-14 1997-01-28 Altera Corporation Programmable logic array device with grouped logic regions and three types of conductors
KR980004968A (en) * 1996-06-29 1998-03-30 김주용 Method of distributing bank of semiconductor memory device
KR20030090533A (en) * 2002-05-20 2003-11-28 미쓰비시덴키 가부시키가이샤 Semiconductor circuit device adaptable to plurality of types of packages
KR20040003209A (en) * 2002-07-02 2004-01-13 삼성전자주식회사 Pad and peripheral circuit layout in semiconductor device
KR20040009861A (en) * 2002-07-26 2004-01-31 삼성전자주식회사 Semiconductor memory device with data input/output organization of a multiple of 9
KR20040026215A (en) * 2002-09-23 2004-03-30 엘지전자 주식회사 Sensing devise of opening or closing folder for folder type mobile-phone
JP2004171445A (en) * 2002-11-22 2004-06-17 Renesas Technology Corp Semiconductor data processor and data processing system

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