KR100835761B1 - The controller of high voltage generator - Google Patents

The controller of high voltage generator Download PDF

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Publication number
KR100835761B1
KR100835761B1 KR1020060134934A KR20060134934A KR100835761B1 KR 100835761 B1 KR100835761 B1 KR 100835761B1 KR 1020060134934 A KR1020060134934 A KR 1020060134934A KR 20060134934 A KR20060134934 A KR 20060134934A KR 100835761 B1 KR100835761 B1 KR 100835761B1
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KR
South Korea
Prior art keywords
output
voltage
pump cell
signal
unit
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KR1020060134934A
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Korean (ko)
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유제일
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주식회사 하이닉스반도체
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by G11C11/00
    • G11C5/14Power supply arrangements, e.g. Power down/chip (de)selection, layout of wiring/power grids, multiple supply levels
    • G11C5/145Applications of charge pumps ; Boosted voltage circuits ; Clamp circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by G11C11/00
    • G11C5/14Power supply arrangements, e.g. Power down/chip (de)selection, layout of wiring/power grids, multiple supply levels
    • G11C5/147Voltage reference generators, voltage and current regulators ; Internally lowered supply level ; Compensation for voltage drops
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements

Abstract

The high voltage generator control device of the present invention includes a pump cell unit for generating a high voltage through a plurality of pump cells, a double comparison unit comparing the magnitude of the output voltage of the pump cell unit with the first reference voltage and the second reference voltage; The voltage level classifying unit determines the output voltage range according to the output result of the double comparator, and outputs it in a specific code form, and receives three clock signals having rising edges at different time points and the output signal of the voltage level classifying unit. A voltage change determiner configured to output a range of an output voltage at a first reference time and an output voltage at a second reference time, and enable to operate a specific pump cell among the plurality of pump cells according to an output value of the voltage change determiner It characterized in that it comprises a pump cell operation signal output unit for outputting a signal.

Description

High voltage generator control device {The controller of high voltage generator}

1 is a graph illustrating a change state of an output voltage of a high voltage generator over time.

2 is a block diagram showing the configuration of a high voltage generator control device according to the present invention.

3 is a circuit diagram showing in detail the configuration of the double comparison unit according to the present invention.

4 is a circuit diagram showing in detail the configuration of the voltage level classification unit according to the present invention.

5 is a circuit diagram showing in detail the configuration of the clock converter according to the present invention.

6 is a waveform diagram showing waveforms of the mood clock signal and the first to third clock signals.

7 is a circuit diagram showing in detail the configuration of the voltage change determination unit according to the present invention.

8 is a circuit diagram illustrating a detailed configuration of a pass circuit included in a voltage change determiner.

9 is a circuit diagram showing in detail the configuration of the pump cell operation signal output unit according to the present invention.

Description of the main parts of the drawing

200: pump cell portion 210: double comparison unit

220: voltage level classification unit 230: basic clock generator

240: clock converting unit 250: voltage change determining unit

260: pump cell operation signal output unit

The present invention relates to a control device of a high voltage generator for supplying a high voltage to a nonvolatile memory device, and more particularly, to reduce the operation current by controlling the operation of a pump cell generating a high voltage according to the output high voltage level. A high voltage generator control apparatus.

In general, the nonvolatile memory device includes a high voltage generation circuit that performs an electrical program operation and an erase operation, and generates a high voltage required for each operation. Since the level of the high voltage required for each operation is different, a plurality of high voltage generating circuits outputting different high voltages are required. Meanwhile, each high voltage generation circuit includes a plurality of pump cells including a plurality of capacitors and a plurality of transistors, and each high voltage is generated by the operation of the pump cells.

However, despite the change in the level of the high voltage, which is the output voltage, the number of pump cells operated is unchanged, which may cause unnecessary current consumption.

In order to solve the above problems, an object of the present invention is to provide a high voltage generator control device capable of changing the number of pump cells operated according to the level of the high voltage output.

The high voltage generator control device of the present invention for achieving the above object is a pump cell unit for generating a high voltage through a plurality of pump cells, and the magnitude of the output voltage and the first reference voltage and the second reference voltage of the pump cell unit A dual comparator for comparison, a voltage level classifier for determining a range of output voltages according to an output result of the double comparator, and outputting a specific code form, three clock signals having rising edges at different points in time, and the voltage levels A voltage change determiner configured to receive an output signal of a classification unit and output a range of an output voltage at a first reference time point and an output voltage at a second reference time point, and specify one of the plurality of pump cells according to an output value of the voltage change determiner And a pump cell operation signal output unit configured to output an enable signal for operating the pump cell.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a graph illustrating a change state of an output voltage of a high voltage generator with time.

The X axis is the time axis, and the Y axis represents the output voltage HV_out. It is a section in which the output voltage HV_out transitions during the predetermined time Ts, and is a section in which the output voltage HV_out is stabilized during the subsequent section Tn, and the voltage level is changed to some extent.

In this case, according to the present invention, two output voltage levels different from each other are determined when the output voltage HV_out is greater than or equal to the first reference voltage Va, and less than the first reference voltage Va and greater than the second reference voltage Vb. The output voltage HV_out is classified into a case smaller than two reference voltages Vb so as to control the output voltage HV_out to have a level equal to or greater than the first reference voltage Va.

For example, when the level of the current output voltage HV_out is less than the second reference voltage Vb (X section), the pump cell is operated to be larger than the first reference voltage Va (Z section), or When the pump cell is smaller than one reference voltage Va and larger than the second reference voltage Vb (Y section), the pump cell is also operated to be larger than the first reference voltage Va (Z section). The numbers can be configured differently so that the desired voltage level can be reached without operating all of the multiple pump cells.

2 is a block diagram showing the configuration of a high voltage generator control device according to the present invention.

The high voltage generator control device compares the magnitude of the output voltage HV_out and the reference voltage Vref from the pump cell unit 200 including a plurality of pump cells, and outputs a voltage smaller than the reference voltage Vref. The voltage level classifying unit 220 analyzes and outputs the range of the voltage level currently output according to the output of the dual comparator 210 and the dual comparator 210 for comparing two reference voltages and magnitudes with another reference voltage. ). On the other hand, it includes a basic clock generator 230 for generating a basic period clock, a clock converter 240 for generating a plurality of clocks having different rising edges from the basic clock, the voltage level classification unit 220 The voltage change determination unit 250 and the output signal of the voltage change determination unit 250 which determine the change state of the output voltage HV_out at different times by using the output of the output and the clock change unit 240 as inputs. Accordingly, the pump cell operation signal output unit 260 for outputting an operation control signal for a specific pump cell.

The pump cell unit 200 includes a plurality of pump cells, the operation of which is controlled by a specific pump cell enable signal CKEN <n>. The output voltage HV_out is generated by the operation of the pump cell. In the present invention, the number of operation of the pump cell is controlled by adjusting the output of the pump cell enable signal CKEN <n> according to the change state of the output voltage HV_out. To control.

Now let's look at the detailed composition of each component and its operation.

3 is a circuit diagram illustrating in detail the configuration of the dual comparator 210.

The double comparator 210 may be configured such that the double comparator includes a first voltage divider 212 for varying the level of the output voltage of the pump cell part and a second reference voltage Vb by varying the level of the first reference voltage Va. A second voltage divider 214 for outputting the second voltage divider 214, a first comparer 216 for comparing magnitudes of the first reference voltage Va and the variable output voltage of the first voltage divider 212, and And a second comparison unit 218 comparing the magnitudes of the output voltages of the second reference voltage Vb and the first voltage divider 212.

The first reference voltage divider 212 includes resistors R1 and R2 connected in series between a terminal to which the output voltage HV_out is supplied and a ground voltage source, and a variable output voltage at the connection terminal of the resistors ( HV_out). The level of the output voltage HV_out may be changed by changing the configurations of the resistors R1 and R2.

The second reference voltage divider 214 includes resistors R3 and R4 connected in series between a terminal supplied with the first reference voltage Va and a ground voltage source, and a second reference voltage at the connection terminal of the resistors. (Vb) is output. The level of the second reference voltage Vb may be varied by changing the configurations of the resistors R3 and R4. That is, when the level difference between the level of the second reference voltage Vb and the first reference voltage Va is smaller, finer control can be achieved.

The first comparator 216 receives the first reference voltage Va as the non-inverting terminal + and inverts the output voltage HV_out having a variable level from the first voltage divider 212. And an OP amplifier inputted to the OP amplifier. When the variable output voltage HV_out is greater than the first reference voltage Va, the output signal Vaa becomes low level, and the first reference voltage If it is smaller than Va), the output signal Vaa becomes a high level.

Similarly, the second comparator 218 receives the second reference voltage Vb as the non-inverting terminal + and inverts the output voltage HV_out having a variable level from the first voltage divider 212. And an op amp inputted through-), wherein the output amplifier Vbb becomes low when the variable output voltage HV_out is greater than the second reference voltage Vb, and the second reference voltage. If it is smaller than Vb, the output signal Vbb is at a high level.

In this case, in order to supply a more stable first reference voltage Va, the first reference voltage Va is input to the non-inverting terminal, and the inverting terminal and the output terminal are connected to each other to be applied to the second voltage divider 214. It may further include an OP amplifier for outputting a reference voltage. here

The output result of the double comparison unit 210 as described above is as follows.

When the variable output voltage HV_out is greater than the first reference voltage Va, the first output signal Va and the second output signal Vbb become low level values. (Z section in Fig. 1)

When the variable output voltage HV_out is less than the first reference voltage Va and greater than the second reference voltage Vb, the first output signal Vaa becomes a high level value and the second output signal Vbb is low. It is a level value. (Y section in Fig. 1)

When the variable output voltage HV_out is smaller than the second reference voltage Vb, the first output signal Vaa and the second output signal Vbb become high level values. (X section in Fig. 1)

4 is a circuit diagram showing the configuration of the voltage level classification unit 220 in detail.

The voltage level classification unit 220 may include a first code output unit 222 outputting a first code X indicating a case in which the output voltage of the pump cell is smaller than a second reference voltage, and an output voltage of the pump cell. The second code output unit 224 for outputting a second code (Y) indicating the case of less than the first reference voltage and greater than the second reference voltage, and the case where the output voltage of the pump cell is greater than the first reference voltage And a third code output unit 226 for outputting a third code Z indicating.

The first code output unit 222 includes a first AND gate A222 that receives a first output signal Vaa and a second output signal Vbb from the dual comparator 210, and a second The code output unit 224 includes a second AND gate A224 to which the first output signal Vaa and the inverted second output signal / Vbb are input, and the third code output unit 226 is inverted. And a third AND gate A226 for inputting the first output signal / Vaa and the inverted second output signal / Vbb. In this case, the second code output unit 224 may further include a first inverter IV222 for inverting the second output signal Vbb, and the third code output unit 226 may include the first output signal Vaa. May include a second inverter IV224.

Therefore, when the variable output voltage HV_out is smaller than the first reference voltage Va and the second reference voltage Vb, the first output signal Vaa and the second output signal Vbb are high level values. Only the first code X, which is an output signal of the first AND gate A222, becomes high level.

In addition, when the variable output voltage HV_out is less than the first reference voltage Va and greater than the second reference voltage Vb, the first output signal Vaa is a high level value and the second output signal Vbb. Since is a low level value, only the second code Y, which is an output signal of the second AND gate A224, becomes a high level.

In addition, when the variable output voltage HV_out is greater than the first reference voltage Va, the third AND gate A226 because the first output signal Vaaa and the second output signal Vbb are low level values. Only the third code Z, which is an output signal of, becomes a high level.

In summary, the code XYZ indicating the state of the current output voltage HV_out is generated through the dual comparator 210 and the voltage level classifier 220. That is, if the code XYZ is (100), the variable output voltage HV_out is smaller than the second reference voltage Vb. If the code XYZ is 010, the variable output voltage HV_out is zero. If it is less than the first reference voltage Va and is greater than the second reference voltage Vb, and if the code XYZ is (001), the variable output voltage HV_out is greater than the first reference voltage Vb.

5 is a circuit diagram illustrating in detail the configuration of the clock converter 240.

The clock converter 240 receives the base clock from the base clock generator 230 and generates three clocks Q1, Q2, and Q3 having different rising edges. That is, the first clock signal Q1 having the rising edge at the same time as the base clock signal by receiving the base clock signal, the second clock signal Q2 having the rising edge at the falling edge of the base clock signal, and the first clock signal The third clock signal Q3 having the high level value is generated in the period where the clock signal and the second clock signal become the low level.

The clock converter 240 may include a first JK flip-flop 242 synchronized with a base clock and outputting a first clock Q1, and a second clock Q2 synchronized with an inverted basic clock and outputting a second clock Q2. 2 JK flip-flop 244, and NOR gate 246 for outputting the third clock (Q3) by the negative logic sum of the output of the first and second JK flip-flops (242, 244).

When the JK flip-flop inputs a high level signal to each input terminal (ie, J = H, K = H), the previous storage contents are output in complementary form, and the operation is activated in the rising edge section of the input clock. .

A waveform of the output clock Q1 of the first JK flip-flop 242 will be described with reference to FIG. 6.

The high level signal is input to each input terminal of the first JK flip-flop 242, and the basic clock signal CLK <0> is input.

The flip-flop is operated at the rising edge t1 of the basic clock signal, and the operation is to store the previous storage contents in complementary form. Therefore, when the initial value is low level, the flip-flop is shifted to the high level at the time t1.

 Since the flip-flop does not operate at the falling edge t2 of the basic clock signal, the previous high level state is maintained.

Since the flip-flop operates again at the rising edge t3 of the basic clock signal, it transitions to the low level, which is a complementary state to the previous state.

In this way, the first clock Q1 having a double cycle than the base clock is output.

Next, the second clock Q2 which is the output of the second JK flip-flop 244 will be described.

The high level signal is input to each input terminal of the second JK flip-flop 244, and the basic clock signal CLK <0> is input in an inverted form.

Since the basic clock signal CLK <0> is input in an inverted form, the flip-flop does not operate even on the rising edge t1 of the basic clock signal, but operates on the falling edge t2, which is stored in the previous storage. Is stored in complementary form, and when the initial value is low level, the transition to high level occurs at time t2.

Since the flip-flop does not operate at the rising edge t3 of the basic clock signal, the previous high level state is maintained.

Since the flip-flop operates again at the falling edge t4 of the basic clock signal, it transitions to the low level, which is a complement form of the previous state.

In this way, when compared to the first clock Q1, the second clock Q2 having a period twice as long as the basic clock is output while being delayed in time by the period T in which the basic clock signal becomes a high level.

Next, since the third clock Q3 negates the first clock Q1 and the second clock Q2, when both the first clock Q1 and the second clock Q2 are at a low level, as shown in FIG. A clock signal is generated that generates a high level pulse. Therefore, after the high level pulse is applied to both the first clock Q1 and the second clock Q2, the high level pulse is applied.

7 is a circuit diagram showing in detail the configuration of the voltage change determination unit 250.

The high voltage generator control device of the present invention controls the operation of the pump cell by comparing the voltage state when a specific time is compared with the voltage state when a certain time elapses therefrom, and thus compares the voltage state by time. To this end, voltage states are compared based on clock signals of the clock converter 240 having high level pulses at different points in time.

To this end, a first pass circuit for passing data in synchronization with the first clock signal Q1, a third pass circuit for passing data in synchronization with the second clock signal Q2, and a third clock signal Q3 in synchronization with the first clock signal Q1 And a second pass circuit for passing data passed through the first pass circuit, and a fourth pass circuit for passing data passed through the third pass circuit in synchronization with the third clock signal Q3.

On the other hand, the configuration of the pass circuit is shown in FIG.

The pass circuit includes a transfer gate consisting of an NMOS gate operated by a clock signal and a PMOS gate operated by a signal inverted by a clock signal. The pass circuit is enabled by a high level clock signal and transfers an input signal to an output terminal.

Since each pass circuit separates and transmits each code that is an output of the voltage level classification unit 220 from each other, the first through fourth pass circuits and the second code that pass the first code X of the output codes. A fifth to eighth pass circuit for passing Y) and a ninth to twelfth pass circuit for passing the third code (Z).

The first pass circuit and the third pass circuit have high-level pulses in different sections, and the time difference is as long as the section T of FIG. Therefore, the change state of each code can be checked by the time difference. That is, although the first code X is initially at a high level, after a period of time T passes, the first code X is at a low level and the second code Y or the third code Z is at a high level. Can be a high level.

Since the second pass circuit and the fourth pass circuit are synchronized by the third clock Q3, the data passing through the first pass circuit and the third pass circuit passes at the same time.

The voltage change determination unit 250 includes a logic circuit unit 252 for identifying and outputting a change state for each code. The logic circuit unit 252 outputs the output data of any one of the second, sixth and tenth pass circuits indicating the state of the pump cell output voltage at the first reference time point, and at the second reference time point. The output data of any one of the fourth, eighth and twelfth pass circuits representing the state of the pump cell output voltages is ANDed and the output data state at the first reference time point and the second reference time point are ANDed. Outputs a plurality of state data indicating the state of the output voltage at.

To this end, the logic circuit unit 252 inputs the first code X which has passed through the first and second pass circuits and the first code X which has passed through the third and fourth pass circuits as an input, and outputs an output signal ( A first AND gate, which outputs A1), a first code X which has passed through the first and second pass circuits, and a second code Y which has passed through the seventh and eighth pass circuits as inputs, and output signal ( The second AND gate outputting A2), the first code X passed through the first and third pass circuits, and the third code Z passed through the eleventh and twelfth pass circuits are inputted, and the output signal ( A third AND gate for outputting A3), the second code Y passing through the fifth and sixth pass circuits and the first code X passing through the third and fourth pass circuits as inputs; The fourth AND gate for outputting the output signal A4, the second code Y passing through the fifth and sixth pass circuits, and the second code Y passing through the seventh and eighth pass circuits are input. Fifth AND for outputting output signal A5 Sixth AND for inputting the second code Y passing through the second, fifth and sixth pass circuits, and the third code Z passing through the eleventh and twelfth pass circuits, and outputting an output signal A6. A gate, the third code Z passing through the ninth and tenth pass circuits and the first code X passing through the third and fourth pass circuits as inputs, and outputting an output signal A7. A third code Z which has passed through the seventh AND gate, the ninth and tenth pass circuits, and a second code Y which has passed through the seventh and eighth pass circuits as inputs, and outputs an output signal A8. The third code Z, which has passed through the eighth AND gate, the ninth and tenth pass circuits, and the third code Z, which has passed through the eleventh and twelfth pass circuits, is input and outputs an output signal A9. And a ninth AND gate.

The output result of the logic circuit unit 252 is shown in Table 1.

Cj Cj + 1 NODE 100 100 A1 100 010 A2 100 001 A3 010 100 A4 010 010 A5 010 001 A6 001 100 A7 001 010 A8 001 001 A9

For example, when the code XYZ is '100' at the past time point Cj, that is, when the first code X is at a high level, the output signal A1 is '100' even at the current time point Cj + 1. ) Is high level, and if the code XYZ is '001' at the past time point Cj, that is, if the third code Z is at the high level, output is '010' at the current time point Cj + 1. The signal A8 goes high. At this time, according to the present invention, if the output signal A1 is at a high level, since the X section of FIG. 2 is continued, a control operation to increase the number of operations of the pump cell is required, and if the output signal A8 is at a high level, the Z section is required. Since the voltage has dropped to the interval from to Y, a control operation for increasing the number of operations of the pump cell is required, but the number of operations will be at least as compared with the case where the previous output signal A1 is at a high level.

Accordingly, the number of operation of the pump cell can be controlled according to the voltage level of the output signals A1 to A9. For example, in the case of three pump cells, a method of controlling the operation number will be described.

Cj Cj + 1 NODE  Pump cell operation count 100 100 A1 3 100 010 A2 2 100 001 A3 0 010 100 A4 3 010 010 A5 3 010 001 A6 0 001 100 A7 3 001 010 A8 One 001 001 A9 0

In the case of the output signal A1, as described above, since the voltage level is low, all three pump cells are operated. When the current state is in the Z section, the operation of the pump cell is stopped. In general, the most frequent case is a case in which the voltage level in the Z section is changed to the Y section in which the voltage level is partially reduced (A8). In this case, only one pump cell is operated.

9 is a circuit diagram showing the configuration of the pump cell operation signal output unit 260 in detail.

The pump cell operation signal output unit 260 receives a plurality of state data from the voltage change determination unit 250 and at least three or more pumps when the output voltage of the pump cell unit is less than or equal to the second reference voltage at a second reference time point. The first control signal for operating the cell is output, and the output voltage of the pump cell portion is less than or equal to the second reference voltage at a first reference point, and the output voltage of the pump cell portion is greater than or equal to the second reference voltage and less than or equal to the first reference voltage at the second reference point. In the case of the range of to output a second control signal for operating at least two pump cells, the output voltage of the pump cell portion at the first reference time is more than the first reference voltage, the output voltage of the pump cell portion at the second reference time When the second reference voltage is greater than or equal to the first reference voltage, a third control signal for operating at least one pump cell is output, and the pump cell part is provided at the second reference time point. When the output voltage of the first reference voltage or more includes a first logic circuit portion 262 for outputting a fourth control signal for stopping the operation of the pump cell.

The first logic circuit unit 262 is configured to input state data indicating that the output voltage of the pump cell unit is less than or equal to the second reference voltage at the second reference time, and outputs the first control signal. And state data indicating that an output voltage of the pump cell unit is less than or equal to a second reference voltage at a first reference time, and an output voltage of the pump cell unit is in a range from a second reference voltage to a first reference voltage or less at a second reference time. A second logical sum gate configured to be an input and outputting the second control signal, and the output voltage of the pump cell portion is greater than or equal to the first reference voltage at the first reference point, and the output voltage of the pump cell portion is the second reference point at the second reference point; A third logical sum gate configured to input state data indicating that the voltage is in a range of more than a first reference voltage and outputting the third control signal; The condition data 2 output voltage pump cell unit at the reference point, which indicates that more than a first reference voltage input and a fourth OR gate for outputting the fourth control signal.

Each OR gate serves as a buffer when each input signal is one.

 Accordingly, the first logic circuit unit 262 may include a first control signal B1 indicating a case of driving at least three pump cells, a second control signal B2 indicating a case of driving at least two pump cells, and a pump. A third control signal B3 indicating a case in which at least one cell is driven and a fourth control signal B4 indicative of a case in which the pump cell is not driven are output.

In addition, the pump cell operation signal output unit 260 may include a second logic circuit unit 264 that receives the control signals B1 to B4 of the first logic circuit unit 262 to determine which pump cell to operate. do.

The second logic circuit unit 264 receives the first to fourth control signals B1 to B4 to operate the first pump cell control signal C1 and the second pump cell to operate the first pump cell of the pump cell unit. Outputs a second pump cell control signal C2 for activating the second pump, a third pump cell control signal C3 for operating the third pump cell, and a fourth pump cell control signal C4 for stopping the operation of the pump cell.

To this end, the second logic circuit unit 264 may include a first logic sum gate configured to input first to third control signals B1 to B3 and output the first pump cell control signal C1, and the first logic circuit gate 264. And a second AND gate for inputting second control signals B1 and B2 and outputting the second pump cell control signal C2, and inputting the first control signal B1 to the third pump cell. And a second buffer configured to output the control signal C3, and a second buffer configured to output the fourth pump cell control signal as the input of the fourth control signal.

Therefore, when any one of the first to third control signals B1 to B3 is at a high level, at least one pump cell must be operated, thereby generating the first pump cell control signal C1. In addition, when any one of the first and second control signals B1 and B2 is at a high level, at least two pump cells should be operated, so that not only the first pump cell control signal C1 but also the second pump cell control signal ( C2) is generated. In addition, when only the first control signal B1 is at a high level, all three pump cells must be operated to generate the third pump cell control signal C3. At this time, when the fourth control signal B4 is at the high level, the fourth pump cell control signal C4 for stopping the operation of all the pump cells is generated.

In addition, the pump cell operation signal output unit 260 receives the pump cell control signals C1 to C4, which are outputs of the second logic circuit unit 264, to enable an enable signal CKEN <2: 0>), and includes a third logic circuit portion 266.

The third logic circuit unit 266 receives the first to fourth pump cell control signals C1 to C4 and applies the first pump cell enable signal CKEN <0> applied to the first pump cell of the pump cell unit. The second pump cell enable signal CKEN <1> for operating the second pump cell and the third pump cell enable signal CKEN <2> for operating the third pump cell are output.

To this end, the third logic combination unit 266 inputs a signal inverting the fourth pump cell control signal C4 and an enable signal EN for operating the pump cell operation signal output unit 260. A second AND gate, a second pump cell control signal C1 and an output signal of the first AND gate, and the first pump cell enable signal CKEN <0> is output; And a third AND that receives the AND gate, the second pump cell control signal C2 and the output signal of the first AND gate, and outputs the second pump cell enable signal CKEN <1>. A gate and a fourth logical gate including the third pump cell control signal C3 and the output signal of the first AND gate, and outputting the third pump cell enable signal CKEN <2>; Include.

The first AND gate outputs a low level signal when the control signal C4 is at a high level, that is, when all the pump cells are not operated. Therefore, the second to fourth AND gates output low level enable signals. As a result, the pump cell is not operated. However, when the control signal C4 is at a low level, a signal for enabling a specific pump cell is output according to the voltage level of each control signal C1 to C3.

According to the above-described configuration of the present invention, an object of the present invention is to provide a high voltage generator control device capable of varying the number of pump cells operated according to the level of the high voltage output. In particular, it has a configuration in which the output voltage and the reference voltage to be compared are two, and thus finer control is possible.

Claims (26)

  1. A pump cell section generating high voltage through a plurality of pump cells,
    A dual comparison unit comparing the magnitude of the output voltage of the pump cell unit with a first reference voltage and a second reference voltage;
    A voltage level classification unit for determining a range of an output voltage according to an output result of the double comparator and outputting the specific code form;
    A voltage change determination unit receiving three clock signals having rising edges at different time points and an output signal of the voltage level classification unit and outputting a range of an output voltage at a first reference time point and an output voltage at a second reference time point; ,
    And a pump cell operation signal output unit configured to output an enable signal for operating a specific pump cell among the plurality of pump cells according to the output value of the voltage change determination unit.
  2. The apparatus of claim 1, wherein the pump cell unit includes a first pump cell, a second pump cell, and a third pump cell supplying voltages of the same level to each other.
  3. The apparatus of claim 1, wherein the dual comparator comprises: a first voltage divider configured to vary a level of an output voltage of the pump cell part;
    A second voltage divider configured to output the second reference voltage by varying a level of the first reference voltage;
    A first comparator comparing the magnitudes of the variable output voltages of the first reference voltage and the first voltage divider;
    And a second comparator for comparing the magnitudes of the variable output voltages of the second reference voltage and the first voltage divider.
  4. The method of claim 3, wherein the first comparator receives the first reference voltage as a non-inverting terminal and receives the variable output voltage as an inverting terminal to output a low level signal when the first reference voltage is smaller. A high voltage generator control device comprising an op amp for outputting a high level signal when the 1 reference voltage is greater.
  5. The method of claim 3, wherein the second comparator receives the second reference voltage as the non-inverting terminal and the output voltage as the inverting terminal to output a low level signal when the second reference voltage is smaller, and the second reference voltage is A high voltage generator control device comprising: an op amp that outputs a high level signal when larger.
  6. 4. The OP amplifier of claim 3, wherein the dual comparator receives the first reference voltage as a non-inverting terminal, and the inverting terminal and the output terminal are connected to each other to output an first reference voltage to be applied to the second reference voltage divider. High voltage generator control device further comprising.
  7. 4. The apparatus of claim 3, wherein the voltage level classification unit comprises: a first code output unit configured to output a first code indicating a case where an output voltage of the pump cell is smaller than a second reference voltage;
    A second code output unit configured to output a second code indicating a case where an output voltage of the pump cell is less than a first reference voltage and greater than a second reference voltage;
    And a third code output unit configured to output a third code indicating a case where an output voltage of the pump cell is greater than a first reference voltage.
  8. The method of claim 7, wherein the first code output unit comprises a first AND gate for outputting the first code, the output voltage of the first comparator and the second comparator of the dual comparator and the output of the first code. High voltage generator control.
  9. The display device of claim 7, wherein the second code output part includes a signal obtained by inverting the output voltage of the second comparator of the double comparator and a second AND gate configured to output the second code as an input voltage of the first comparator. High voltage generator control device characterized in that.
  10. The third code output unit of claim 7, wherein the third code output unit is configured to input a signal inverting the output voltage of the first comparator of the double comparator and a signal of inverting the output voltage of the second comparator, and output the third code. And a high voltage generator control device comprising an AND gate.
  11. The apparatus of claim 1, wherein the high voltage generator control device comprises: a basic clock generator configured to generate a basic clock signal;
    The first clock signal having the rising edge at the same time as the base clock signal, the second clock signal having the rising edge at the falling edge of the base clock signal, the first clock signal and the second clock signal are inputted. And a clock converter configured to generate a third clock signal having a high level value in a low level section.
  12. 12. The method of claim 11, wherein the clock converter comprises: a first JK flip-flop that is synchronized with the basic clock signal, inputs a high level voltage, and outputs the first clock signal;
    A second JK flip-flop in synchronization with the signal inverting the basic clock signal and receiving a high level voltage as an input and outputting the second clock signal;
    And a negative logic sum (NOR) gate for inputting the first clock signal and the second clock signal and for outputting the third clock signal.
  13. The display device of claim 7, wherein the voltage change determiner comprises: a first pass circuit configured to pass the first code of the voltage level classifier at a first reference time point;
    A third pass circuit for passing the first code at a second reference time point;
    A second pass circuit configured to pass data passing through the first pass circuit at a third reference time point later than the first and second reference time points;
    A fourth pass circuit for passing data passing through the third pass circuit at the third reference time point;
    A fifth pass circuit which passes the second code of the voltage level classification unit at the first reference time point;
    A seventh pass circuit for passing the second code at the second reference time point;
    A sixth pass circuit configured to pass data passing through the fifth pass circuit at the third reference time point;
    An eighth pass circuit for passing data passing through the seventh pass circuit at the third reference time point;
    A ninth pass circuit configured to pass the third code of the voltage level classification unit at the first reference time point;
    An eleventh pass circuit for passing the third code at the second reference time point;
    A tenth pass circuit configured to pass data passing through the ninth pass circuit at the third reference time point;
    And a twelfth pass circuit configured to pass data passing through the eleventh pass circuit at the third reference time point.
  14. The apparatus of claim 11, wherein the voltage change determiner comprises: a first pass circuit configured to pass data in synchronization with the first clock signal;
    A third pass circuit for passing data in synchronization with the second clock signal;
    A second pass circuit configured to pass data passed through the first pass circuit in synchronization with the third clock signal;
    And a fourth pass circuit configured to pass data passed through the third pass circuit in synchronization with the third clock signal.
  15. The display device of claim 13, wherein the voltage change determiner comprises: output data of any one of second, sixth, and tenth pass circuits indicating a state of the pump cell output voltage at the first reference time point;
    An output voltage at a first reference time point by ANDing the output data of any one of the fourth, eighth and twelfth pass circuits indicating the state of the pump cell output voltage at the second reference time point And a logic circuit section for outputting a plurality of state data representing the state of the and the state of the output voltage at the second reference time point.
  16. 16. The circuit according to claim 15, wherein the logic circuit unit is configured to output output data of any one of the second, sixth and tenth pass circuits, and one of the fourth, eighth and twelfth pass circuits. A high voltage generator control device comprising a plurality of AND gates for inputting output data.
  17. 16. The method of claim 15, wherein the pump cell operation signal output unit receives a plurality of state data from the voltage change determination unit at least at least three pump cells when the output voltage of the pump cell unit is less than the second reference voltage at the second reference time point And a first control signal for operating the high voltage generator.
  18. The pump cell operation signal output unit receives a plurality of state data from the voltage change determination unit, and the output voltage of the pump cell unit is less than or equal to the second reference voltage at a first reference time, and the pump at the second reference time. And a second control signal for operating at least two pump cells when the output voltage of the cell portion is in the range of more than the second reference voltage to less than the first reference voltage.
  19. The pump cell operation signal output unit receives a plurality of state data from the voltage change determination unit, and the output voltage of the pump cell unit is greater than or equal to the first reference voltage at a first reference time, and the pump at the second reference time. And outputting a third control signal for operating at least one pump cell when the output voltage of the cell portion is in the range of more than the second reference voltage to less than the first reference voltage.
  20. The method of claim 15, wherein the pump cell operation signal output unit receives a plurality of state data from the voltage change determination unit and stops the operation of the pump cell when the output voltage of the pump cell unit is greater than the first reference voltage at a second reference time point. And a fourth control signal outputting the high voltage generator control device.
  21. 16. The apparatus of claim 15, wherein the pump cell operation signal output unit receives a plurality of state data from the voltage change determination unit, and a first control signal for operating at least three pump cells and a second control for operating at least two pump cells. And a first logic combination portion for outputting a signal, a third control signal for operating at least one pump cell, and a fourth control signal for stopping operation of the pump cell.
  22. The first logical sum OR of claim 21, wherein the first logic combination unit is configured to input state data indicating that an output voltage of a pump cell unit is less than or equal to a second reference voltage at the second reference time, and output the first control signal. ) Gates,
    Input state data indicating that an output voltage of the pump cell unit is less than or equal to a second reference voltage at the first reference time, and that an output voltage of the pump cell unit is in a range from the second reference voltage to less than the first reference voltage at the second reference time. A second logical sum gate configured to output the second control signal;
     Input state data indicating that the output voltage of the pump cell unit is greater than or equal to the first reference voltage at the first reference time, and the output voltage of the pump cell unit is greater than or equal to the second reference voltage and less than the first reference voltage at the second reference time. A third logical sum gate configured to output the third control signal;
    And a fourth logic sum gate configured to input state data indicating that an output voltage of the pump cell unit is equal to or greater than a first reference voltage at the second reference time and output the fourth control signal.
  23. 23. The apparatus of claim 22, wherein the pump cell operation signal output unit receives the first to fourth control signals to operate the first pump cell control signal and the second pump cell to operate the first pump cell of the pump cell unit. And a second logic combination portion for outputting a two pump cell control signal, a third pump cell control signal for operating the third pump cell, and a fourth pump cell control signal for stopping the operation of the pump cell. Device.
  24. 24. The gate driving circuit of claim 23, wherein the second logic combiner comprises: a first logic sum gate configured to input the first to third control signals and output the first pump cell control signal;
    A second logical sum gate configured to input the first and second control signals and output the second pump cell control signal;
    A first buffer configured to input the first control signal and output the third pump cell control signal;
    And a second buffer configured to receive the fourth control signal as an input and output the fourth pump cell control signal.
  25. The method of claim 23, wherein the pump cell operation signal output unit receives the first to fourth pump cell control signals to receive a first pump cell enable signal and a second pump cell applied to the first pump cell of the pump cell unit. And a third logic combination unit for outputting a second pump cell enable signal for operating and a third pump cell enable signal for operating the third pump cell.
  26. The gate driving circuit of claim 25, wherein the third logic combination unit comprises: a first AND gate configured to input a signal inverting the fourth pump cell control signal and an enable signal for operating the pump cell operation signal output unit;
    A second AND gate that receives the first pump cell control signal and the output signal of the first AND gate and outputs the first pump cell enable signal;
    A third AND gate which receives the second pump cell control signal and the output signal of the first AND gate and outputs the second pump cell enable signal;
    And a fourth AND gate for inputting the third pump cell control signal and the output signal of the first AND gate, and outputting the third pump cell enable signal.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050101687A (en) * 2004-04-19 2005-10-25 주식회사 하이닉스반도체 High voltage generation circuit
JP2008001000A (en) * 2006-06-23 2008-01-10 Sharp Corp Image processing apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050101687A (en) * 2004-04-19 2005-10-25 주식회사 하이닉스반도체 High voltage generation circuit
JP2008001000A (en) * 2006-06-23 2008-01-10 Sharp Corp Image processing apparatus

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* Cited by examiner, † Cited by third party
Title
공개특허공보 10-2005-0101687호
공개특허공보 특2001-0001583호

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