KR100812608B1 - Apprataus for downlink and uplink adjustment between radio access station and relay station - Google Patents

Abstract

An apparatus for downlink and uplink matching between a Wibro BS(Base Station) and a Wibro RS(Relay Station) is provided to reduce production cost by using FPGA(Field Programmable Gate Array), clock, PLL(Phase Locked Loop), and power in common and improve system performance by reducing undesired clock noise. An apparatus for downlink and uplink matching between a Wibro(Wireless Broadband Internet) BS and a Wibro RS includes a repeater matching board(120) connected through a gate array and a connector(130) on the digital IF(Intermediate Frequency) board(100) of the Wibro BS. The gate array diverges a baseband signal and a block signal received in downlink into the BS digital IF board and the repeater matching board and transmits the diverged signals, and converts digital IF signals respectively received from the BS digital IF board and the repeater matching board in uplink into a baseband signal and transmits the converted signal.

Description

WiBro base station and relay period downlink and uplink matching device {APPRATAUS FOR DOWNLINK AND UPLINK ADJUSTMENT BETWEEN RADIO ACCESS STATION AND RELAY STATION}

1 is a diagram showing the configuration of a base station digital IF board and a repeater matching board.

2 illustrates a digital IF in downlink / uplink in a base station digital IF board.

3 is a diagram illustrating digital IF in downlink / uplink in a repeater matching board.

4 is a diagram showing the configuration of a base station digital IF board and a repeater matching board according to the present invention;

5 is a diagram illustrating a digital IF at downlink / uplink in a base station digital IF board and a repeater matching board according to the present invention.

Explanation of symbols on the main parts of the drawings

100: base station digital IF board 110: FPGA

120: repeater registration board 130: connector

140: DUC 150: DAC

160: ADC 170: DDC

The present invention relates to a structure and method for matching down-link and up-link with a WiBro base station.

WiBro (Wireless Broadband Internet) is a high-speed Internet service that enables users to access various types of information and contents by accessing the Internet at high speed (about 1Mbps) anytime and anywhere while using mobile devices. That is, it is a concept of extending indoor wired high-speed Internet service so that it can be used outdoors.

This WiBro service uses the 2.3GHz frequency band to guarantee seamless wireless Internet service within a cell radius of 1Km and at least 60Km / H when moving, and is a new service that can use wireless Internet at a lower cost. It is developed to support the mobility of 1Mbps per subscriber and the serviceability of 100Km / H and the speed of 3Mbps.

When the WiBro service starts, connecting a device like a laptop wireless LAN card or a USB wireless LAN card allows you to enjoy movies, play online games or surf the web in the office or on the road, as if you are surfing the Internet at the office. .

Hereinafter, the configuration of the digital IF board and the repeater matching board of the WiBro base station for the WiBro service will be described in more detail.

1 is a view showing the configuration of the base station digital IF board and the repeater matching board, Figure 2 is a diagram showing the digital IF when downlink / uplink in the base station digital IF board, Figure 3 is a downlink / uplink in the repeater matching board A diagram showing digital IF at link time.

As shown, the down-link transmits a baseband digital IF (DIFB) signal to a 14-bit I / Q signal and a clock signal of 20 MHz received from a baseband signal processing and control assembly (PCA). ) To the FPGAs 11 and 21 of the board 10 and the repeater matching board 20.

Accordingly, the signals output from the FPGAs 11 and 21 of the base station digital IF board 10 and the repeater matching board 20 are respectively converted into a digital up converter (DUC) 12 and 22 and a digital to analog converter (DAC) ( 13, 23) is output to the RF unit.

The uplink transmits a 20 MHz baseband I / Q signal received from the FPGAs 11 and 21 of the base station digital IF board 10 and the repeater matching board 20 to the channel card.

That is, the signals inputted from the RF unit to the base station digital IF board 10 and the repeater matching board 20 are analog to digital converter (ADC) 14, 24 and digital down converter (DDC) 15 and 25, respectively. It is transmitted to the FPGA (11, 21) through the channel card output.

In other words, the base station Digital IF board 10 receives a 10 MHz reference clock signal from the outside, locks it with a 320 MHz voltage controlled SAW oscillator (VCSO) clock, and distributes the same to each device.

In this case, the down-link converts a baseband digital signal into a digital IF (11MHz, 20MHz, 29MHz) signal using Fine NCO. The signal converted to the digital IF is 80MHz up-converted using Coarse NCO and then converted to the final digital IF (91MHz, 100MHz, 109MHz) signal as shown in FIG. 2.

In contrast to down-link, up-link converts digital IF (91MHz, 100MHz, 109MHz) signal received from RF part to 80MHz down-conversion using Coarse NCO and then digital IF (11MHz, 20MHz, 29MHz) to the signal. The converted digital IF (11MHz, 20MHz, 29MHz) signals are converted to baseband digital signals using Fine NCO and transmitted to the channel card.

On the other hand, the repeater matching board 20 is synchronized to the 400MHz VCSO clock and then distributed to each device (Device).

In this case, the down-link converts the baseband digital signal into a digital IF (16MHz, 25MHz, 34MHz) signal using Fine NCO. The signal converted to digital IF is converted to the final digital IF (116MHz, 125MHz, 134MHz) signal by 100MHz up-conversion using Coarse NCO.

In addition, the uplink (up-link) is 100MHz down-conversion of the digital IF (66MHz, 75MHz, 84MHz) signal received from the RF unit using Coarse NCO and then converted into a digital IF (-16MHz, -25MHz, -34MHz) signal. To convert. The converted digital IF (-16MHz, -25MHz, -34MHz) signals are converted to baseband digital signals using Fine NCO and transmitted to the channel card.

In other words, the clock source used for the base station digital IF board and the repeater matching board are configured differently, and the FPGA, power supply (3.3V, 1.2V), etc. need to be doubled. The problem arises.

Accordingly, an object of the present invention is to solve the above problems, by using a field matching gate array (FPGA) by detachably configuring the repeater matching board on the base station digital IF board, the downlink and uplink matching structure of the base station and repeater It provides a WiBro base station and a relay downlink and uplink matching device for common use of clock, phase locked loop (PLL), and power.

According to an aspect of the WiBro base station and the relay period downlink and uplink matching device according to the present invention for achieving the above object, the WiBro base station includes a repeater matching board connected through a gate array and a connector on the digital IF board of the base station; The gate array branches and transmits the baseband signal and the clock signal received during downlink to the base station digital IF board and the repeater matching board, and the base station digital IF for uplink. The digital IF signal received from the board and the repeater matching board, respectively, is converted to the baseband signal and transmitted.

In particular, the gate array uses a field programmable gate array (FPGA).

The gate array converts the digital IF signals received from the base station digital IF board and the repeater matching board to the baseband signal by summing and down-converting the respective digital IF signals during uplink. do.

In particular, the base station digital IF board and the repeater matching board use a single clock source and a power supply in common, and are synchronized with a 400 MHz VCSO clock and then distributed to each device.

At this time, the base station digital IF board and repeater matching board converts the baseband digital signal into a digital IF signal using Fine NCO during downlink, and the converted digital IF signal is up-converted through Coarse NCO. Converts to a final digital IF signal, down-converts the digital IF signal received during uplink using the Coarse NCO, converts it to a digital IF signal, and converts the converted digital IF signal through the Fine NCO. It is converted into a baseband digital signal and transmitted.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, detailed descriptions of preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that reference numerals and like elements among the drawings are denoted by the same reference numerals and symbols as much as possible even though they are shown in different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

4 is a view showing the configuration of the base station digital IF board and repeater matching board according to the present invention, Figure 5 is a diagram showing the digital IF at the downlink / uplink in the base station digital IF board and repeater matching board according to the present invention .

As shown, in the present invention, the repeater matching board 120 is connected to the base station digital IF board 100, and in particular, the repeater matching board 120 is connected to the FPGA 110 through a connector 130. Lose.

That is, as shown in FIG. 4, the down-link is a base station digital IF board 100 and a repeater matching board 120 for the 20-bit 14-bit I / Q signal and the clock signal received from the channel card in the FPGA 110. Branch to provide.

In other words, the signals output from the FPGA 110 of the base station digital IF (DIFB) board 100 are branched, respectively, so that the base station digital IF (DIFB: digital IF block) board 100 and the repeater matching board 120 are separated. It is output to the RF unit through the DUC (Digital Up Converter) (140a, 140b) and DAC (Digital to Analog Converter) (150a, 150b).

In addition, the up-link includes summing and down-conversion of the digital IF signal received from the base station digital IF board 100 and the digital IF signal received from the repeater matching board 120 in the FPGA 110. Down-conversion) is used to convert the baseband I / Q signal and convert the baseband I / Q signal to the channel card.

That is, signals inputted from the RF unit to the base station digital IF board 100 and the repeater matching board 120 are analog to digital converters (ADCs) 160a and 160b and digital down converters (DDCs) 170a and 170b, respectively. It is transmitted to the FPGA 110 through the channel card is output.

In particular, the signal input to the repeater matching board 120 is transmitted to the FPGA 110 through a connector 130 and output to the channel card.

In other words, the base station digital IF board 100 and the repeater matching board 120 use a clock and a PLL together, and synchronize with a 400 MHz VCSO clock and distribute them to each device.

At this time, the down-link converts the baseband digital signal to a digital IF (16 MHz, 25 MHz, 34 MHz) signal using Fine NCO, and the signal converted to digital IF is 100 MHz up-converted using Coarse NCO. Up-conversion to the final digital IF (116MHz, 125MHz, 134MHz) signals.

In addition, the uplink (down-conversion) of the digital IF (66MHz, 75MHz, 84MHz) signal received from the RF unit using Coarse NCO, and then the digital IF (-16MHz, -25MHz,- 34MHz) signal, and converted digital IF (-16MHz, -25MHz, -34MHz) signal is converted to baseband digital signal using Fine NCO and transmitted to channel card.

As a result, when two or more clock sources are used, harmonic components between clock sources may be generated, which may cause unwanted noise. However, in the present invention, the base station digital IF board 100 and the repeater matching board 120 may have a single 100 MHz. The clock can be used for signal conversion. That is, the base station digital IF signal and the repeater signal can be used together using one clock and a PLL.

In the above, specific preferred embodiments of the present invention have been illustrated and described. However, the present invention is not limited to the above-described embodiment, and various modifications can be made by any person having ordinary skill in the art without departing from the gist of the present invention attached to the claims. will be.

According to the present invention, a common use of FPGA, clock & PLL, and power supply can reduce the manufacturing cost, and the common use of clock and PLL can reduce unwanted clock noise, thereby improving system performance. There is.

Claims (5)

In the WiBro base station and the relay period downlink and uplink matching device, A repeater matching board connected through a connector and a gate array on the digital IF board of the WiBro base station, The gate array branches and transmits the baseband signal and the clock signal received in the downlink to the base station digital IF board and the repeater matching board, and transmits the baseband digital IF board in the uplink. WiBro base station and repeater downlink and uplink matching device, characterized in that for converting each digital IF signal received from the repeater matching board to the baseband signal and transmitted. The method of claim 1, And the gate array is a Field Programmable Gate Array (FPGA). The method of claim 1, The gate array, WiBro base station, characterized in that the digital IF signal received from the base station digital IF board and the repeater matching board in the up-link (Summing) and down-conversion to convert to a baseband signal And relay downlink and uplink matching devices. The method of claim 1, The base station digital IF board and the repeater matching board use a single clock source and a power supply in common, and synchronize them with a 400 MHz VCSO clock and distribute them to each device. Uplink Matching Device. The method of claim 4, wherein The base station digital IF board and repeater matching board converts the baseband digital signal to a digital IF signal using Fine NCO during downlink, and the converted digital IF signal is up-converted through a coarse NCO to the final digital. Converts to an IF signal, down-converts the digital IF signal received during uplink using the Coarse NCO, and then converts the digital IF signal to a digital IF signal, and converts the converted digital IF signal to a baseband through the Fine NCO. WiBro base station and relay period downlink and uplink matching device, characterized in that for converting and transmitting the digital signal.

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