KR100777753B1 - Data processing using a coprocessor - Google Patents

Abstract

The data processing system using the main processor 8 and the coprocessor 10 loads into the coprocessor 10 various numbers of data values that depend on the alignment and also performs on the operands in the loaded data words. Provide a coprocessor load instruction (USALD) that specifies the data processing operations to be generated and generate the resulting data words. The coprocessor processing operation specified in this manner may be a calculation of the sum of absolute differences with respect to the column of pixel byte values. The result of this calculation is accumulated in the accumulation register 22. Coprocessor memory 18 is installed within coprocessor 10 to provide coprocessor 10 with a local storage of frequently used operand values.

Sum of data processor, coprocessor, main processor, load instruction, absolute difference

Description

DATA PROCESSING USING A COPROCESSOR}             

The present invention relates to a data processing system. In particular, the present invention relates to a data processing system incorporating a main processor and a coprocessor.

Data processing systems incorporating a main processor and a coprocessor are known. An example of such a data processing system is the Cambridge ARM Limited data processing system in the UK, which includes an ARM7 or ARM9 combined with a coprocessor such as a Piccolo coprocessor that performs the same functions as a dedicated digital signal operation. Provides the main processor. Another example of a coprocessor may be a floating point arithmetic coprocessor or the like.

Coprocessors are often used to provide additional functionality within a data processing system that is unnecessary in the base system, but are useful in certain cases when it is natural to have additional costs to provide a suitable coprocessor. In particular, the required data processing environment is those including digital signal processing such as video image manipulation. The amount of data that needs processing in such an application can be high. This is a problem to provide a data processing system that can solve the required processing amount and at the same time have a very low cost and low power consumption.

One way to handle such computationally intensive applications is to provide a dedicated digital signal processing circuit. Such a dedicated circuit may have a structure, in particular, configured to perform arithmetic processing at a very limited range but at very high speed. By way of example, multiple data channels may be configured to allow data to flow in and out of the associated circuit in parallel. Such a configuration may solve the problem of requiring a high data throughput, but the disadvantage is that the configuration is usually not variable. This invariability also means that the smallest changes required to implement the algorithm can require expensive corresponding hardware changes. This is generally compared with a general purpose processor designed to run a wide variety of different algorithms at first.

One aspect of the invention,

A main processor that performs data processing operations in response to program instructions;

At least one loaded data word therein connected to the main processor and responsive to a coprocessor load instruction of the main processor, the at least one defined by the coprocessor load instruction using the one or more loaded data words Coprocessor processing operations to provide operand data to generate at least one result data word,

In response to the coprocessor load instruction, varying the number of loaded data words loaded into the coprocessor, depending on whether the start address of the operand data in the one or more loaded data words is aligned with a word boundary. .

It can be seen that the present invention may be provided with a coprocessor having a very special function in a system including a general-purpose main processor. In particular, coprocessor load instructions may also perform data processing operations to be performed on the operands within the loaded data word to generate the resulting data word, which may yield significant advantages in terms of speed and code density. Such a coprocessor has a very special role in the system, but when combined with a general purpose main processor, such a combination can provide the desired increase in processing power while maintaining the capabilities of the general purpose processor and adapting to different algorithms and circumstances. It turned out.

Memory systems and bus structures are often set up to work properly only to make specific alignments based on their address base, but the desired operand values manipulated and used by the coprocessor may be different alignment values. In this way, to improve performance, the number of loading data words loaded into the coprocessor depends on the alignment value. As an example, it may be desirable to load eight 8-bit operands in response to a coprocessor load instruction using a word aligned 32-bit data word, which is equivalent to two data words, or word boundaries, if the operands are aligned on a word boundary. If the operands are not aligned, they may be achieved by three data words.

In particular, preferred embodiments of the present invention are examples in which a coprocessor memory is provided to locally store a data word to be used as an operand in combination with the loaded data word in the coprocessor. This configuration shows that, in the real world, when doing many calculations, very small subsets of data words are often needed to use in combination with very large sets of data words that are not often needed. . This feature exploits this by locally storing the frequently needed data words, thus advantageously reducing the data channel capacity required between the main processor and the coprocessor. Compared with conventional digital signal processing systems, it is usually more difficult to simply add more data channels between one main processor and one coprocessor as needed, since the main processor structure is limited by other factors. Do.

The performance of the system is improved in embodiments in which loaded data words retrieved from memory connected to the main processor are passed to the coprocessor without being stored in registers of the main processor. In this case, it will be appreciated that the main processor may provide the role of an address generator and a memory accessor for the coprocessor.

It is particularly convenient if the main processor has a register operative to store an address value indicating that the data word is loading into the coprocessor. This improves flexibility in the form of algorithms that may be supported by controlling the address pointer to the main processor.

It will be appreciated that the data words loaded and manipulated may have various widths. As an example, the data word may be a 32-bit data word containing four 8-bit operands each representing an 8-bit pixel value. However, it will be appreciated that data words and operands can have a wide variety of different sizes, such as 16 bits, 64 bits, 128 bits and the like.             

In many cases in real life, the alignment may change, but the alignment is generally the same for a large number of sequential accesses. In such a case, the preferred embodiment uses a register value in the coprocessor to specify which coprocessor responds to control the alignment between the data operand and the data word and how much the data word is loaded per coprocessor load instruction. May be stored.

While the coprocessor can perform a wide variety of processing operations on the operands in the loaded data words that depend on the individual system, the present invention provides sums of absolute differences between a plurality of operand values. It is particularly useful in systems where it is necessary to perform. Performing the sum of absolute differences for large amounts of data often represents an important part of the processing load that a general purpose processor requires when performing operations such as pixel block matching in image processing. By unloading most of the lower computations of the sum of the absolute differences into the coprocessor, the performance is significantly increased while still maintaining the flexibility of the general-purpose processor to use the sum of special-purpose absolute differences as part of a wide variety of different algorithms. .

The accumulation register is preferably configured to accumulate the sum of the calculated absolute differences within the coprocessor within the sum of absolute differences system. This cumulative register in the coprocessor is retrieved back into the main processor for further manipulation as needed, but retained locally in the coprocessor, to speed up the operation and transfer data between the coprocessor and the main processor. Can reduce the requirements.             

To enhance the role of the main processor as the address generator of the coprocessor, the coprocessor load instruction preferably includes an offset value applied to the address value stored as a pointer in the main processor. This offset value may optionally be used to update the pointer value before or after the pointer value is used.

In addition, as described above, the present invention provides a computer program product incorporating coprocessor load instructions. This computer program product may be in the form of a distributable medium such as a compact disk or a floppy disk, may be part of firmware embedded in the device, or may be downloaded dynamically via a network link or the like.

Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings in which:

1 is a view schematically showing the calculation of the sum of preferred absolute differences,

2 is a diagram schematically illustrating a combination of a main processor and a coprocessor,

3 is a flowchart schematically showing an example of a calculation form performed by the system of FIG.

4 is a diagram illustrating an example of four coprocessor load instructions.

5 through 7 provide further details of a coprocessor according to one embodiment.

1 shows the current block of pixels 2 which is desirable to find the best match in the reference image. The current block of pixels contains 8 * 8 blocks with 8 bit pixel byte values. The current block of the pixel 2 is compared with the reference block of the pixel 4 located at different vector displacements v from the current block of the pixel 2. At each angular vector displacement desired for testing for matching, the equation of the sum of the absolute differences shown in FIG. 1 is calculated. This equation determines the absolute difference between respective corresponding pixel values for the two blocks, and adds the 64 absolute difference values obtained above. Good image registration is generally represented by the sum of low absolute difference values. Inside an image data processing system such as one execution MPEG type processing, such sum calculation of the absolute difference is often required and may present a large processing overhead disadvantageously for general purpose processors.

2 shows a data processing system 6 having a main processor 8, a coprocessor 10, a cache memory 12, and a main memory 14. The main processor 8 includes a register bank 16 for storing general purpose register values that the main processor 8 may use. For example, this main processor 8 may be one of the main processors designed by ARM Limited of British Village.

The main processor 8 is connected to the cache memory 12 and serves to provide fast access to the data values required very often. The low speed but higher capacity main memory 14 is provided outside the cache 12.

The coprocessor 10 is connected to the coprocessor bus of the main processor 8 and executes certain operations in response to the coprocessor instructions received and executed by the main processor 8. Within the ARM architecture, load coprocessor instructions are provided to load data values into the coprocessor. The coprocessor 10 shown in FIG. 2 extends the functionality of such coprocessor load instructions and uses those instructions to perform certain predetermined processing operations on operand values in data words loaded into the coprocessor 10. Tell the coprocessor to run.

More specifically, the coprocessor 10 includes a coprocessor memory 18, an alignment register 20, an accumulation register 22, and a control and arithmetic function logic section 24. Sixteen 32-bit data words may be loaded into coprocessor memory 18 using specific coprocessor load instructions. Each of these 16 data words contains four 8-bit pixel values and corresponds to an 8 * 8 pixel block, which is the current block 2 shown in FIG. The pixel values in the current block 2 are the reference blocks representing the sum of the lowest absolute differences and corresponding to the best image match, using the sum of absolute differences having reference blocks obtained from different positions in the reference image. (4) will be compared as a block to find. Storing frequently used pixel values of the current block 2 in the coprocessor memory 18 is an efficient way of handling resources. Once the coprocessor memory 18 has been loaded by the current block 2, a particular coprocessor load instruction (USALD instruction) loads two or three data words into the coprocessor 10 to load this loaded data word. It is executed by the main processor 8 which serves to calculate the sum of the absolute difference values of the eight pixel operands within. In addition, the USALD instruction in the instruction stream of the main processor 8 triggers the control and arithmetic function logic section 24 to pass the necessary data from the cache 12 or the main memory 14 via the main processor 8. Coprocessor 10 (directly or in the form of one or more control signals) that controls the loading of the number of words and then performs a sum calculation of the absolute difference using these loaded values and the values from the coprocessor memory 14 Delivered. The alignment register 20 holds an alignment value preset by a coprocessor register load instruction executed by the main processor 8. The control and arithmetic function logic section 24, in response to this alignment value, loads two 32-bit data words if the operands are aligned by word boundaries or three 32-bit data words if there is no such alignment. do. On the side of the cache memory 12 of FIG. 2, eight desired pixel operand values stored inside the cache memory that are not aligned by the word boundary and the alignment offset of CR_BY0 are shown. In the example shown, three 32-bit data words are stored in one of the registers of register bank 16 and loaded into an address value [Rn] that points to the aligned word addressed as shown. When three 32-bit data words are retrieved, control and arithmetic function logic section 24 performs multiple operations to select the required operand from within the loaded data word according to the specified alignment value. The operand value extracted from the loaded data word consists of a sum of absolute differences that form part of the calculation shown in FIG. 1 using standard arithmetic processing logic such as an adder and a subtractor. It will be appreciated that in the example showing the eight pixel byte operand, it effectively represents a single column in the block comparison between the current pixelblock 2 and the reference pixel block 4 shown in FIG. In order to perform the full calculations shown in FIG. 1, eight such coprocessor load instructions need to be executed in sequence. The sum of the absolute differences calculated by each of these coprocessor instructions is accumulated in the accumulation register 22. Therefore, after executing all eight coprocessor load instructions that respectively specify the column sum of the absolute differences, the block sum of the absolute differences is performed and the result is stored in the accumulation register 22. The stored value may be returned to the main processor 8 by, for example, a main processor instruction for retreating a coprocessor register value to one of the registers in the register bank 16.

In the above example, the address pointer is held in a register of the register bank 16 which directly points to the start address of the first data word to be searched. However, the stored pointer value can be made up of an offset such as a 10-bit offset applied to the stored pointer value to indicate the actual address to be accessed. In some cases, it is convenient to use this additional offset to update the pointer value each time it is used. This allows the coprocessor load instruction to advance effectively through the data specifying the reference image by an appropriate amount, so that eight different pixels needed for a particular reference block 4 without necessarily requiring additional main processor instructions to change the pointer. Have the heat pick up.

3 is a flow diagram schematically illustrating an example of a process performed using the system of FIG. 2. In step 26, sixteen words representing the current pixel block 2 are loaded into the coprocessor memory 18 from the cache 12 or the main memory 14. In step 28, the register Rn is loaded into the main processor 8 by a pointer value indicating the start of the reference block 4 in the memory. In step 30, the alignment value is loaded into the alignment register 20 of the coprocessor 10 using the coprocessor register load instruction of the main processor 8. It can be seen that steps 26, 28 and 30 set up the data processing environment to execute the sum instruction of the coprocessor load and the absolute difference. In many cases, this setup must be performed at one time to maintain the current state in order to test multiple reference blocks 4 for a particular current block 2. In such cases, the processing overhead associated with steps 26, 28 and 30 is significantly reduced.

Step 32 represents the execution of eight USALD coprocessor load instructions as described above. Each of these instructions calculates the sum of the absolute differences for the columns in the current block 2 and the reference block 4, respectively, to update the cumulative value in the accumulation register 22.

In step 34, the sum of the calculated absolute differences for the entire reference block 4 is retrieved for the main processor register instruction from the accumulation register 22 to the main processor 8 by means of the mobile coprocessor register. This cumulative value can be compared with a previously calculated cumulative value or with other parameters to identify the best image match or for other purposes.

4 shows three variations of the USALD instruction. The first variant consists only of addressing via a pointer held in register Rn without using an offset, and consists of conditional execution according to the conditional code {cond}. The second variant uses an address pointer consisting of a 10-bit offset value that may be added or subtracted from the initial value before or after its value used according to the flag {!}. Further, the third variant uses the offset value applied to the pointer value in the register Rn before using the offset value, and the pointer value at this time is not changed.             

Hereinafter, a more specific description of the embodiment of the present invention is given below:

1.1 terms and abbreviations

This document uses the following terms and abbreviations.

Term Meaning

ASIC Application Specific Integrated Circuit

BIST Built In Self Test

JTAG Joint Test Action Group

range

This document contains technical details of the ARM9x6 coprocessor for improving the performance of MPEG4 encoder applications. This document contains functional specifications in terms of hardware and software. This document does not contain the details of implementing hardware or software.

Introduction

Urchin CoProcessor (UCP) is an ARM9x6 designed to accelerate computational execution of the sum of absolute differences (SAD). This SAD operation is used in the MPEG4 motion estimation algorithm when comparing an 8x8 block from a reference frame with an 8x8 block of the current frame. This is part of the MPEG4 video encoding application.

1.2 UCP Structure

UCP interprets a set of coprocessor instructions that are part of the ARM instruction set. The ARM coprocessor instructions cause the ARM processor to

· Allow data to be transferred between UCP and memory (using the load LDC and save to coprocessor STC instructions to coprocessor),

Allow data to be transferred between UCP and ARM registers (using the move to coprocessor MCR and move to ARM MRC instructions).

ARM operates as an address generator and data pump for UCP.

The UCP consists of a register bank, a data path and control logic. This is shown in the UCP schematic diagram of FIG. 5.

1.3 Coprocessor Interface

The only connection from ARM to UCP is the coprocessor interface. All other system connections (AMBA or interrupts) are handled through ARM.

1.4 Design Constraints

The initial implementation of UCP is a point solution aimed at the 0.18um library. This will integrate the UCP with ARM926. This UCP is just a coprocessor in the system. The main constraint in design is the strict time conversion requirements in which all design decisions are made.

Other important design constraints are gate count, maximum operating frequency (worst case) and power consumption.

1.4.1 Gate Count

This section has been deleted because it is not relevant to the patent application.             

1.4.2 Operating Frequency

This section has been deleted because it is not relevant to the patent application.

1.4.3 Power Consumption

This section has been deleted because it is not relevant to the patent application.

Programmer's model

1.5 register

The UCP coprocessor includes two types of data storage:

Registers: These registers are used to transfer data directly between the ARM register and the coprocessor. These can be accessed by MCR and MRC operations.

Block buffer: This buffer stores 8 bytes (64-bits) per 8 lines that can only be loaded or stored directly from memory-mapped regions (ie not ARM registers). This block buffer is accessed by a set of special UCP instructions (ARM refers to these instructions as LDC and STC operations).

Here is a summary of the registers inside the UCP:

Reserved or indeterminate register bits should be masked at register read and set to zero at register write. Exceptions to this are CR_ACC and CR_BY0. These registers will always be restored to zero on read from unused bits, and writing to these registers can put any value in the unused bit position (UCP ignores these values).

1.5.1 CR_ACC

This is a 14 bit read / write register. This register can be updated directly by the MCR and indirectly by the SAD operation.

1.5.2 CR_IDX

This is a 3-bit read / write register. This register can be updated by the MCR directly, or indirectly by a SAD operation that increments the block buffer load / store or line index.

This register represents the line index of the block buffer. This sets which line the next operation that accesses the block buffer (these operations always use signal lines from the block buffer) will refer to.

If this register is incremented beyond the value 7, it will be overwritten with zeros.

1.5.3 CR_BY0

This is a 2-bit read / write register. This register can only be updated by the MCR.

UCP supports access to a reference frame from a byte aligned address. The lower two bits of the address bus for these loads are stored in this register.

Note that the coprocessor does not directly see the address value used by the ARM for memory access because the software has to program the byte offset separately in CR_BY0. Also, since ARM does not directly support unword-aligned loads for coprocessors, UCP performs three word loads and extracts the eight bytes required.

1.5.4 CR_CFG

This is a single bit read / write register. This register can only be updated by the MCR.

The IDX_INC bit controls whether the CR_IDX register is incremented after block buffer load / store or SAD operations. If that bit is clear, no increment occurs. If that bit is set, CR_IDX is incremented after the block buffer or SAD operation is completed.

1.5.5 CR_ID

This 14-bit read-only register has a UCP structure and calibration code.

Bits [3: 0] contain the correction number for the implementation.

Bits [7: 4] are set to the value 0xF for the ARM design implementation.

Bits [13: 8] contain the UCP structure version: 0x00 = version 1.

1.6 instruction set             

The assembler syntax of the UCP coprocessor uses the same format as ARM.

{} Indicates an optional field.

cond field is the ARM instruction condition code.

dest specifies the UCP destination register.

Rn is an ARM register.

CRn is a UCP register.

! Indicates that the computed address is written back to the base register.

UCP is the number of coprocessors in UCP

10_Bit_Offset is a formula for obtaining a value for a 10-bit word offset. This offset is added to the base register to form a load address. Note that

The offset must be a multiple of four.

6_Bit_Offset is a formula for obtaining a value for a 6-bit word offset. This offset is added to the base register to form a load address. Note that the above

The offset must be a multiple of four.

Note: Allow post indexing with or without light back.

The next page describes the instruction set for UCP.             

1.6.1 Instruction Set Summary

1.6.2 Instruction Encoding

The commands in the UCP are of the following coprocessor command types:

Coprocessor instructions are encoded as follows:

cond: condition code

UCP: Number of UCP Coprocessors

Rn: ARM register source CRn: UCP register source             

Rd: ARM register destination CRd: UCP register destination

8_bit_offset: 8-bit number (0-255); Used to indicate address offset.

P: pre / post indexing bit 0 = post; Add offset after transmission 1 = free; Add offset before transmission

U: up / down bit 0 = down; Subtract from base 1 = up; Add offset to base

W: write back bit 0 = no write back 1 = write address base

Note that only the opcode is valid for the UCP. Any modification of the opcodes (which hold UCPs from bit 11 down to 8 down) will result in unpredictable behavior .

1.6.3 UMCR

Use this UMCR instruction to write to the UCP register. UMCR moves data from ARM register Rn to UCP register CRd.

action

1 Move ARM register Rn to UCP register CRd

Associative symbol

UMCR CRd, Rn, {cond}

example

UMCR CR_ACC, R0; Load the contents of R0 into CR_ACC             

1.6.4 UMRC

Read from the UCP register using this UMRC instruction. UMCR moves data from UCP register CRn to ARM register Rd.

action

1 Move UCP register CRn to ARM register Rd

Associative symbol

UMRC Rd, CRn, {cond}

example

UMRC R6, CR_ID; Load ID register into R6.

1.6.5 UBBLD

Use this UBBLD instruction to load data into the block buffer.

action

Load 1 word Block_Buffer (CR_IDX, 0)

Load 2 word Block_Buffer (CR_IDX, 1)

If 3 (IDX_INC == 1)

4 ++ CR_IDX             

Associative symbol

UBBLD [Rn], # 0, {cond}

UBBLD [Rn, # + /-10_Bit_Offset] {!}, {Cond}

UBBLD [Rn], # + /-10_Bit_Offset {!}, {Cond}

example

UBBLD [R0], # 320! ; Load two words from mem (R0) into the block buffer

Post-increase until next line.

1.6.6 UBBST

This UBBST instruction is used to store data from the block buffer. This operation is for validation purposes only and is not used by application code.

action

Save 1 word Block_Buffer (CR_IDX, 0)

Save 2 words Block_Buffer (CR_IDX, 1)

If 3 (IDX_INC == 1)

4 ++ CR_IDX

Associative symbol

UBBST [Rn], # 0, {cond}

UBBST [Rn, # + /-10_Bit_Offset] {!}, {Cond}             

UBBST [Rn], # + /-10_Bit_Offset] {!}, {Cond}

example

UBBST [R3], # 8! ; Two words from the block buffer, starting with mem (r3)

Save into memory.

Note: UCP does not support UBBST consecutively when IDX_INC == 1. Each UBBST must be separated by at least one NOP. Using UBBST in succession will result in unpredictable behavior .

1.6.7 USALD

This USALD instruction loads data from a reference block and performs an SAD accumulation operation.

action

If 1 (CR_BY0 == 0)

Load 2 words into first word_tmp

3 otherwise

Load 4 words into mux1_tmp; Load word into mux2_tmp; Combining mux1_tmp and mux2_tmp based on CR_BY0 to form an unaligned word and load it into the first word_tmp.

5 SAD is performed for each byte in the first word_tmp and the corresponding byte in Block_Buffer (CR_IDX, 0). This accumulation is done by CR_ACC.

6 (CR_BY0 == 0)

Load 7 words into second word_tmp

8 otherwise

Load 9 words into mux3_tmp; Combining mux2_tmp and mux3_tmp based on CR_BY0 to form an unaligned word and load it into the second word_tmp.

10 SAD is performed for each byte in the second word_tmp and the corresponding byte in Block_Buffer (CR_IDX, 1). This accumulation is done by CR_ACC.

If 11 (IDX_INC == 1)

12 ++ CR_IDX

Note: Arithmetic is unsigned. Does not include a configuration to detect / process an overflow of CR_ACC. The size of the CR_ACC is chosen so that overflow cannot reliably occur from an 8x8 block comparison.

Mnemonic

USALD [Rn], # 0, {cond}

USALD [Rn, # + /-10_Bit_Offset] {!}, {Cond}

USALD [Rn], # + /-10_Bit_Offset {!}, {Cond}

example

USALD [R0], # 320! ; Two words mem (R0), SAD and R0 to the next line

Post-increase.             

1.7 Instruction Cycle Timing

The table below shows the number of cycles required to complete each instruction.

Note: N = 2 cycles if CR_BY0 is 0, N = 3 cycles otherwise.

1.8 Data hazards

Data hazards are cases where data dependencies between instructions can cause unpredictable behavior.

UCP does not use hardware interlocks to solve data hazards. Instead, software should have non-coprocessor instructions where needed, if NOP is needed.

TABLE 1

Functional description

1.9 coprocessor overview

This coprocessor is closely connected to the ARM9x6 processor. Each instruction destined for the UCP is processed immediately, as if the ARM core were executing its instructions. This UCP is not a coprocessor with fire and forget, and UCP instructions are executed immediately and the result (with certain conditions; see section 1.8) is available for the next instruction. This means that the ARM does not need to poll the state of the coprocessor and the coprocessor does not need to interrupt the ARM.             

1.10 Functional Diagram

6 shows the connection of the UCP.

1.11 Block Diagram

7 shows the main block of the UCP.

The control logic reads each instruction as it arrives from memory and has a pipeline follower to match the UCP and ARM. This coprocessor pipeline consists of the following steps: fetch, decode, execute, store, record, and SAD-accumulate.

The register bank holds a block buffer and MCR / MRC capable registers. This register bank also holds logic to increment RC_IDX.

The data path contains logic for USALD operations, including byte manipulation, SAD, and accumulation. This data path also handles the results of register read selection and internal operations, UMRC and UBBST.

System connection

UCP is designed to be directly connected to an ARM9x6 processor. The CHSDE_C and CHSEX_C outputs are not used in this configuration. The CPABORT input should be less constrained to the ARM966 and ARM946 processors. In such a configuration, the UCP would need special abandon handler code to recover from data abandonment during the load operation.

1.12 Connection with ARM920T

The ARM920 coprocessor interface is functionally identical to the 9x6 coprocessor interface. However, the interfaces differ significantly from each other in terms of signal timing. To use UCP as an ARM920, a separate external retiming block is required. The detailed requirements of this retiming block are beyond the scope of this document, but here is a brief overview of their construction.

The clock provided by the ARM920 is inverted and then transferred to the CPCLK for the UCP. Instead of using the CHSDE and CHSEX outputs, CHSDE_C and CHSEX_C are passed to a transparent latch enabled by the ARM 920 clock.

The CPABORT signal is obtained from the ETM interface.

1.13 Connection of secondary coprocessor

The UCP is by default not configured for a system using multiple external coprocessors. Auxiliary logic is required to support this.

When multiple coprocessors are attached with the interface, the handshaking signal can be combined by ANDing bit 1 and ORing bit 0. For two coprocessors with handshaking signals CHSDE1, CHSEX1 and CHSDE2, CHSEX2, respectively:

CHSDE [1] <= CHSDE1 [1] AND CHSDE2 [1]

CHSDE [0] <= CHSDE1 [0] OR CHSDE2 [0]

CHSEX [1] <= CHSEX1 [1] AND CHSEX2 [1]

CHSEX [0] <= CHSEX1 [0] OR CHSEX2 [0].

AC timing

This section is not complete at this time. AC timing is available for the 920T of the Philips process.

Appendix

1.14 Signal Description

The table below describes the signals that the UCP interfaces with the ARM9TDMI. At this time, this is made to be changed when implementation begins. The final signal may differ from the list shown below.

1.14.1 UCP Command Fetch Interface Signals

1.14.2 UCP Data Bus

1.14.3 UCP Coprocessor Interface Signals

1.14.4 Different Signals of the UCP

Claims (12)

A main processor that performs data processing operations in response to program instructions; At least one loaded data word therein connected to the main processor and responsive to a coprocessor load instruction of the main processor, the at least one defined by the coprocessor load instruction using the one or more loaded data words A coprocessor for performing a coprocessor processing operation of the processor and providing operand data to generate at least one result data word, In response to the coprocessor load instruction, a varying number of loaded data words is loaded into the coprocessor, depending on whether the start address of the operand data in the one or more loaded data words is aligned with a word boundary, And an alignment register for storing a value specifying an alignment between the operand data and the one or more loaded data words. The method of claim 1, The coprocessor comprises a coprocessor memory for storing one or more locally stored data words used as operands in the at least one coprocessor processing operation in combination with the one or more loaded data words. Device. The method according to claim 1 or 2, And a memory coupled to the main processor, wherein the one or more loaded data words are retrieved from the memory to the coprocessor via the main processor without being stored in a register within the main processor. Device. The method according to claim 1 or 2, And the main processor includes a register operative to store an address value indicating the one or more data words. The method according to claim 1 or 2, And said at least one coprocessor processing operation calculates a sum of an absolute difference between a plurality of byte values. The method of claim 5, The coprocessor includes a coprocessor memory that, in combination with the one or more loaded data words, stores one or more locally stored data words used as operands in the at least one coprocessor processing operation, the sum of the absolute differences Is calculated as the sum of the absolute differences between the plurality of byte values in the one or more loaded data words and the corresponding byte values of the plurality of byte values in the one or more locally stored data words. The method of claim 6, And the sum of the absolute differences is accumulated in a cumulative register of the coprocessor. delete The method of claim 4, wherein And the coprocessor load instruction includes an offset value added to the address value when executed. The method according to claim 1 or 2, And said at least one coprocessor processing operation calculates a sum of absolute differences as part of block pixel value matching. Performing data processing operations in the main processor in response to program instructions; Load one or more loaded data words into a coprocessor connected to the main processor in response to a coprocessor load instruction of the main processor, and use the one or more loaded data words to define at least one defined by the coprocessor load instruction Performing one coprocessor processing operation and providing operand data to generate at least one result data word, In response to the coprocessor load instruction, varying numbers within the coprocessor, depending on a value stored in an alignment register in the coprocessor indicating whether the start address of the operand data in the one or more loaded data words is aligned with a word boundary. And a loaded data word of the data processing method. Performing data processing operations in the main processor in response to program instructions; Load one or more loaded data words into a coprocessor connected to the main processor in response to a coprocessor load instruction of the main processor, and use the one or more loaded data words to define at least one defined by the coprocessor load instruction Control the computer to perform one coprocessor processing operation and provide operand data to generate at least one result data word, In response to the coprocessor load instruction, varying numbers within the coprocessor, depending on a value stored in an alignment register in the coprocessor indicating whether the start address of the operand data in the one or more loaded data words is aligned with a word boundary. And a computer program loaded with the loaded data word.

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