KR100767379B1 - A method manufacturing a thin film transistor substrate - Google Patents

Abstract

First, a conductive film of an aluminum alloy is sequentially stacked and patterned on an upper portion of a substrate to form a horizontal gate wiring including a gate line, a gate electrode, and a gate pad on the substrate. Next, a gate insulating film is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. Subsequently, a conductive layer including a lower layer of chromium and an upper layer of an aluminum alloy is stacked and patterned to form a data line including a data line, a source electrode, a drain electrode, and a data pad crossing the gate line. At this time, the lower layer of chromium is patterned by wet etching using an etchant consisting of 8-12% Ce (NH ₄ ) ₂ (NO ₃ ) ₆ and 4-12% nitric acid (NH ₃ ) and the remaining ultrapure water. In the case of 4-8% nitric acid, wet cleaning can be performed using a cleaning solution composed of 4-8% nitric acid and ultrapure water. Next, the resistive contact layer that is not covered by the data line is removed to expose the channel portion of the semiconductor layer. Next, a protective layer is stacked and patterned to form contact holes exposing the drain electrode, the gate pad, and the data pad. Then, the IZO is stacked and patterned to connect the drain electrode, the gate pad, and the data pad, respectively, to the pixel electrode, the auxiliary gate pad, and Form an auxiliary data pad.

Aluminum, IZO, etchant, chromium, etching time

Description

A manufacturing method of a thin film transistor substrate {A METHOD MANUFACTURING A THIN FILM TRANSISTOR SUBSTRATE}

1 is a thin film transistor substrate for a liquid crystal display according to an embodiment of the present invention,

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II ',

3A, 4A, 5A, and 6A are layout views of a thin film transistor substrate illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, according to a process sequence thereof.

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ in FIG. 4A and is a cross-sectional view showing the next step in FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and is a cross-sectional view showing the next step in FIG. 4B;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and is a cross-sectional view showing the next step in FIG. 5B;

7 is a scanning electron microscope (SEM) photograph of an exposed channel part in a method of manufacturing a thin film transistor substrate according to an experimental example of the present invention.

8 is a graph showing the etching time of the chromium film with respect to the etchant according to the experimental example of the present invention.

The present invention relates to a method for manufacturing a thin film transistor substrate, and more particularly, to a method for manufacturing a thin film transistor substrate for a liquid crystal display device using the thin film transistor as a switching element.

In general, a liquid crystal display device injects a liquid crystal material between two substrates having an electrode generating an electric field, and applies an electric potential different from each other to form an electric field to change the arrangement of liquid crystal molecules, thereby transmitting light. It is a device that expresses the image by adjusting.

Such a liquid crystal display device has a plurality of pixels in which a display electrode is formed and color filters of red, green, and blue are formed, and thin film transistors for controlling an image signal applied through wirings are formed in each pixel. It is. The thin film transistor is electrically connected to a scan signal line or a gate line for transmitting a scan signal, an image signal line or a data line for transferring an image signal, and a pixel electrode.

Here, in order to complete the substrate on which the thin film transistor is formed, it is common to form a wiring, a semiconductor layer, a pixel electrode, and the like through a photolithography process using a mask. In this case, since the wiring is used as a means of transmitting a signal, it is common to use a metal material having a low resistance, in particular, an aluminum-based metal material such as aluminum (Al) or aluminum alloy (Al alloy) to minimize signal delay. . However, because the wiring of aluminum or aluminum alloys is weak in physical or chemical properties, corrosion occurs when connected when in contact with other materials, thereby degrading the characteristics of the device. In order to solve this problem, wires are formed as a double layer by adding chromium with excellent contact properties with other materials, and methods for etching chromium include Ce (NH ₄ ) ₂ (NO ₃ ) ₆ and nitric acid (HNO ₃ ). Applying a wet etching using an etchant comprising a, there is a problem that the residue is left in the wet etching process is deteriorated characteristics of the device.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a thin film transistor substrate capable of preventing residue from remaining.

In order to solve this problem, in the present invention, the chromium film is etched using an etchant consisting of 8-12% Ce (NH ₄ ) ₂ (NO ₃ ) ₆ and 4-12% nitric acid (NH ₃ ) and the remaining ultrapure water. In the case of 4-8% nitric acid, the wet cleaning is performed using a cleaning solution composed of 4-8% nitric acid and ultrapure water.

More specifically, in the method for manufacturing a thin film transistor substrate according to the present invention, first, a gate line including a gate line and a gate electrode connected to the gate line is formed on an insulating substrate, and a gate insulating film covering the gate line is formed. Subsequently, a semiconductor layer of amorphous silicon and a resistive contact layer of doped amorphous silicon are formed on the gate insulating film of the gate electrode, and then a first conductive film made of chromium is laminated and 8-12% of Ce (NH ₄ ) ₂ (NO ₃ ) Wet etching the conductive layer using an etchant consisting of ₆ , 4-12% nitric acid (NH ₃ ) and the remaining ultrapure water, and source electrode for the source electrode and the gate electrode connected to the data line and the data electrode and adjacent to the gate electrode. A data line is formed that includes the drain electrode positioned opposite to the side of the substrate.

At this time, after forming the data wiring, it is preferable to perform a wet cleaning using a cleaning liquid composed of 4-8% nitric acid and the remaining ultrapure water.

Further, after the wet cleaning, the resistive contact layer exposed using the data wiring as a mask is etched to expose the semiconductor layer, a protective film covering the exposed semiconductor layer is formed, and the protective film is etched to form a contact hole exposing the drain electrode. A pixel electrode connected to the drain electrode may be formed on the passivation layer through the contact hole.

The data line may be formed on the first conductive layer and further include a second conductive layer including aluminum or an aluminum alloy.

Then, the method for manufacturing the thin film transistor substrate according to the embodiment of the present invention with reference to the accompanying drawings will be described in detail to be easily carried out by those skilled in the art.

First, the structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view illustrating a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II ′.

A gate wiring including a conductive film made of a metal material of aluminum or aluminum alloy having low resistance is formed on the insulating substrate 10. The gate line is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line 22. ), The gate electrode 26 of the thin film transistor is connected.

The gate wirings 22, 24, and 26 are preferably formed of a single film of aluminum series, but may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material such as chromium or molybdenum or molybdenum alloy having good contact properties with other materials such as ITO or IZO or a substrate.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 55 and 56 and the gate insulating layer 30, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), Data wires 62, 64, 66, 68 made of metal or a conductor such as titanium (Ti) are formed. The data line is formed in the longitudinal direction and crosses the gate line 22 to define a pixel, the data line 62 and the branch of the data line 62 and the source electrode 65 extending to the upper portion of the ohmic contact layer 54. ), Which is connected to one end of the data line 62 and is separated from the data pad 68 and the source electrode 65 to which an image signal from the outside is applied, and is opposite to the source electrode 65 with respect to the gate electrode 26. And a drain electrode 66 formed over the ohmic contact layer 56. In addition, the data line further includes a conductor pattern 64 for a storage capacitor that overlaps the protruding gate line 22 to form an organic capacitor.

The data lines 62, 64, 65, 66, and 68 are preferably formed of a single film of aluminum or aluminum alloy, but may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having a low contact resistance with other materials, especially IZO. Examples include Al (or Al alloys) / Cr or Al (or Al alloys) / Mo (or Mo alloys), and the like. In an embodiment of the present invention, data wirings 62, 64, 65, 66, and 68 may be used. It consists of a double film of a lower film 601 of silver chromium and an upper film 602 of aluminum-neodymium alloy.

Low dielectric constant insulation made of SiOC or SiOF or the like when deposited on silicon nitride or an acrylic organic material having a low dielectric constant or a chemical vapor phase on the data wires 62, 65, 64, 66, 68 and the semiconductor layer 40 which are not covered by these. A protective film 70 made of a material is formed. In the passivation layer 70, contact holes 72, 76, and 78 that expose the conductive pattern 64 for the storage capacitor, the drain electrode 66, and the data pad 68, respectively, are formed, and together with the gate insulating layer 30. The contact hole 74 which exposes the gate pad 24 is formed.

On the passivation layer 70, a pixel electrode 82, which is electrically connected to the drain electrode 66 and the conductive capacitor pattern 64 for the storage capacitor and positioned in the pixel, is formed through the contact holes 76 and 72. In addition, the auxiliary gate pad 84 and the auxiliary data pad 88, which are connected to the gate pad 24 and the data pad 68, respectively, are formed on the passivation layer 70 through the contact holes 74 and 78. The pixel electrode 82, the auxiliary gates, and the data pads 84 and 88 are made of indium zinc oxide (IZO).

1 and 2, the pixel electrode 82 is electrically connected to the conductive pattern 64 for the storage capacitor to form the storage capacitor with the gate line 22. The storage capacitor wiring may be added to the same layer as the wirings 22, 24, and 26.                     

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 6B.

First, as shown in FIGS. 3A and 3B, about 2,500 mW using a target containing Al-Nd containing 2 at% of Nd among aluminum or aluminum alloy metals having low resistance on the substrate 10. The gate line 22, the gate electrode 26, and the gate pad 24 are formed and stacked by sputtering at about 150 ° C. to form a gate wiring having a tapered structure.

Next, as shown in FIGS. 4A and 4B, the gate insulating film 30 made of silicon nitride, the semiconductor layer 40 made of amorphous silicon, and the doped amorphous silicon layer 50 doped with N-type impurities at a high concentration. The semiconductor layer 40 on the gate insulating film 30 facing the gate electrode 24 by successively stacking three-layer films and patterning the semiconductor layer 40 and the doped amorphous silicon layer 50 in a patterning process using a mask. And the ohmic contact layer 50 is formed. Here, the gate insulating film 30 is preferably formed by laminating silicon nitride to a thickness of about 2,000 to 5,000 Pa, in a temperature range of 250 to 400 ° C.

Next, as shown in Figs. 5A to 5B, a lower film 601 made of chromium is laminated to a thickness of about 500 GPa, and Nd of 2 at% in aluminum or aluminum alloy metal having a low resistance thereon. Using a target of Al-Nd alloy containing a top layer 602 is sequentially laminated by sputtering (sputtering) at a thickness of about 2,500Å at about 150 ℃, patterned by a photo process using a mask gate line ( A data line 62 intersecting with the data line 22, a source electrode 65 connected to the data line 62 and extending to an upper portion of the gate electrode 26, and a data pad 68 connected to one end thereof. ) And the conductive pattern 64 for the storage capacitor which is separated from the source electrode 65 and overlaps the drain electrode 66 and the gate line 22 facing the source electrode 65 around the gate electrode 26. Data with a taper structure The form. Here, both the upper layer 602 and the lower layer 601 may be etched by wet etching, and the chromium layer of the lower layer 601 may include Ce (NH ₄ ) ₂ (NO ₃ ) ₆ , nitric acid (HNO ₃ ), and ultrapure water. Patterned by wet etching using an etchant comprising a. When the chromium film is etched using the etchant, the Ce component remains on the substrate, which acts as a cause of deterioration of the characteristics of the thin film transistor. In order to solve this problem, when the content of nitric acid (HNO ₃ ) is increased, the residue may be prevented from being left, but the etching ratio of the chromium film to the etching solution may be reduced, thereby reducing productivity. Accordingly, in order to minimize the residue remaining, the etchant uses an etchant consisting of 8-12% Ce (NH ₄ ) ₂ (NO ₃ ) ₆ and 4-12% nitric acid (NH ₃ ) and the remaining ultrapure water. In the case where the content of nitric acid is low at 4-8%, the chromium film is patterned using an etching solution, and then wet cleaning is performed using a cleaning solution composed of 4-8% nitric acid and ultrapure water. This will be described in detail later through experimental examples.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer 40 which is a channel portion between 55 and 56, that is, between the source and drain electrodes 65 and 66 is exposed. Subsequently, in order to stabilize the surface of the channel portion of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 6A and 6B, an inorganic insulating film such as silicon nitride is stacked in a range of 250 to 400 ° C. to form a protective film 70, and together with the gate insulating film 30 in a photolithography process using a mask. Patterning by dry etching forms contact holes 72, 74, 76, 78 exposing the conductive capacitor conductor 64, the gate pad 24, the drain electrode 66, and the data pad 68, respectively. .

Next, as shown in FIGS. 1 and 2, the IZO film is laminated by sputtering and patterned using a mask to conduct the conductive capacitor pattern 72 and the drain electrode 66 for the storage capacitor through the contact holes 72 and 76. ) And an auxiliary gate pad 84 and an auxiliary data pad 88 respectively connected to the gate pad 24 and the data pad 68 through the pixel electrode 82 and the contact holes 74 and 78 connected to each other. do.

Experimental Example

In the experimental example, in order to laminate the chromium film and form the data wiring, an etching solution containing Ce (NH ₄ ) ₂ (NO ₃ ) ₆ , nitric acid (NH ₃ ), and the remaining ultrapure water was patterned, followed by a cleaning process. And a channel portion between the drain electrodes 65 and 66 was formed in a “∩” shape, and the residue remaining on the channel portion was measured after etching the doped amorphous silicon layer 50 using the data wiring as an etching mask. At this time, the content of Ce (NH ₄ ) ₂ (NO ₃ ) ₆ in the etchant of wet etching is fixed to 10.8%, the content of nitric acid (NH ₃ ) is changed in the range of 4-16%, and the content of nitric acid in the cleaning process The mixture was washed with ultrapure water in the range of about 4-8%.

In addition, in order to measure the etching ratio of the chromium film, the chromium film is laminated to a thickness of 1,500Å, and then the same Ce (NH ₄ ) ₂ (NO ₃ ) ₆ content is fixed at 10.8%, and the content of nitric acid (NH ₃ ) is 4- The etching time of the chromium film was measured while changing in the 16% range.

FIG. 7 is a scanning electron microscope (SEM) photograph of an exposed channel part in a method of manufacturing a thin film transistor substrate according to an experimental example of the present invention, and FIG. 8 illustrates an etching time of a chromium film with respect to an etchant according to an experimental example of the present invention. The graph shown.

As shown in FIG. 7, as the content of nitric acid in the etchant was increased, staining was reduced, indicating that the residue was reduced. In this case, when the content of nitric acid in the etchant was 4% and 8%, a large amount of residue was measured. However, in the case of the nitric acid content of 12% and 16%, almost no residue was observed even if the cleaning process was not performed. However, as shown in FIG. 8, when the nitric acid content in the etching solution is in the range of 12-16%, the etching time is very high as 80 seconds or more, thereby reducing productivity. On the other hand, as shown in Figure 7, even when the content of nitric acid in the etchant 4% and 8% as a result of additional wet cleaning using a cleaning solution consisting of 8% nitric acid and the remaining ultrapure water almost no residue.

 As described above, according to the present invention, in the manufacturing process of the thin film transistor substrate, the etching time is secured by optimizing the content of nitric acid in the chromium etching solution for etching the chromium film or additionally performing wet cleaning through the cleaning solution containing nitric acid. Minimizing the residue can improve the characteristics of the thin film transistor.

Claims (4)

Forming a gate line including a gate line and a gate electrode connected to the gate line on the insulating substrate; Forming a gate insulating film on the substrate; Forming a semiconductor layer of amorphous silicon on the gate insulating film of the gate electrode, Forming an ohmic contact layer of doped amorphous silicon on the semiconductor layer, Stacking a first conductive film made of chromium, and The conductive layer is etched using an etchant consisting of 8-12% Ce (NH ₄ ) ₂ (NO ₃ ) ₆ , 4-12% nitric acid (NH ₃ ) and the remaining ultrapure water, and is connected to the data line and the data line. Forming a data line including a source electrode adjacent to the gate electrode and a drain electrode positioned opposite to the source electrode with respect to the gate electrode; Method of manufacturing a thin film transistor substrate comprising a. In claim 1, After the data line forming step, A method of manufacturing a thin film transistor substrate further comprising performing a wet cleaning using a cleaning liquid consisting of 4-8% nitric acid and the remaining ultrapure water. In claim 2, After the wet cleaning step, Etching the ohmic contact layer exposed by using the data line as a mask to expose the semiconductor layer; Forming a protective film covering the exposed semiconductor layer, Etching the passivation layer to form a contact hole exposing the drain electrode; And forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer. In claim 1, The method of claim 1, further comprising forming a second conductive film including aluminum or an aluminum alloy on the first conductive film.

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