KR100766666B1 - Multi-processor system - Google Patents

Abstract

Data transmission when data is written to the shared memory is performed using a high-speed dedicated line provided between each processor and the shared memory. When writing to the shared memory space of the shared memory, each processor notifies the update notification bus corresponding to the conventional global bus to which address to update. The other processor detecting this notification prohibits access to the address in the shared memory cache and waits for data written to the address to be transmitted using the dedicated line. When data is transmitted, data is written to the corresponding address of the shared memory cache. At this time, the corresponding data is also written to the corresponding address of the shared memory, and cache coherency is maintained. In addition, in order to transmit the write address, it is necessary to acquire a license to use the bus. However, since data is transmitted using a dedicated line, the time for acquiring the license to use the bus is greatly reduced.

Update Notification, Global Bus, Shared Memory Cache, Cache Coherency, Private Line

Description

Multiprocessor System {MULTI-PROCESSOR SYSTEM}

SUMMARY OF THE INVENTION The present invention is a shared memory type multiprocessor system that combines a plurality of processors and arranges a shared memory space shared by these processors, in particular a system configured by a processor having a shared memory cache for caching data in the shared memory space. It is about. The processing of the software is shared by each processor, and the shared memory is used as a place for storing information to be managed in units of systems, not as an exchange of data when the processing is continued between processors or a single processor. Shared memory caches are introduced to improve system performance by speeding up access to shared memory.

1 is a diagram showing a conventional example of the simplest shared memory type multiprocessor system.

A plurality of processors and shared memory are connected by the same global bus, and each processor accesses the shared memory via this global bus. Each of the processors 1a-1 to 1a-n sends bus request signals 1c-1 to 1c-n to the arbiter 1b, and the right of use is adjusted by the arbiter so that the processor 1 receives the same time. Only one processor is given a right to use the global bus 1e, and bus permission signals 1d-1 to 1d-n are sent to the processors. Upon receiving the bus permission signal, the processor accesses the shared memory 1f via the global bus to receive the desired data.

In the realization method of FIG. 1, all access to the shared memory space is via the global bus regardless of the type of read and write.

There are two restrictions here.

Constraints 1: Time for signal transmission (physical constraints)

Constraints 2: Require order wait time for bus licenses (principle constraints)

The former is due to the fact that the signal transmission distance becomes long in the global bus, and that high-speed signal transmission becomes difficult due to electrical conditions such as a plurality of processors sharing the same signal line. The latter is attributable to the fact that when two or more processors access the shared memory at the same time, the second and subsequent processors wait for access to the shared memory by adjusting the global bus usage rights. As a result, these restrictions cause the following problems in access to the shared memory space.

Issue 1: lack of bands (number of accesses per hour allowed to the system)

Problem 2: Excessive Latency (Time to Start to Complete)

Fig. 2 is a diagram showing a conventional example in which the shared memory cache 2h is disposed on each processor.

When the processor core 2g reads the shared memory space, if there is a copy of the data of the shared memory space on the shared memory cache, the read processing can be completed on the processor via the internal bus 2i, and the above limitations. 1 can be reduced. In addition, since the access via the global bus is not performed, the adjustment of the use rights of the global bus becomes unnecessary, and the above-mentioned restriction 2 is released. In this regard, the introduction of a shared memory cache is an improvement over this problem.

The introduction of a shared memory cache allows each processor to maintain a copy of the data in the shared memory space individually, but the data on the shared memory space must look the same for all processors. Therefore, regarding the write processing which is the trigger for data update, consideration of coherency control that guarantees this is essential. Although the reason is mentioned later, this coherency control also becomes a barrier in solving the said problem.

Here, the requirements on coherency control are subdivided into the following three.

Requirement 1: Time Motivation

Requirement 2: spatial motivation

Requirement 3: Reduction of renewal time

It is a figure explaining coherence control.

3 illustrates the meaning of the above requirement, when data at any address on the shared memory space had a value of 0, processor 1 writes the value 1 to that address, and then processor 2 writes the value 2 to it. It is assumed that other processors 3 to n read the address. Here, requirement 1 corresponds to excluding the possibility of reading on an individual processor, for example in the order of value 2 → value 1 (guarantee of t ₁ ≧ 0), and requirement 2 is already a value 1, for example. Even if there is a processor that reads, it is equivalent to excluding the possibility that a processor that reads a value 0 thereafter occurs (a guarantee of t _2? O). In addition, requirement 3 corresponds to making the time from the time of data update to another processor still reading the data before the update and the time until the data after the update can be read as short as possible (t _2). And minimization of t ₃ ). Requirement 3 is not a requirement for coherency control, but is needed to improve system performance.

In the example of coherency control in FIG. 2, each write process of a processor to a shared memory space is reflected in its shared memory cache and written to the shared memory via the global bus, while another processor May monitor a write access appearing on the global bus and replace the data with data on the global bus when the data of the corresponding address is on each shared memory cache.

4 is a diagram for explaining an example of a method of establishing cache coherency.

4 is an example of a processing sequence based on the above method. In the drawings, the timings of (4a) to (4f) correspond to the following ideas, respectively.

(4a): processor core activates write access

(4b): Send global bus request by write access start

(4c): Bus use permission, address is output to the global bus

(4d): Another processor / shared memory receives information from the global bus and writes to its shared memory or shared memory cache

(4e): complete memory write

(4f): The processor that initiated write access opens the bus

In this example, the conditions necessary for the coherence guarantee are expressed by the following equation.

t _{rc ( min )} > t _{dsd (max)} + t _{dmw (max)}

t _{dsd (max)} <t _{dsd (min)} + t _{dmw (min)}

here,

t _rc: Time from issuance of light to global bus to bus opening

t _dsd: the time required for other processors to recognize the write to the global bus

t _{dmw: The} time it takes for the processor / shared memory to recognize write access on the global bus and then reflect that data to itself

to be.

Here, Equation 1 is a condition for satisfying the above requirement 1, which guarantees to open the global bus after the write value is reflected in the shared memory and the shared memory cache on all processors (generally, the completion response of the write process). Is sent from the pi-right side and a bus opening is often used as the reception). By satisfying the conditions, it is guaranteed that the previous write processing is completed when the next processor starts the write processing by adjusting the usage rights of the global bus. In other words, although the requirement of coherency control is satisfied by the shortcomings of the global bus, in practice, the above requirement 1 is essentially indistinguishable from requiring adjustment of data update. Guaranteeing the ordering of data updates is equivalent to ensuring that a plurality of data updates do not occur at the same time, i.e., making adjustments. Therefore, satisfying the above requirement 1 of coherency control is a barrier in solving the above problem by receiving the above-mentioned constraint 2 generated in using the global bus.

On the other hand, Equation 2 is a condition for absorbing that the timing of Fig. 4 (4d) is varied in each processor and satisfying the above requirement 2. The timing (4d) is a timing at which a boundary between whether the data before the update is returned to the processor core or the data after the update is returned when the read access competing with the write access shown in the global bus is activated on each processor. Since it is the timing of (4e) that the data after the update is conveyed, if the expression (2) is not satisfied, this timing is reversed depending on the processor, which is contrary to the above requirement.

Here, for example, Equation 1 indicates that the bus occupancy time must be greater than or equal to a certain time, that is, to impose a restriction on a band of the shared memory space, and Equation 2 indicates a write time for the shared memory cache or the shared memory. Even when trying to increase the bandwidth by shortening the time, it is indicated that the timing of 4d must be maintained for a predetermined time or more, taking into account that the timing of 4d varies between processors. According to these examples, since conditions are added to various operation timings, coherency control itself brings about a kind of limitation when it is desired to shorten processing time and improve performance.

Patent Literature 1 is a technique that takes coherence between conventional caches. In Patent Document 1, a processor module has a cache memory and issues a coherency transaction to another processor module via a bus. The processor module receiving the coherency transaction executes the coherency check. When updating is performed to maintain coherency, data to be used for updating is sent over the bus. The signal line connecting the processor module and the main memory is used for notification of the result of the coherency check.

[Patent Document 1] Japanese Patent Application Laid-Open No. 7-281956

<Start of invention>

Disclosure of Invention An object of the present invention is to solve the above problem by minimizing the performance deterioration factor caused by the various constraints including coherency control as described above, and to improve the bandwidth and latency of the shared memory space. It is to provide a processor system.

The multiprocessor system of the present invention is a multiprocessor system in which a plurality of processors each having a shared memory cache and at least one shared memory are combined with each other, wherein data to be used for updating is performed in updating data in a shared memory area. A dedicated line means for exclusively transmitting and receiving the data between the processor and the shared memory, and a global bus means for transmitting data update notification while adjusting the right to transmit the update notification to each processor, wherein the data from the processor is provided. Each processor and the shared memory independently transmit the update notification and the data to be used for the update, and by receiving the update notification, access to the address indicated by the update notification is restricted, and each processor and the shared memory. By data to use for update that arrived at After the data of the address of the shared memory area is updated, access to the address is permitted.

According to the present invention, by providing a dedicated line means for transmitting and receiving update data, transmission and reception of update data is speeded up. In addition, since the global bus means only needs to adjust and transmit the update notification with a small amount of data, it is less likely to wait for a long time to obtain a bus usage right. Further, in accordance with the update notification, each processor and the shared memory update the shared memory area by the update data, thereby ensuring coherence between the shared memory cache and the shared memory.

1 illustrates a conventional example of the simplest shared memory type multiprocessor system.

Fig. 2 is a diagram showing a conventional example in which a shared memory cache 2h is disposed on each processor.

3 is a diagram for explaining coherency control.

4 is a view for explaining an example of a method of establishing cache coherency.

5 is a configuration diagram of a system based on an embodiment of the present invention.

6 is an example of a time chart based on a series of processes of the first aspect in the embodiment of the present invention.

7 is an example of a time chart of processing based on the second aspect of the embodiment of the present invention.

8 is an example of a time chart when data is updated with different data sizes.

9 is an example of a time chart of processing based on the third aspect of the embodiment of the present invention.

10 is an example of a time chart based on the principle of the fourth aspect of an embodiment of the present invention.

11 and 12 are time charts showing the configuration diagram of the system in the fifth aspect of the embodiment of the present invention and its control principle.

13 is a view for explaining a sixth aspect of an embodiment of the present invention.

14 is a more detailed system block diagram based on the embodiment of the present invention.

Fig. 15 is a diagram showing the internal configuration of each of the processors 14a-1 to 14a-10 in Fig. 14.

Fig. 16 is a diagram showing the flow of signals during write access in the first aspect in the embodiment of the present invention.

Fig. 17 is a diagram showing a signal flow at the time of receiving update data based on the first aspect of the embodiment of the present invention.

FIG. 18 is a diagram illustrating a signal flow during typical read access in which data in the shared memory cache can be used in the first aspect of the embodiment of the present invention. FIG.

Fig. 19 is a diagram showing a signal flow when data on a shared memory cache cannot be used in read access in the first aspect of the embodiment of the present invention and involves update data request processing.

20 is a diagram showing the flow of signals in response by the master processor to an update data request transmitted from another processor in the first aspect of the embodiment of the present invention;

Fig. 21 is a diagram showing the flow of signals during write access in the second aspect of the embodiment of the present invention.

Fig. 22 is a diagram showing a signal flow when receiving update data sent from another processor in the second aspect of the embodiment of the present invention.

Fig. 23 is a diagram showing a signal flow during write access in which update notification is omitted in the third aspect of the embodiment of the present invention.

Fig. 24 is a diagram showing a signal flow at the time of receiving update data in which the update notification sent from another processor is omitted in the third aspect of the embodiment of the present invention.

Fig. 25 is a diagram showing the flow of signals when a processor added to the system makes an entire data transmission request in the cache fill operation in the second aspect of the embodiment of the present invention.

Fig. 26 is a diagram showing a signal flow when a master processor performs full data transmission in response to a full data transmission request in the cache fill operation in the fourth aspect of the embodiment of the present invention.

Fig. 27 is a diagram showing a signal flow when a processor expanded in a system performs full data reception in the cache fill operation in the fourth aspect of the embodiment of the present invention.

Fig. 28 is a diagram showing a signal flow at the time of light access based on the fifth aspect of the embodiment of the present invention.

<Best Mode for Carrying Out the Invention>

5 is a configuration diagram of a system based on the embodiment of the present invention.

The principle of this invention in the 1st aspect of embodiment of this invention is described below. In Fig. 5, the portion corresponding to the global bus of the conventional example is used as the update notification bus 5e as a bus that makes a notification of data update and a request for sending update data. The content of the update data is transmitted and received between the repeater 5h using the data channel 5g. It is assumed that the data channel uses high speed broadband known transmission means (e.g., Gigabit Ethernet). The repeater 5h has a function of broadcasting the data shown in each port to which the data channel is connected to all the ports. In addition, when the number of processors is small and becomes the actual number of data channels, the data channels may be provided one-to-one between all processors and the shared memory without providing repeaters, and processing may be performed on each processor. In addition, the shared memory may be disposed on a specific processor, and in the case where each processor has a shared memory cache equal to the size of the shared memory space, as in the example in Japanese Patent Application Laid-Open No. 2002-126212, the shared memory may be shared. You do not need to install the memory itself. In any case, the effect as embodiment of this invention can be acquired.

When the processor core issues a write process to the shared memory space, each processor acquires an update notification bus and sends an update target address to the update notification bus. At the same time, update data is input to the transmission buffer of the data channel. The update data mainly receives signal processing delays at ports of the processors and repeaters, and delays the update notification to reach other processors.

On the other hand, the update notification bus is always monitored by all processors. When an update notification is detected, the update notification bus writes the corresponding address to the update queue on the processor. After that, when update data arrives, it is written to the shared memory cache and the corresponding address is erased from the update queue. When the read processing from the processor core is activated for an address existing on the update queue, the read from the shared memory cache is suspended, and the data is processed in accordance with the write processing to the shared memory cache when the update data arrives. The process of conveying to a core is performed. Here, all addresses are to be monitored for the addresses stored in the update queue, and the address of the write destination is added to the update data. Therefore, each processor can compare the address in the update queue with the address added to the update data, and write the update data to the appropriate address of the shared memory cache. In addition, although the configuration of the shared memory is basically the same as that of the processor, there is no processor core in the shared memory and the shared memory chip has a larger shared memory cache.

If there is no valid data on the shared memory cache, i.e. read access at the time of a cache miss, the processor that issues a request to send an update data to the update notification bus and maintains the shared memory or other valid data on the shared memory cache This is done by sending update data.

6 is an example of a time chart based on a series of processes of the first aspect in the embodiment of the present invention.

In this example, processor 1 writes data 1 to address 1, processor 2 writes data 2 to address 2, and parallel processor 3 writes address 1, address 0, and address 1 in parallel. This is the case. In addition, all initial values of data in the shared memory space are zero. In Fig. 6, A denotes an address, D denotes data, and (1)? 0 denotes data writing to address 1, and 1? (0) denotes data from address 0. Each of 1 means a lead.

In the first read of the processor 3, since the update queue is empty, the read is performed from the shared memory cache, and data 0 is returned to the processor core. Subsequently, an update notification from processor 1 is detected, and it is put into the update queue of processor 3. At the second read of the processor 3, the update queue is not empty, but the address 1 is only on the update queue, and there is no match with the read address, and data 0 is the same process as the first read. Conveyed to the core. In the third read, since there is a match with the read address on the update queue, the read of the shared memory cache is not activated and the read access is maintained. After that, when update data of address 1 arrives from processor 1, data 1 is written to the shared memory cache of processor 3, and the update queue is cleared, and at the same time, the data is returned to the processor core as read data of address 1.

The main advantages of this method are the following two. One is that the processor on the side of updating data does not have to wait for the other processor to reflect the shared memory cache, so that the bus occupancy time can be reduced, and the bandwidth of the shared memory space can be improved. will be. In addition, the average latency of read access can be reduced by eliminating unnecessary waiting time of read access that is not in conflict with the data update process. Of these, the degree of improvement of the latter conventional example varies depending on the hit ratio of the shared memory cache and the probability of occurrence of access contention. In particular, the higher the hit rate and the lower the probability of contention occurrence, the more prominent the advantage of the present scheme is.

The principle in the first aspect of the embodiment of the present invention is to further expand the bandwidth of the shared memory space by blocking the unit of data update in the first aspect. As a general conceivable implementation, the bandwidth of the data channel and shared memory cache can be much larger than that of the update notification bus. Therefore, the band of the shared memory space is limited by the band of the update notification bus, and there is a possibility that the band of the data channel and the shared memory cache cannot be used up. First of all, this is to be solved.

7 is an example of a time chart of processing based on the second aspect of the embodiment of the present invention.

In FIG. 7, data update is performed in units of four addresses. The update notifications sent by the processors 1 and 2 are performed by indicating the head of the update target address, and the update data of the corresponding address is collectively sent out on the data channel.

With the fixed data length, there is a case that data must be updated by tightening even data that is unnecessary for software processing. Therefore, the bandwidth of the data channel and the shared memory cache may be wasted and the effective band may be lowered. do. Therefore, the update data size is made variable so that only necessary data is sent out to the data channel.

8 is an example of a time chart when data is updated with different data sizes.

In FIG. 8, only the first write of the processor 1 is the update size 2 in the example of FIG. This difference reduces the occupancy time of the data channel and the shared memory cache by the time required for data exchange for two addresses as a whole. In addition, since the arrival of the update data corresponding to the write processing of the processor 2 is shortened by that time, and the time until the contents of the update queue is cleared is shortened, the latency during access contention can be reduced by this principle.

In addition, the scheme in the second aspect may be not only an improvement of the band but also a means for providing an exclusive update in units of blocks on the shared memory space. In this regard, it is also possible to make the software processing more efficient and to improve the processing capability of the system. This is because in order to realize the equivalent in software, extra processing is required to manage update start and completion.

The principle in the third aspect of the embodiment of the present invention is that the processor can select, for each write access, an attribute of whether coherency control is required, so that an update notification is given for a write access for which an attribute of no coherency control is specified. The control is performed to send only the update data to another processor without issuing the. Depending on the contents of the software process, there is also the use of the shared memory space where no coherency guarantee is required. Therefore, the software uses this control for such a process to reduce the frequency of use of the update notification bus, thereby reducing the shared memory. In addition to improving the bandwidth of the space, it is possible to reduce the time required for update data to be reflected to other processors, and to reduce the average latency of read access by minimizing the increase in latency caused by unnecessary access contention. .

9 is an example of a time chart of processing based on the third aspect of the embodiment of the present invention.

The access pattern of the processor in this example is in accordance with the example of FIG. 6, except that the first write of processor 1 is accompanied by an attribute that requires no coherency control. Since the processing on the update notification bus accompanying the first write of the processor 1 is not started, the occupancy time of the update notification bus is reduced as necessary. In addition, since the update notification accompanying the second write access by the processor 2 is quickly sent to the update notification bus by that much, the update time can be shortened. The third read of the processor 3 is issued after the write of the processor 1, but since it is not put into the update queue by this control, no waiting for contention occurs and the read access is completed with the same latency as usual. .

The principle in the fourth aspect of the embodiment of the present invention is that the processor or shared memory holding all the data in the shared memory space at the time of online expansion of the processor frees the data in the shared memory space owned by the processor. Is sent to the expansion processor, which receives the data and initializes the shared memory cache.

If the contents of the shared memory cache are invalid data immediately after the expansion, and all of them are directly added to the operating system, all accesses to the shared memory space will be missed in the shared memory cache. As a result, the processing capacity of the expansion processor is notably reduced immediately after the start of operation, and since the update notification bus and the data channel are inadvertently occupied, there is a risk that other processors are affected and the system performance is rather deteriorated. According to this method, the processing capacity of the operating system can be prevented from being increased by the processor expansion, and the processing capacity of the expansion processor can also be raised to the maximum immediately after the start of operation.

10 is an example of a time chart based on the principle of the fourth aspect of the embodiment of the present invention.

In the figure, a to h are transfers based on the normal data update process, and 1 to 8 are data transfers to the expansion processor performed by this system. The expansion processor notifies another processor of the newly installed system by sending a signal to the update notification bus or by using a dedicated signal line indicating unimplementation. The processor or shared memory that sends data to the enlarged processor object receives the notification and sends update data to the data channel when its update queue is empty, as shown in FIG. If the update queue is not empty, data sending stops immediately and priority processing is given priority. When the update queue becomes empty, data sending resumes. By this process, a process of sending out data for filling the shared memory cache to the expansion processor can be added without affecting the timing of the normal data update process performed on the system. After the expansion processor is filled with all data received from the data channel, the expansion processor starts the original processing and participates in the operation system. At this time, the contents of the shared memory cache are all updated, and the hit ratio of the shared memory cache is kept high immediately after the start of operation, thereby improving the processing capability as a system.

11 and 12 are structural diagrams of a system in a fifth aspect of the embodiment of the present invention, and a time chart showing the control principle thereof.

The principle of the control according to the fifth aspect is to reduce the latency of read access during contention by selectively allowing the same method as conventionally used to write to a specific address having a high contention frequency. As shown in Fig. 11, whether the data channel 11g or the data bus is used as the same adjustment logical path as that of the update notification bus by providing a data bus 11i for transmitting update data, the processor determines for each write access. Choose.

Fig. 12 shows the difference in timing between the case of using a data channel (P = 0) and the case of using a data bus (P = 1) in the write access issued at the same time. The time from the write access activation until the other processor does not read the data before the update is t _dsd . However, the time until able to read the data after the updating is, with respect to the t _duc1 For (P = 1), when the (P = 0), received a latency effect of the data channel, increasing the t _duc0 do. As long as there is no contention of read access to the same address, this difference has no effect. However, in case of contention, this time difference appears as an increase in latency of the read access. Optionally use (P = 0). As a result, the average latency of read access can be reduced.

It is a figure explaining the 6th aspect of embodiment of this invention.

FIG. 13A is a time chart of control in the sixth aspect.

The sixth aspect applies the control principle of the fifth aspect to the system configuration of the first to fourth aspects as it is, and updates data without performing physical transfer of update data for a specific write access. . Specifically, the data to be written to the address on the shared memory space is made to correspond in advance to a specific address generated by the processor core, and when the write access to the specific address is issued, the reservation is made at the time the update notification is issued. Treated data is transmitted as update data. In this method, only a small amount of data can be handled, but the same effects as those in the fifth aspect can be obtained without providing a conventional data bus having a large number of signal lines.

In the example of FIG. 13A, the write to address 1 is treated as the write of data 1 to the same address in the shared memory space. When the update notification is recognized, the update data can be treated as being delivered at the same time, so that the processing can be performed at the same timing as in the fifth embodiment (P = 1). In addition, since the occupation of the data channel does not occur, when there is subsequent access, the effect of reducing latency related to the access can also be obtained.

For example, in the example of FIG. 13A, when a protocol for treating writes to address 2 as writes to data 0 to address 1 is provided and used in combination, the overhead of access contention is small, and therefore, to other processors. It is possible to provide the software with a function as a two-value flag at which the reflection time is also high (Fig. 13 (b)).

14 is a more detailed system block diagram based on the embodiment of the present invention. The system is composed of ten processors 14a-1 to 14a-10 and a bus arbiter / repeater 14b. The bus arbiter and repeater provide completely independent functions, but both blocks are housed in the same unit to simplify system configuration. The update notification bus 14c includes bus blocks BC1 to BC10, bus request signals NR1 to NR10, bus permission signals NG1 to NG10, update notification address NA (30 bits), update notification address mask NM (4 bits), and immediate update data. ND (4 bits), update notification signal NV, update data request signal RV, and immediate update attribute signal NI, and operate in synchronization with BC. The data channels TSD1 to TSD10 and RSD1 to RSD10 utilize all duplex communication channels in which serial transmission lines having transmission bands of about 3 gigabit / sec are opposed to each other. At least two of the processors maintain the entire contents of the shared memory space, one of which responds to the update data request as a master processor.

FIG. 15 is a diagram illustrating an internal configuration of each of the processors 14a-1 to 14a-10 of FIG. 14.

The functional blocks inside the processor are roughly divided into a processor core 15a, a processor bus bridge 15b, an update notification bus bridge 15e, a data channel IF 15h, an update queue 15k, and a shared memory cache 15n. . The functional outline of each part is described below.

(15a) processor core

It is the main processing unit.

(15b) processor bus bridge

Perform comprehensive control of access to the shared memory space.

The control block 15c performs overall control, and the redirector 15d performs bus switching between the functional blocks and converts addresses and data.

(15e) Update Notice Bus Bridge

The update notification bus is controlled.

(15h) data channel IF

Update data is transmitted / received with another processor.

(15k) update queue

Holds an update queue and prints the queue status externally.

(15n) shared memory cache

It maintains data in shared memory space and provides fast access to processor cores.

It is a figure explaining the flow of the signal at the time of the light access of 1st aspect in embodiment of this invention.

The flow is described below. The preceding number of each line corresponds to the number attached to each signal of FIG.

(1) The processor core 16a sets the processor address PA, the processor data PD, and the processor transmission data PT, and transmits the processor write signal PW.

(2) The control logic 16c of the processor bus bridge 16b sets the redirector function control signal FC. The redirector 16d thus echoes the processor address PA to the effective address EA and the cache address CA and the processor data PD to the effective data ED and the cache data CD.

(3) The control logic 16c of the processor bus bridge 16b transmits the update notification transmission signal NS.

(4) The transmission unit 16f of the update notification bus bridge 16e receives NS and transmits the bus request signal NR.

(5) The transmitting unit 16f of the update notification bus bridge 16e receives the bus permission signal NG to obtain an update notification bus.

(6) EA is echoed to update notification address NA, and update notification signal NV is transmitted to all the processors. NA and NV are also looped back to the update notification bus bridge monitoring unit 16g of the own processor.

(7) The monitoring unit 16g of the update notification bus bridge 16e echoes NA as the update notification address SA and receives the NV as the update notification received signal SV when receiving the NV sent by itself. Send. Upon receiving the SV, the update notification is queued in the queue register 16l of the update queue 16k. At this time, the same control is performed on other processors.

(8) The control logic 16c of the processor bus bridge 16b receives the SV and transmits the update data transmission signal US, and the framer 16i of the received data channel IF 16h transmits the contents of EA / ED. Queue to the buffer. After the transmission of the US, an acknowledge signal ACK is transmitted to the processor core, and the access on the processor core side is completed.

(9) In the framer 16i of the data channel IF 16h, data queued to the transmission buffer is built into a packet from time to time, and when completed, SERDES 16j (abbreviation for serializer deserializer) is used to parse a serial signal. It is a function block for converting to a parallel signal or a parallel signal to a serial signal) and is transmitted as the transmission parallel data TPD. SERDES receives it, modulates it with an electrical signal that can be carried in the data channel, and sends update data as a TSD on the transmission serial.

It is a figure explaining the flow of the signal at the time of update data reception based on the 1st aspect of embodiment of this invention.

The flow is described below. The number in front of each row corresponds to the number added to each signal in FIG.

(1) The SERDES 17j of the data channel IF 17h demodulates the received serial data RSD and sends it to the framer 17i as a received parallel data RPD.

(2) The framer 17i of the data channel IF 17h receives the RPD, extracts and expands a packet in the data, sets the update data address UA and update data UD, and transmits the update data reception signal UR. In accordance with this, the UA is set in the queue clear address QCA in the queue register 17l.

(3) The control logic 17c of the processor bus bridge 17b receives the UR and sets the redirector function control signal FC. The redirector l7d thus echoes the UA to the CA and the UD to the CD. If other processing is being performed in the control logic 17c, it waits once and executes this processing as soon as it completes.

(4) The control logic 17c of the processor bus bridge 17b transmits the cache write signal CW, and the shared memory cache 17n receiving this updates the desired data specified in the CA on the CD. In addition, the control logic 17c transmits the queue clear signal QC, and the update queue 17k which has received this clears the QCA set in (2) from the queue register 17l.

FIG. 18 is a diagram illustrating a signal flow during typical read access in which data in the shared memory cache can be used in the first aspect of the embodiment of the present invention.

The flow is described below. The number in front of each line corresponds to the number added to each signal in FIG.

(1) The processor core 18a sets PA and PT, and transmits the processor read signal PR.

(2) The control logic 18c of the processor bus bridge 18b sets the FC, and the redirector 18d echoes the PA to the EA and CA accordingly.

(3) The control logic 18c of the processor bus bridge 18b transmits the CR.

(4) The shared memory cache 18n receives the CR, transmits the unavailable signal NP when the data on the cache designated by the CA is not available, and transmits the cache data CD when it is available. In addition, the comparator 18m of the update queue 18k transmits a contention signal COL when the queue specified by EA is on the queue register.

(5) When neither the NP nor the COL is received, the control logic 18c of the processor bus bridge 18b echoes the CD to the PD, sends an ACK, and access is completed. In the case of receiving the COL, after the release of the CR, the process waits until the release of the COL and releases the processing after the release of the COL (3). Here, the process in the case of receiving NP without receiving COL will be described below.

FIG. 19 is a diagram illustrating a signal flow when data on the shared memory cache cannot be used in read access in the first aspect of the embodiment of the present invention and involves update data request processing.

The flow is described below. The number in front of each line corresponds to the number attached to each signal in FIG. In addition, up to (4) on the way is abbreviate | omitted since it is completely the same as the flow at the time of read access demonstrated in the preceding paragraph.

(5) When the control logic 19c of the processor bus bridge 19b does not receive the COL but receives the NP, the update data request signal RS is transmitted.

(6) The transmitting unit 19f of the update notification bus bridge 19e receives the RS and transmits the bus request signal NR.

(7) The transmission unit 19f of the update notification bus bridge 19e receives the bus permission signal NG to obtain an update notification bus.

(8) EA is echoed to update notification address NA, and update data request signal RV is transmitted to all processors. The NA and RV are also looped back to the update notification bus bridge monitoring unit 19g of the self processor.

(9) The monitoring unit 19g of the update notification bus bridge l9e echoes NA as SA and, upon detecting the RV sent by the magnetic processor, echoes as SV in the magnetic processor. The update queue 19k receives the SV as a cue set signal QS and queues the contents of the SA into the queue register 19l as the cue set address QSA.

(10) Since the queue matching the read access object is queued, the COL is necessarily transmitted from the update queue 19k. Upon reception of the COL, the processor bus bridge 19b waits while performing the update notification and the reception of the update data with the read access pending from the processor core 19a until the COL is released.

(11) Upon receiving the update data request sent in (8), update data is sent from the master processor, and the data channel IF 19h sets the update data address UA and the update data UD, and transmits the update data reception signal UR. do. In accordance with this, the UA is set in the queue clear address QCA of the queue register 19l.

(12) Since the queue for read access is cleared from the update queue 19k, the COL is released.

(13) The control logic 19c of the processor bus bridge 19b receives the release of the COL, controls the FC to control the redirector 19d, and echoes the UA to the CA and the UD to the CD and the PD.

(14) The control logic 19c of the processor bus bridge 19b transmits the cache write signal CW to update the desired data on the shared memory cache on the CD, sends an ACK to the processor core, and completes read access. do.

FIG. 20 is a diagram for explaining the flow of signals in response by the master processor to an update data request transmitted from another processor in the first aspect of the embodiment of the present invention.

The flow is described below. The number in front of each row corresponds to the number attached to each signal in FIG.

(1) When the monitoring unit 19g of the update notification bus bridge 19e detects the RV, it echoes the NA to the SA and transmits the update data request signal SR to the processor.

(2) When the control logic 20c of the processor bus bridge 20b is the master processor, the control logic 20c receives the SR, sets the FC, controls the redirector 20d to echo the SA to the EA and CA, and CDs. Connect to ED. Here, if it is not the master processor, the SR is ignored. In addition, when another process is performed in the control logic 17c, it waits once and executes this process as soon as it completes.

(3) The control logic 20c of the processor bus bridge 20b transmits the CR to the shared memory cache 20n.

(4) The CD is sent out from the shared memory cache 20n and echoed to the ED.

(5) The control logic 20c of the processor bus bridge 20b transmits US, and the update data is sent to the data channel similarly to the update data sending process at the write access.

It is a figure explaining the flow of the signal at the time of write access in the 2nd aspect of embodiment of this invention.

The flow is described below. The preceding number in each row corresponds to the number added to each signal in FIG.

(1) The processor core 21a sets the processor address PA, the processor data PD, and the processor transfer type PT, and transmits data of multiple sizes to the redirector by burst transfer.

(2) The control logic 21c of the processor bus bridge 21b sets the redirector function control signal FC. The redirector 21d accordingly echoes the head address set in the processor address PA to the effective address EA. Further, the burst transferred data size is counted, and the execution address mask EM is calculated therefrom and output. Here, the effective address mask is a signal indicating how many lower bits of the effective address are ignored. Data of a plurality of sizes set in the PD is stored in a buffer inside the redirector.

(3) The control logic 21c of the processor bus bridge 21b transmits the update notification transmission signal NS.

(4) The transmission unit 21f of the update notification bus bridge 21e receives NS and transmits the bus request signal NR.

(5) The transmission unit 21f of the update notification bus bridge 21e receives the bus permission signal NG to obtain an update notification bus.

(6) EA is echoed to update notification address NA, EM is echoed to update notification address mask NM, and update notification signal NV is transmitted to all processors. The NA, NM, and NV are also looped back to the update notification bus bridge monitoring unit 21g of the own processor and received.

(7) The monitoring unit 21g of the update notification bus bridge 21e receives NV, echoes NA to the update setting address SA and NM to the update setting address mask SM, and transmits the update notification reception signal SV. The update queue 21k receives the SV as the cue set signal QS, and queues the contents of the SA into the queue register 21l as the queue set address QSA and the contents of the SM as the cue set address mask QSM.

(8) When the control logic 21c of the processor bus bridge 21b receives the SV, it transmits the update data transmission signal US and sets FC at the same time. The redirector 21d sets accordingly ED as data from the head of the update data stored in the buffer in this order. The framer 21i of the data channel IF 21h receiving this queues the contents of the EA / EM / ED in the transmission buffer. After the transmission of the US, an acknowledge signal ACK is transmitted to the processor core, and the access on the processor core side is completed.

(9) In the framer 21i of the data channel IF 21h, data queued in the transmission buffer is constructed in a packet at any time, and is sent to the SERDES 21j as transmission parallel data TPD from the completion. SERDES receives this, modulates with an electrical signal carried in the data channel, and sends out update data as the transmission serial data TSD.

FIG. 22 is a diagram illustrating a signal flow when receiving update data sent from another processor in the second aspect of the embodiment of the present invention. FIG.

The flow is described below. The number in front of each line corresponds to the number added to each signal in FIG.

(1) SERDES 22j of data channel IF 22h demodulates the received serial data RSD and sends it to framer 22i as received parallel data RPD.

(2) The framer 22i of the data channel IF 22h receives the RPD, extracts and expands a packet in the data, sets the update data address UA and the update address mask UM, and transmits the update data reception signal UR. . In accordance with this, the UA is set in the queue clear address QCA of the queue register 22l. At the same time as UR transmission, update data is set in the UD sequentially from the head data.

(3) The control logic 22c of the processor bus bridge 22b receives the UR and sets the redirector function control signal FC. The UA and the UD are once stored in a buffer in the redirector, the UA is set in the CA, and the head data of the UD is set in the CD. If other processing is being performed by the setting control logic 22c in the CA, the process waits once and executes this processing as soon as it is completed.

(4) The control logic 22c of the processor bus bridge 22b transmits the cache write signal CW, and the shared memory cache 22n which receives this updates the desired data specified in the CA on the CD. Subsequently, the next update data stored in the redirector's buffer is set on the CD, the CA value is incremented by one, and the same cache memory update processing is performed according to the UM setting value, and the update data in the buffer disappears. Repeat until. Thereafter, the queue clear signal QC is transmitted, and the update queue 22k having received it clears the QCA set in (2) from the queue register 22l.

It is a figure explaining the flow of the signal at the time of write access in which update notification was abbreviate | omitted in the 3rd aspect of embodiment of this invention.

The flow is described below. The number in front of each line corresponds to the number added to each signal in FIG.

(1) The processor core 23a sets a data only attribute to the processor transmission type PT and transmits a processor address PA, a processor data PD, and a processor write signal PW.

(2) The control logic 23c of the processor bus bridge 23b sets the redirector function control signal FC. The redirector 23d accordingly echoes the processor address PA to the execution address EA and the processor data PD to the effective data ED.

(3) The control logic 23c of the processor bus bridge 23b sets the data only attribute signal DO and transmits the update data transmission signal US. After the transmission of the US, an acknowledge signal ACK is transmitted to the processor core, and the access on the processor core side is completed.

(4) The framer 23i of the data channel IF 23h receiving the update data transmission signal US and the data only attribute signal DO queues the contents and data only attributes of the EA / ED in the transmission buffer.

(5) In the framer 23i of the data channel IF 23h, data and attributes queued in the transmission buffer are constructed in a packet at any time, and are sent to the SERDES 23j as transmission parallel data TPD from the completion. SERDES receives it, modulates it with an electrical signal that can be carried in the data channel, and sends update data as the transmission serial data TSD.

FIG. 24 is a diagram for explaining the flow of a signal when receiving update data in which the update notification sent from another processor is omitted in the third aspect of the embodiment of the present invention.

The flow is described below. The number in front of each line corresponds to the number added to each signal in FIG.

(1) SERDES 24j of data channel IF 24h demodulates the received serial data RSD and sends it to framer 24i as received parallel data RPD.

(2) The framer 24i of the data channel IF 24h receives the RPD, extracts and expands a packet in the data, sets the update data address UA, update data UD, data only attribute DO, and receives update data. Transmit the signal UR.

(3) The control logic 24c of the processor bus bridge 24b receives the update data received signal UR and the data only attribute signal DO to set the redirector function control signal FC. The redirector 24d accordingly echoes the UA to the cache address CA and the UD to the cache data CD. If other processing is being performed by the control logic 24c, it waits once and executes this processing as soon as it completes.

(4) The control logic 24c of the processor bus bridge 24b transmits the cache write signal CW, and the shared memory cache 24n receiving this updates the desired data specified in the CA on the CD.

It is a figure explaining the flow of the signal at the time of the processor extended in the system making the whole data transmission request in the cache fill operation | movement in 2nd aspect of embodiment of this invention.

The flow is described below. The number in front of each row corresponds to the number attached to each signal in FIG.

(1) The control logic 25c of the processor bus bridge 25b transmits RS and IS simultaneously as all data transmission request signals when it detects that its own processor is added to the system.

(2) The transmission unit 25f of the update notification bus bridge 25e receives RS and IS and transmits a bus request signal NR.

(3) The transmission unit 25f of the update notification bus bridge 25e receives the bus permission signal NG to obtain an update notification bus.

(4) The transmitter 25f of the update notification bus bridge 25e simultaneously transmits the RV and NI.

It is a figure explaining the flow of the signal at the time of a master processor performing whole data transmission in response to a whole data transmission request in the cache fill operation | movement in 4th aspect of embodiment of this invention.

The flow is described below. The preceding number of each line corresponds to the number attached to each signal of FIG.

(1) When the monitoring unit 26g of the update notification bus bridge 26e of the master processor receives N1 at the same time as the RV, the monitoring unit 26g simultaneously transmits the SR and the SI.

(2) When the control logic 26c of the processor bus bridge 26b receives SR and SI at the same time, the control logic 26c interprets it as a total data transmission request signal and interprets the head address of the shared memory space as the transmission start address and the next transmission address. Remember as.

(3) When another processor is added to the system and the control logic 26c of the master processor receives the entire data request signal again, the control logic 26c first stores the transmission address and then stores the transmission address as the transmission start address. .

(4) The control logic 26c sets the redirector function control signal FC when the queue empty signal QE is valid and no other processing is required, and the redirector 26d stores the transmission address first and then transmits the address. Is set in the cache address CA, and the control logic 26c transmits the cache read signal CR.

(5) The shared memory cache 26n receives the CR and transmits the data on the cache designated by the CA to the cache data CD.

(6) The redirector 26d of the processor bus bridge 26b sets the previously set CA to the effective address EA and echoes the CD to the effective data ED. The control logic 26c sets the data only attribute DO and transmits the update data transmission signal US. The framer 26i of the data channel IF 26h receiving this queues the contents and data only attributes of the EA / ED in the transmission buffer.

(7) The control logic 26c of the processor bus bridge 26b stores the address following the transmitted address as the next transmission address. When the transmitted address reaches the last address of the shared memory space, the address of the head of the shared memory space is stored as the next transmission address. If the next transmission address matches the previously stored transmission start address, all data transmission ends.

(8) The procedure of (3)-(7) is repeated, and data is sent sequentially.

(9) In the framer 26i of the data channel IF 26h, data queued in the transmission buffer is constructed in a packet at any time, and is sent to the SERDES 26j as transmission parallel data TPD from the completed one. SERDES receives it, modulates it with an electrical signal that can be carried in the data channel, and sends out data as a transmission serial data TSD.

It is a figure explaining the flow of the signal at the time of the processor extended in the system to receive the whole data in the cache fill operation | movement in 4th aspect of embodiment of this invention.

The flow is described below. The number in front of each line corresponds to the number added to each signal in FIG.

(1) When the control logic 27c receives the processor read signal PR or the processor write signal PW during the entire data reception operation, the control logic 27c holds this request. Even during the entire data reception operation, queuing and clearing to the update queue are performed in the flows shown in Figs. 16 and 17, respectively.

(2) The SERDES 27j of the data channel IF 27h demodulates the received serial data RSD and sends it to the framer 27i as a received parallel data RPD.

(3) The framer 27i of the data channel IF 27h receives the RPD, extracts and expands a packet in the data, sets the update data address UA, update data UD, data only attribute DO, and updates data reception signal. Send UR.

(4) The control logic 27c of the processor bus bridge 27b receives the UR and sets the redirector function control signal FC. The redirector 27d echoes the UA to the cache address CA and the UD to the cache data CD accordingly. If other processing is being performed in the control logic 27c, it waits once and executes the processing as it completes.

(5) The control logic 27c of the processor bus bridge 27b transmits the cache write signal CW. Since the data only attribute DO is received, the queue clear signal QC is not transmitted.

(6) The shared memory cache 27n receiving the cache write signal CW updates the desired data specified in the CA and CD, and transmits an unavailable signal NP when the data is not available in the state before the update. .

(7) The control logic 27c of the processor bus bridge 27b measures the number of times the unusable signal NP is received during the entire data reception operation to recognize that the entire area of the shared memory cache is filled with valid data. The data receiving operation ends.

(8) When there is a processor read signal PR or a processor write signal PW held when the entire data reception operation is completed, the operation is started.

It is a figure explaining the flow of the signal at the time of light access based on the 5th aspect of embodiment of this invention.

The flow is described below.

(1) The processor core 28a sets the PA, PD and PT to transmit the PW.

(2) The control logic 28c of the processor bus bridge 28b sets the redirector function control signal FC. The redirector 28d accordingly echoes the processor address PA to the effective address EA and the cache address CA and the processor data PD to the effective data ED and the cache data CD.

(3) The control logic 28c of the processor bus bridge 28b transmits the update notification transmission signal NS. In addition, when the PA is in the specified address space, it immediately sends the update attribute transmission signal IS.

(4) The transmission unit 28f of the update notification bus bridge 28e receives NS and transmits NR.

(5) The transmitting unit 28f of the update bus bridge 28e receives the NG and obtains an update notification bus.

(6) EA is echoed to update notification address NA, IS to immediate update attribute signal NI, and ED to immediate update data ND, respectively, and update notification signal NV is transmitted to all processors. The NA, ND, NV, and NI are also looped back to the update notification bus bridge monitoring unit 28g of the magnetic processor.

(7) When the monitoring unit 28g of the update notification bus bridge 28e receives the NV together with the NI, it immediately echoes into the self processor as the update signal SI. The same operation is performed on other processors.

(8) The control logic 28c of the processor bus bridge 28b sets the redirector function control signal FC. The redirector 28d accordingly echoes the SA to the CA and the SD to the CD. The same operation is performed on other processors. At this time, when the processor bus bridge 28b is performing other processing, this processing is prioritized after completion of the processing.

(9) The control logic 28c of the processor bus bridge 28b transmits the cache write signal CW, and the shared memory cache 28n which receives this updates the desired data specified in the CA on the CD. The same operation is performed on other processors.

(10) An ACK is sent to the processor core, and access on the processor core side is completed.

The write access based on the sixth aspect of the embodiment of the present invention uses reservation data when writing to a specific address, and the flow is almost similar to the write access in the fifth aspect. The following points are differences.

(8) The redirector 28d of the processor bus bridge 28b ignores the SD and generates the reserved data corresponding to the SA and outputs it to the CD when the SA is interpreted as a specific address using the reserved data for the access. .

As described above, in the shared memory type multiprocessor system constituted by a processor having a shared memory cache, the time required for coherency guarantee and the time required for data transmission are clearly separated by the application of the present invention. The problem existing in the prior art in accessing the shared memory space is solved in the following points.

Minimize bus occupancy time and eliminate unnecessary latency increases

Conceal latency in data transmission paths, thereby facilitating bandwidth expansion

As a result, the high speed of the shared memory cache can be utilized to the maximum, and both the bandwidth and the latency of the shared memory space access can be improved, thereby contributing to the improvement of the processing capacity of the system.

Claims (10)

 A multiprocessor system in which a plurality of processors each having a shared memory cache and at least one shared memory are coupled to each other, Dedicated line means for exclusively transmitting and receiving data between the processor and the shared memory for updating the data in the shared memory area; Global bus means that the license is adjusted by the arbiter to send data update notifications to each processor. Including; Sending the update notification of the data from the processor and the data to be used for the update are independently performed. In each processor and the shared memory, by receiving the update notification, access to the address indicated by the update notification is restricted. And access to the address after the data of the address of the shared memory area is updated by the data to be used for the update arriving at each processor and the shared memory. The method of claim 1, The dedicated line means includes repeater means for connecting a line from the processor to the shared memory. The method of claim 2, The dedicated line means comprises a dedicated line provided in each of the plurality of processors. The method of claim 1, And updating the plurality of update data units in a single update by associating a plurality of update data with the update notification. The method of claim 4, wherein In the update notification, the size of data used for updating in one update is variable. The method of claim 1, Update of data in the shared memory space that does not require maintenance of cache coherency is performed by sending update data to an address of data that does not require maintenance of the cache coherency without transmitting the update notification. And a multiprocessor system. The method of claim 1, And when a new processor is added to the multiprocessor system, transferring the contents of the shared memory cache of another processor to the shared memory cache of the processor, and thereafter operating the new processor. The method of claim 1, And means for transmitting update notification and data for update using said global bus means, and for updating said shared memory area. The method of claim 1, For access to a specific address in the shared memory area, only the update notification is transmitted and received, and the processor or shared memory which has received the update notification updates the address using predetermined data. Processor system. A method of accelerating memory access in a multiprocessor system in which a plurality of processors each having a shared memory cache and shared memory are coupled to each other, the method comprising: In the updating of data in the shared memory area, transmitting and receiving data to be used for the update via a dedicated line dedicated to send and receive data between the processor and the shared memory; Sending and receiving update notification of data to each processor through a global bus whose license is adjusted by the arbiter, Sending the update notification of the data from the processor and the data to be used for the update are independently performed. In each processor and the shared memory, by receiving the update notification, access to the address indicated by the update notification is restricted. Authorizing access to the address after the data of the address in the shared memory area is updated by the data to be used for the update arriving at each processor and the shared memory; Method comprising a.

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