KR100745675B1 - Apparatus and method for switching packet data using the atca platform - Google Patents

Abstract

The present invention relates to a high-performance packet switching apparatus and method applying the ATCA standard platform, and the packet switching apparatus according to the present invention includes a packet processing apparatus and a packet which are mounted in a node slot of an ATCA platform through a fabric interface defined in ATCA. Packet switching unit for exchanging; A switch controller configured to collect and control the configuration and various state information of the packet switching unit; And a redundancy and DMA control unit for converting data received from the switch control unit into serial data and transferring the data to the packet switching unit, and converting the serial data from the packet switching unit into parallel data for a DMA operation and transferring the data to the switch control unit. It is characterized by including.

ATCA, Packet Switching Unit, Redundancy, Fabric Interface, Packet Processing Unit

Description

APAPATUS AND METHOD FOR SWITCHING PACKET DATA USING THE ATCA PLATFORM

1 is a view showing the overall structure of a switching system to which the ATCA standard platform to which the present invention is applied.

2 is a diagram showing the device configuration of the ATCA standard platform.

3 is a diagram illustrating the specification and connection state of the backplane of the ATCA platform.

4 is a block diagram of a high performance packet switching device for an ATCA platform according to an embodiment of the present invention.

5 is a block diagram of a DMA controller according to an exemplary embodiment of the present invention.

6 is a block diagram of a redundant control unit according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100: main processor device 110: packet switching device

120: packet processing apparatus 201, 202: node slot

203: switch slot 300: maintenance bus

301: base interface 302: fabric interface

303: update channel 304: common clock signal

305: user-defined area 400: switch control unit

403: redundancy and DMA control unit 404: packet switching unit

409: control message switch

The present invention can perform a high performance packet switching function between a plurality of packet processing devices while complying with the ATCA backplane standard, and realize a redundancy function to apply a high performance packet switching to the ATCA standard platform that can guarantee high reliability of the packet forwarding path. An apparatus and method are provided.

In the future, the information and communication network is expected to integrate computers and network devices so that high-speed data transmission, protocol, information processing, storage, and computing will be solved in one platform, and existing servers and network devices will be gradually transformed into integrated systems. have. In addition, since 2007, more than hundreds of billions of dollars are expected worldwide, but the situation is not easily optimistic due to the contraction of the telecommunications market and management of investment risk of operators. In such a situation, efforts to continuously lower the price of communication equipment are required, and when introducing a new service, an easily and quickly applicable broadband communication network must be realized.

The Industrial Industrial Consortium (PICMG), the industry consortium (PICMG), has been in force since late 2001 to address this market situation and to facilitate the convergence of telecommunications and computing and the adoption of new services in accordance with the development of communication technology. A basic standard platform structure is presented in the Advanced Telecom Computing Architecture (TCA) standard platform.

The Advanced TCA (hereinafter referred to as 'ATCA') convergence technology is a future-oriented platform structure for integrating computer and communication equipment based on high performance computing bus, high speed switching, and serial-deserial (SERDES) technology. It is led by more than 100 companies such as telecommunications companies and chip vendors. From a telecom and network operator's perspective, new services and performance upgrades can be facilitated and reduced with a single platform. From an equipment manufacturer's perspective, the role is clear to chip vendors, board vendors, and system vendors. It has the strength of gaining an edge in technology and price competitiveness over integrated equipment makers.

On the other hand, since the switching device in the existing communication system has defined its own system structure and signals, there is no system-to-system compatibility with other devices having the same function. Therefore, there is an urgent need for the development of a high performance switching device utilizing a standard platform such as ATCA as described above.

An object of the present invention for solving the above problems is to perform a high-performance packet switching function between a plurality of packet processing devices while complying with the ATCA backplane specification, and by realizing the redundancy function to ensure high reliability for the packet forwarding path To provide a high performance packet switching device and method applying the ATCA standard platform.

A packet switching device according to the present invention for achieving the above object, the packet switching unit for exchanging a packet with each packet processing device mounted in a node slot of the ATCA platform through a fabric interface defined in ATCA; A switch controller configured to collect and control the configuration and various state information of the packet switching unit; And a redundancy and DMA control unit for converting the data received from the switch control unit into serial data and transferring the data to the packet switching unit, and converting the serial data from the packet switching unit into parallel data for a DMA operation and transferring the data to the switch control unit. Characterized in that.

In addition, the packet switching providing method according to the present invention for achieving the above object, the first buffer for driving the reception request signal in a valid state when the packet storage state is not full in the reception buffer of the DMA control unit configured in the packet switching device; step; A second step of, at the switch control unit of the packet switching device, receiving the reception request signal and transmitting a reception valid signal to the reception control unit of the DMA control unit; Transmitting data to be transmitted to the reception buffer through a reception data signal when there is data to be transmitted by the switch controller; And a fourth step of driving, by the switch controller, a reception completion signal in the last DMA bus transfer period when all of the data is transferred.

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The present invention is a communication and computing system that provides a fast and reliable packet switching function. However, switching devices in the existing communication systems have defined their own system structures and signals, and thus are not compatible with other devices having the same function. Therefore, in the present invention, it is possible to ensure mutual compatibility by implementing a switching system and apparatus according to the ATCA standard.

Meanwhile, the packet switching device defined in the ATCA standard platform specification includes a base interface for exchanging power and maintenance bus signals and control messages defined in the backplane standard, a fabric interface for packet forwarding, and It must accept both common clock signals and update channels. In addition, it provides a redundancy function for high reliability of the packet switching device.

Meanwhile, the above-described Advanced Telecom Computing Architecture (ATCA) platform is used to design a system according to PICMG's standardized standard to shorten development period and to achieve economic efficiency. Therefore, the packet switching system according to the present invention applied to the above standard may be composed of one or more packet processing apparatus, main processor apparatus, packet switching apparatus, and the like.

The packet switching device and the plurality of packet processing devices perform packet exchange according to a standard defined in the ATCA fabric interface for packet delivery. In addition, the packet processing apparatus according to the present invention includes a base interface for exchanging power and maintenance bus signals and control messages defined in the ATCA backplane standard, a fabric interface for packet forwarding, and a common clock. It will accept both signal and update channels.

Meanwhile, as described above, the ATCA standard platform establishes a standard for interworking between individual devices constituting a communication system and a computing system, thereby shortening the development period and economical efficiency in developing individual devices suitable for a specific purpose. It is aimed. Accordingly, packet exchange in the ATCA platform is performed through a fabric interface between a plurality of packet processing apparatuses centering on a packet switching apparatus.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that reference numerals and like elements among the drawings referred to herein are represented by the same reference numerals and symbols as much as possible even though they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

First, referring to Figures 1 to 3, the structure of the ATCA standard platform to which the present invention is applied will be described in detail.

1 is a view showing the structure of a switching system to which the ATCA standard platform according to the present invention is applied.

Referring to FIG. 1, the ATCA standard platform according to the present invention has a structure in which a main processor device 100, a packet switching device 110, and a plurality of packet processing devices 120 are interconnected.

The packet switching device 110 performs a high speed packet switching function between the plurality of packet processing devices 120 and may be configured in a redundant structure. In this case, a control message exchange device (not shown) has a function of exchanging control messages corresponding to packet routing table information and state information of each device between the main processor device 100 and the packet processing device 120. It may be composed of a redundant structure.

The packet processing apparatus 120 determines a forwarding path to the next hop for an IP packet received from the outside, and performs a packet header change function to perform a switch module (that is, the packet switching apparatus 110). )), And the packet received from the packet switching device 110 has a reassembly function of the packet and a control function for packet traffic.

The main processor device 100 may store routing information and various state information necessary for packet delivery in the platform, perform overall control functions of the platform, and have a dual structure.

2 is a view showing the device configuration of the ATCA standard platform according to an embodiment of the present invention.

Referring to FIG. 2, an ATCA standard platform according to an embodiment of the present invention may be configured with 14 slots. This can be broadly divided into node slots 201 and 202 and switch slots 203 (or hub slots).

Input / output (I / O) devices and service devices such as the main processor device 100 and the packet processing device 120 may be mounted in the node slots 201 and 202. In addition, the packet switching device 110 may be mounted in the switch slot 203.

3 is a diagram showing the connection of the type of backplane standard signal configuration of the ATCA platform according to the present invention.

Referring to FIG. 3, backplane standard signals of the ATCA platform are allocated to Zone 1, Zone 2, and Zone 3. In area 1, a power input signal and a system state management and maintenance bus signal 300 are defined. In the area 2, a base interface signal 301 for exchanging control information between various devices located in a node slot, and a fabric interface for exchanging packet data between node slots ( 302, an update channel 303 for exchanging state information between two types of combined devices, a common clock signal 304, and the like are defined in the standard. The area 3 305 is an area defined to be used according to a user's needs.

Meanwhile, the fabric interface 302 of the region 2 may define topologies such as a star, dual dual star, and full mesh, and in the present invention, the full mesh By using a topology approach, we construct a fabric interface for a 10Gbps interface. In contrast, the base interface 301 of the region 2 is configured in a dual star topology.

Hereinafter, a detailed configuration of a packet switching device 110 that provides high performance packet switching according to an embodiment of the present invention will be described with reference to FIGS. 4 to 6.

4 is a block diagram of a packet switching apparatus 110 of the ATCA standard according to an embodiment of the present invention.

Referring to FIG. 4, the packet switching apparatus 110 according to an exemplary embodiment of the present invention includes a switch controller 400, a flash 401, a memory 402, redundancy and a direct memory access (DMA) control unit 403, and a packet. The switching unit 404, the temperature sensing unit 405, the maintenance and power control unit 406, the clock generator 407, the power conversion unit 408, and the control message switch unit 409 may be configured.

The switch control unit 400 collects and controls the configuration and various state information of the packet switching unit 404 and the control message switch unit 409. In this case, the control of the packet switching unit 404 is performed through the redundancy and the DMA control part of the DMA control unit 403.

Meanwhile, the redundancy and DMA control unit 403 plays a role of redundancy control and DMA control, and may be divided into a redundancy control unit and a DMA control unit according to an implementation method.

The redundancy and DMA control unit 403 converts the data continuously transmitted through the 16-bit parallel bus to serial data and transfers the serial data from the packet switching unit 404 to the packet switching unit 404. The data is converted into parallel data for operation and transferred to the switch controller 400.

The packet switching unit 404 exchanges a packet with each packet processing device 120 mounted in a node slot of the ATCA platform through the fabric interface 411. At this time, the fabric interface 411 is composed of four pairs of differential signals and when one differential signal follows the Infiniband standard of 3.2Gbps, it is possible to support the performance of 10Gbps by supporting a packet transfer rate of 12.8Gbps. These four pairs of differential signals are Tx = {TXn [0] +/-, TXn [1] +/-, TXn [2] +/-, TXn [3] +/-} Rx = {RXn [0] +/-, RXn [1] +/-, RXn [2] +/-, RXn [3] +/-}. Here, n represents the node number of the node to be connected.

The maintenance and power control unit 406 performs management functions such as failures, maintenance information, and status information in the packet switching device 110, and receives a corresponding command from the upper platform management block through the maintenance bus. To pass. In addition, a function of controlling the order in which power is applied to the packet switching device with respect to various DC power sources is performed.

The temperature detector 405 detects the temperature and ambient temperature of the packet switching unit 404 and transmits the temperature information upward through the maintenance and power control unit 406. The clock generator 407 generates a clock signal of 160 MHz to provide a packet forwarding reference clock to the packet switching unit 404, whereby the fabric interface 411 by the packet forwarding reference clock in the packet switching unit 404. Packet forwarding). In addition, the clock generator 407 provides a synchronous clock with the packet processing apparatuses 120 mounted in the node slots 201 and 202 of the ATCA platform.

The power converter 408 performs a DC / DC power conversion function. For example, 48V DC power is supplied from the outside to generate various power sources such as 5.0V, 3.3V, 2.5V, 1.5V, which are necessary power inside the packet switching device.

The control message switch unit 409 performs a base interface matching function, which is a standard of the ATCA platform, and performs an Ethernet switch function of 10/100/1000 Mbps. That is, the control message switch 409 is connected to the nodes of each packet processing apparatus 120 in a dual star manner through the base interface 412.

Hereinafter, the structure of the redundancy and DMA controller 410 for performing redundancy control and DMA control according to an embodiment of the present invention will be described in detail with reference to FIGS. 5 and 6. First, a detailed structure of a DMA control part that performs a DMA control function in the redundancy and DMA control unit 410 will be described with reference to FIG. 5, and a detailed structure of the redundancy control part will be described with reference to FIG. 6. In the following description, for convenience of description, the DMA control part of the redundancy and DMA control unit 410 will be referred to as a DMA control, and the redundancy control part will be referred to as a redundancy control unit.

5 is a block diagram of a DMA controller according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the DMA control function of the DMA controller according to an exemplary embodiment of the present invention is used to increase data transfer efficiency between the switch controller 400 and the packet switching unit 404 described above. The DMA control unit includes a reception buffer (RxFIFO) 500, a reception control unit 501, a parallel / serial conversion unit 502, a transmission buffer (TxFIFO) 503, a transmission control unit 504, a serial / parallel conversion unit 505, and the like. It can be configured as.

That is, the DMA controller analyzes a reception buffer 500 for storing parallel data received from the switch controller 400 and a reception controller 501 for performing a serial transmission control function by analyzing a packet stored in the reception buffer 500. And a parallel-to-serial converter 502 for converting parallel data of the receive buffer 500 into serial data, and performs a reception function. The serial data received from the packet switching unit 404 is converted into parallel data. A serial / parallel conversion unit 504, a transmission buffer 503 for storing the parallel-converted data received from the packet switching unit 404, and a transmission control unit for performing a transmission control function of the transmission buffer 503. In operation 505, the transmitting function is performed.

On the other hand, when the packet storage state is not full in the reception buffer 500, the reception request signal RxREQ is driven in a valid state, and after the switch control unit 400 receives the reception request signal, The reception valid signal RxACK is transmitted to the reception control unit 501. In this case, when there is content to be transmitted from the switch controller 400, the switch control unit 400 transmits the received data signal RxDATA to the reception buffer 500.

At this time, the transmission of the data signal is delivered in a burst (burst) until all the transmission data is transmitted. Therefore, when all data is transferred, the switch controller 400 drives the reception completion signal RxDONE in the last DMA bus transfer cycle.

As such, when the reception completion signal RxDONE is driven, the reception control unit 501 analyzes information such as reading, writing, and length of a forwarding packet, and then stores the information in the header area of the parallel / serial conversion unit 502. The parallel / serial converter 502 transmits the data to the packet switching unit 404 by synchronizing the serial transmission data with the serial transmission / reception clock. At this time, the serial transmission valid signal is driven and transmitted.

On the other hand, when the serial / parallel converter 504 receives a serial receive valid signal and serial receive data from the packet switching unit 404 in accordance with a serial transmission / reception synchronous clock, the serial / parallel converter 504 is serial. The data is converted into parallel data and stored in the transmission buffer 503. In this case, when the last data is received, the serial / parallel conversion unit 504 notifies the end of the data to the transmission control unit 505.

As such, when data is stored in the transmission buffer 503, the transmission controller 505 notifies the switch controller 400 that there is data to be transmitted in the transmission buffer 503 by driving the transmission request signal TxREQ. In this case, the switch controller 400 reads data stored in the transmission buffer 503 while driving the transmission valid signal TxACK. If the data read from the transmission buffer 503 after the process is the last data transferred from the transmission buffer 503, the transmission control unit 505 drives the transmission completion signal TxDONE to control the switch control unit. 400 is notified that the end of the delivery data.

6 is a block diagram of a redundant control unit according to an embodiment of the present invention.

As described above, the packet switching apparatus 110 according to the exemplary embodiment of the present invention is configured in redundancy in order to ensure high reliability for packet delivery of the platform. Accordingly, the packet switching apparatus 110 according to an exemplary embodiment of the present invention performs a redundancy control function by a duplication control unit (that is, a duplication and DMA control unit 410) in two packet switching devices.

Referring to FIG. 6, the redundancy control unit according to the embodiment of the present invention may include a first redundancy control unit 600 for the first packet switching device located on the A side and a second packet switching device located on the B side. 2 may be configured as a redundancy control unit 601.

That is, the first redundancy control unit 600 means a redundancy control unit configured in the first packet switching device, and the second redundancy control unit 601 means a redundancy control unit configured in the second packet switching device.

Meanwhile, each of the redundancy control units 600 and 601 drives an activation signal ACTIVE indicating activation of the switch device. At this time, each of the redundancy control units 600. 601 receives the hardware location information signal from the backplane to recognize where its position is, namely, A side or B side. The ACTIVE signal is transmitted through the respective signal buffers 604 and 605 to the update channel 610 defined by the specifications of the ATCA backplane, respectively.

The update channel 610 represents an ATCA backplane, and the update channel 610 is updated with information through update signal lines 606 and 607 connected to the respective signal buffers 604 and 605. At this time, the two update signal lines 606 and 607 represent the A side ACTVIE state and the B side ACTIVE state, respectively.

On the other hand, the duplex control unit (600, 601) of both sides in the ACTIVE state to drive the transition to the active state, while driving the ACTIVE signal if the other side is not active (ACTIVE) state. On the other hand, if the other party is already activated, the user transitions to the inactive state. At this time, if it is activated at the same time, the A side may be in the ACTIVE state. Accordingly, the packet forwarding paths through the fabric interfaces 608 and 609 of the packet switching units 602 and 603 are determined by the activation state signals ACTIVE driven by the duplication control units 600 and 601.

The packet switching providing method using the ATCA platform according to the present invention can be embodied as computer readable codes on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and also include those implemented in the form of carrier waves such as transmission over the Internet. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the claims below, but also by those equivalent to the claims.

As described above, the present invention has the advantage of being able to perform a large packet switching function by connecting a dual star topology between a packet switching device and a plurality of packet processing device nodes while complying with the ATCA backplane standard. In addition, if the fabric interface specification for packet forwarding is satisfied, other service nodes of 10Gbps high speed can be connected and configured, and redundancy can be realized to realize high reliability of the packet forwarding path. .

Claims (11)

A packet switching unit for exchanging a packet with each packet processing apparatus mounted in a node slot of an ATCA platform through a fabric interface defined in ATCA; A switch controller configured to collect and control the configuration and various state information of the packet switching unit; And a redundancy and DMA control unit for converting the data received from the switch control unit into serial data and transferring the data to the packet switching unit, and converting the serial data from the packet switching unit into parallel data for a DMA operation and transferring the data to the switch control unit. Packet switching device for an ATCA platform, characterized in that. The method of claim 1, And a maintenance and power control unit for performing management functions such as faults, maintenance information, and status information in the packet switching device. The method of claim 1, And a temperature sensing unit configured to detect a temperature of the packet switching unit and an ambient temperature, and to transmit temperature information upward through the maintenance and power control unit. The method of claim 1, And generating a predetermined clock signal to provide a packet forwarding reference clock to the packet switching unit, wherein the clock switching unit further enables a packet forwarding through the fabric interface by the packet forwarding reference clock. Packet switching device for ATCA platform characterized by. The method of claim 1, wherein the packet switching device, The packet switching device for the ATCA platform, characterized in that it further comprises a power conversion unit for receiving one or more power supplies in the packet switching device received from the DC power source from the outside. The method of claim 1, wherein the packet switching device, The packet switching device for the ATCA platform, characterized in that it performs a base interface matching function, which is the standard of the ATCA platform, and performs a fast Ethernet switch function. The method of claim 1, wherein the redundancy and DMA control unit, A reception buffer for storing parallel data received from the switch controller; A reception controller which analyzes the packet stored in the reception buffer and performs a serial transmission control function; A parallel / serial converter for converting parallel data of the receive buffer into serial data; A serial / parallel converter for converting serial data received from the packet switching unit into parallel; A transmission buffer for storing the data converted in parallel received from the packet switching unit; And And a transmission control unit performing a transmission control function of the transmission buffer. The method of claim 1, wherein the redundancy and DMA control unit, Packet switching device for the ATCA platform characterized in that it receives the hardware location information signal from the backplane, recognizes its location, and drives the activation signal indicating the activation of the switch device corresponding to it to the update channel . A first step of driving the reception request signal to a valid state when the packet storage state is not full in the reception buffer of the DMA controller configured in the packet switching device; A second step of, at the switch control unit of the packet switching device, receiving the reception request signal and transmitting a reception valid signal to the reception control unit of the DMA control unit; A third step of transferring the data to be transmitted to the reception buffer through a reception data signal when there is data to be transmitted by the switch controller; And And a fourth step of driving, by the switch control unit, a reception completion signal in a final DMA bus transfer period when all of the data is transferred. The method of claim 9, wherein after the fourth step, A fifth step of, when the reception completion signal is driven, the reception controller analyzes information such as reading, writing, and length of a transmission packet and inserts the analyzed information into a header area of a parallel / serial converter; And And a sixth step of synchronizing serial transmission data with a serial transmission / reception clock from the parallel / serial conversion unit to a packet switching unit to transmit data. The method of claim 9, A seventh step in which each of the two redundancy control units redundantly configured in the packet switching device receives hardware location information and recognizes its own location; And Each of the two redundancy control units checks the state of the other side redundancy control unit when it recognizes its position, and transitions to an active state when the other side redundancy control unit is in an inactive state, and transitions to an inactive state when the other redundancy control unit is in an activated state. The packet switching method for an ATCA platform, further comprising the eighth step.

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