KR100718045B1 - Circuit and method for outputting data in semiconductor memory apparatus - Google Patents

Abstract

The data output circuit of the semiconductor memory device of the present invention may include a clock, an input / output instruction signal, and a drive when data selection means and a test signal are selected to select some of a plurality of data transmitted from a global input / output line under control of a selection control signal. And output driving means for generating a control signal, data output from the data selection means, sequentially transmitted after being latched, data of the global input / output line, or the selection control signal to generate output data.

Semiconductor memory device, data output, global input / output line

Description

Circuit and Method for Outputting Data in Semiconductor Memory Apparatus

1 is a configuration diagram of a data output circuit of a semiconductor memory device according to an embodiment of the present invention;

2 is a configuration diagram of a data output circuit of a semiconductor memory device according to another embodiment of the present invention;

3 is a block diagram showing the configuration of the output driving means shown in FIGS. 1 and 2;

4 is a circuit diagram showing the detailed configuration of the signal combination unit shown in FIG.

5 is a circuit diagram showing the detailed configuration of the pull-up unit shown in FIG.

6 is a circuit diagram showing a detailed configuration of the pull-down section shown in FIG.

<Description of the symbols for the main parts of the drawings>

10: data selection means 20: latch means

30: output drive means 310: signal combination unit

320: pull-up unit 330: pull-down unit

The present invention relates to a data output circuit and a method of a semiconductor memory device, and more particularly, to a data output circuit and a method of a semiconductor memory device for improving the test efficiency for the output data.

In general, a semiconductor memory device includes a data output circuit for selectively latching and driving data transmitted through a global input / output line GIO from a plurality of memory banks during data output. In this case, a plurality of data is transferred from the plurality of memory banks to the global input / output line GIO, and a selection control signal is used to select some of the plurality of data. Thereafter, the data bits selected by the selection control signal are latched, and each bit is selected by the latch output instruction signal and sequentially output. The data bits thus output are then driven and output through the data output pads.

As described above, each data bit is output from the plurality of memory banks to the global input / output line GIO and transferred to the data output circuit. However, at this time, the distance between the plurality of memory banks and the global input / output line GIO is not the same. This difference in distance reduces the timing margin between the data bits of the global input / output line GIO and the selection control signal, and such timing margin reduction causes side effects that make it difficult to output valid data. In particular, due to the recent trend in which semiconductor memory devices are increasingly implemented at high speed and high integration, the difficulty of timing control has been a technical limitation of semiconductor memory devices.

However, according to the related art, there is no easy way to test the timing margin between the data bits of the global input / output line GIO and the selection control signal. Therefore, only valid data was output through the data output pad. When invalid data is output, each of the components of the global input / output line (GIO) and the data output circuit has to be measured separately. This acted as a factor that hinders the implementation of a more stable data output operation of the semiconductor memory device, it has been a factor that lowers the test efficiency of the semiconductor memory device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and when a valid data is not outputted at the time of data output, the timing of data transfer from the global input / output line and the selection control signal for selecting some of the data of the global input / output line There is a technical problem to provide a data output circuit and method of a semiconductor memory device that improves the efficiency of data output test by measuring the enable timing to determine the cause of the malfunction.

According to another aspect of the present invention, there is provided a data output circuit of a semiconductor memory device, comprising: data selection means for selecting some of a plurality of data transmitted from a global input / output line according to control of a selection control signal; And when a test signal is enabled, a clock, an input / output instruction signal, a driving control signal, data output from the data selection means, latched, and sequentially transmitted, data of the global input / output line, or the selection control signal are input and output data. Output driving means for generating a; characterized in that it comprises a.

In addition, the data output method of the semiconductor memory device of the present invention comprises the steps of: a) selecting some of the plurality of data of the global input / output line under the control of the selection control signal; And b) when the test signal is enabled, receives a clock, an input / output instruction signal, a driving control signal, data output in the step a), latched, and sequentially transmitted, data of the global input / output line, or the selection control signal. Generating data; characterized in that it comprises a.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram of a data output circuit of a semiconductor memory device according to an exemplary embodiment of the present invention, and illustrates a test mode for measuring timing of data transmitted from a global input / output line.

The illustrated data output circuit is transmitted from the data selecting means 10 and the data selecting means 10 for selecting some of a plurality of data transmitted from the global input / output line GIO under the control of the selection control signal scnt. The latch means 20 and the test signal tst for enabling the latched data to be output as rising data rdata and polling data fdata under the control of the latch output instruction signal lto are enabled. When the signal is transferred from the rising clock rclk, the falling clock fclk, the input / output instruction signal iop, the driving control signal drc, the rising data rdata, the falling data fdata, and the global input / output line GIO. It is composed of an output drive means 30 for receiving the input data to generate the output data (odata).

At this time, the latch output instruction signal lto is an enable signal for sequentially outputting data latched to the latch means 20. When the latch output instruction signal lto is enabled, the rising data rdata is enabled. ) And the polling data fdata are sequentially generated. The rising clock rclk and the falling clock fclk are clocks having a high level potential at the rising edge time and the falling edge time of the DLL clock, respectively. In addition, the test signal tst is a signal generated in a test step to indicate a data output test mode of the data output circuit, and the method of generating the test signal tst is not limited to any one. The input / output instruction signal iop is a signal indicating that the semiconductor memory device is in a data input operation or a data output operation according to its potential level. In addition, the driving control signal drc is a low enable signal, and is a signal for performing a data driving operation of the output driving means 30 when its potential is at a low level.

First, when the test signal tst is disabled, a plurality of data (for example, 16) are transferred from the plurality of memory banks to the global input / output line GIO and supplied to the data selecting means 10. do. Thereafter, the data selecting means 10 selects a portion (for example, four) of the plurality of data according to the control of the selection control signal scnt and transmits the selected data to the latch means 20. The latch means 20 latches each of the received data and sequentially outputs the latched data as the rising data rdata or the polling data fdata under the control of the latch output instruction signal lto. . When the input / output instruction signal iop instructs a data output operation, the output driving means 30 is the rising data rdata or the data synchronized with the rising clock rclk under the control of the driving control signal drc. The output data odata is generated by performing a driving operation of the polling data fdata synchronized with the polling clock clk.

However, when the test signal tst is enabled, the output driving means 30 receives the data transmitted from the global input / output line and performs the above driving operation. Accordingly, an operation time point of the output driving means 30 is determined by input timing of data transmitted from the global input / output line GIO, and accordingly, a time point at which the output data odata is generated and output through the data output pad is determined. Is determined. In this case, the data transferred from the global input / output line GIO is not limited to any of the data transferred from the plurality of memory banks to the global input / output line GIO, and the experimenter can selectively use the data to be tested. It turns out that

2 is a configuration diagram of a data output circuit of a semiconductor memory device according to another embodiment of the present invention, and illustrates a test mode for measuring timing of a selection control signal.

The configuration of the data output circuit shown in FIG. 2 is not different from the configuration of the data output circuit shown in FIG. However, the difference here is that the selection control signal scnt is input to the output driving means 30 instead of the data of the global input / output line GIO.

When the test signal tst is enabled, the output driving means 30 receives the selection control signal scnt and performs the above-described driving operation. Accordingly, an operation time point of the output driving means 30 is determined by the input timing of the selection control signal scnt. Accordingly, the time point at which the output data odata is generated and output through the data output pad is determined.

As described above, the data of the global input / output line GIO and the selection control signal scnt are output through the output data odata respectively output by the above-described two embodiments of the data output circuit of the semiconductor memory device of the present invention. ) Can be inferred. Therefore, if valid data is not outputted, the tester may perform such a test to determine whether there is an abnormal operation timing of the data of the global input / output line GIO or the selection control signal scnt. Thereafter, when the test mode ends, the test signal tst is disabled and the output data odata is generated by the rising data rdata and the polling data fdata.

3 is a block diagram showing the configuration of the output driving means shown in FIGS.

The output driving means 30 combines the driving control signal drc, the test signal tst, data of the global input / output line GIO, or the selection control signal scnt to drive the first to fourth drives. The rising data synchronized with the signal combination unit 310 generating the signals drv1 to drv4, the input / output instruction signal iop, the first and second driving signals drv1 and drv2, and the rising clock rclk. a pull-up unit 320 for performing a pull-up operation for generating the output data odata in response to an input of the polling data fdata synchronized with the rdata and the polling clock fclk; The input / output instruction signal iop, the third and fourth driving signals drv3 and drv4, the rising data rdata synchronized with the rising clock rclk, and the polling data synchronized with the polling clock fclk. for generating the output data (odata) in response to an input of (fdata) The output data odata is formed at the output node Nout common to the pull-up unit 320 and the pull-down unit 330. The pull-down unit 330 performs a pull-down operation.

The first driving signal drv1, the second driving signal drv2, the third driving signal drv3, and the fourth driving signal drv4 have opposite phases, respectively. In the normal mode, the potential level of the first to fourth driving signals drv1 to drv4 is determined by the potential level of the driving control signal drc. However, in the test mode, the potential of the first to fourth driving signals drv1 to drv4 is determined by the potential level of the data of the global input / output line GIO or the selection control signal scnt.

The pull-up unit 320 and the pull-down unit 330 may be configured to output the first and second driving signals drv1 and drv2 or the third and fourth driving signals when the input / output instruction signal iop indicates a data output operation. Activated by (drv3, drv4) to drive the rising data (rdata) and the polling data (fdata). By the driving operation of the pull-up unit 320 and the pull-down unit 330, the output data odata has a potential of an external power supply voltage VDD or ground voltage VSS level.

4 is a circuit diagram showing the detailed configuration of the signal combination unit shown in FIG.

As illustrated, the signal combination unit 310 corresponds to an input of the driving control signal drc, the test signal tst, the data of the global input / output line GIO, or the selection control signal scnt. Data of the first combination unit 312 and the driving control signal drc, the test signal tst, and the global input / output line GIO generating the first and second driving signals drv1 and drv2, or the The second combination unit 314 generates the third and fourth driving signals drv3 and drv4 in response to the input of the selection control signal scnt.

Here, the first combination unit 312 may include the first inverter IV1 receiving the driving control signal drc, the data of the test signal tst and the global input / output line GIO, or the selection control signal ( a first NAND gate ND1 receiving the scnt, an output signal of the first inverter IV1, and an output signal of the first NAND gate ND1, and outputting the first driving signal drv1. A second inverter IV2 receives the NAND gate ND2 and the first driving signal drv1 and outputs the second driving signal drv2.

The second combination unit 314 receives a third inverter IV3 that receives the driving control signal drc, a fourth inverter that receives data of the global input / output line GIO, or the selection control signal scnt. IV4, a third NAND gate ND3 receiving the test signal tst and an output signal of the fourth inverter IV4, an output signal of the third inverter IV3, and the third NAND gate ND3. A fifth NAND gate ND4 for outputting the third driving signal drv3 and a third driving signal drv3 for outputting the fourth driving signal drv4 It consists of inverter IV5.

When the test signal tst is disabled, a high level signal is output from the first NAND gate ND1 of the first combination unit 312, so that the first driving signal drv1 is the driving control signal drc. Has a potential equal to), and the second driving signal drv2 has a potential of the inversion level of the driving control signal drc. In this case, since the output signal of the third NAND gate ND3 of the second combining unit 314 is also at a high level, the third driving signal drv3 is the first driving signal drv1 and the fourth driving. The signal drv4 has the same level of electric potential as the second driving signal drv2, respectively. Since the driving control signal drc is a low enable signal, the first and third driving signals drv1 and drv3 are at a low level, and the second and fourth driving signals drv2 and drv4 are at a high level. Operation of the pull-up unit 320 and the pull-down unit 330 is started.

However, when the test signal tst is enabled, the first to fourth driving signals drv1 to drv4 output from the first and second combination units 312 and 314 may be connected to the global input / output line GIO. Generated by data or the selection control signal scnt, respectively. That is, when the driving control signal drc is enabled, when the data of the global input / output line GIO or the potential of the selection control signal scnt is at a low level, the first and fourth driving signals drv1 and drv4 may be The level is low and the second and third driving signals drv2 and drv3 are at a high level. On the contrary, when the data of the global input / output line GIO or the potential of the selection control signal scnt is at a high level, the second and third driving signals drv2 and drv3 are at a low level, and the first and fourth driving are performed. The signals drv1 and drv4 are at a high level.

As described above, in the data output circuit of the present invention, the output driving means 30 generates the output data odata according to a timing at which the data of the global input / output line GIO or the selection control signal scnt is transmitted. Accordingly, it is possible to determine whether there is an operation timing error of the data of the global input / output line GIO or the selection control signal scnt.

5 is a circuit diagram showing the detailed configuration of the pull-up unit shown in FIG.

The pull-up unit 320 transfers the rising data rdata or the falling data fdata to the first node N1 in response to an input of the rising clock rclk and the falling clock fclk. The first control unit 324 for controlling the potential of the first node N1 in response to the input of the data supply unit 322, the input / output instruction signal iop, and the first and second driving signals drv1 and drv2. In response to a signal transmitted from the first driver 326 and the first driver 326 for latching and driving the signal applied to the first node N1, the output node of the external power supply VDD ( Nout) is configured as a first switching unit 328 for controlling the supply.

Here, the first data supply unit 322 is configured to transfer the rising data rdata to the first node N1 and the falling clock PG1 under the control of the rising clock rclk. The second passgate PG2 transfers the polling data fdata to the first node N1 under the control of fclk.

In addition, the first control unit 324 may include a first transistor TR1 to which the input / output instruction signal iop is input to a gate terminal and the external supply power supply VDD is applied to a source terminal, and the first driving signal to a gate terminal. The second driving signal drv2 is connected to the second transistor TR2 and the gate terminal of which drv1 is input, a source terminal is connected to the drain terminal of the first transistor TR1, and a drain terminal is connected to the second node N2. ) Is input and the drain terminal is connected to the second node (N2), the third transistor (TR3), the input and output instruction signal (iop) is input to the gate terminal, the drain terminal and the source terminal of the third transistor (TR3) A fourth transistor TR4 connected to the source terminal of which is grounded, a fifth transistor of which the first driving signal drv1 is input to a gate terminal thereof, a drain terminal thereof is connected to the second node N2, and a source terminal thereof is grounded. TR5), and a gate terminal is connected to the second node N2 The second driving signal drv2 is input to the sixth transistor TR6 and the gate terminal connected to the drain terminal, the drain terminal is connected to the first node N1, and the source terminal is grounded, and the external power supply VDD is connected to the source terminal. ) Is applied and the drain terminal includes a seventh transistor TR7 connected to the first node N1.

In addition, the first driver 326 may include a sixth inverter IV6 receiving a signal applied to the first node N1 and a seventh inverter IV7 forming a latch structure with the sixth inverter IV6. And eighth and ninth inverters IV8 and IV9 for non-inverting driving the output signal of the sixth inverter IV6.

Finally, the first switching unit 328 receives a signal output from the first driver 326 at a gate terminal, the external supply power VDD is applied to a source terminal, and a source terminal of the output node Nout. It consists of an eighth transistor TR8 connected to.

The first data supply unit 322 outputs the rising data rdata when the potential of the rising clock rclk is high level, and outputs the falling data fdata when the potential of the falling clock fclk is high level. And outputs the result to the first node N1.

At this time, when the potential of the input / output instruction signal iop becomes high level when the semiconductor memory device performs data output operation, the first transistor TR1 of the first controller 324 is turned off. And the fourth transistor TR4 is turned on. In this case, when the potential of the first driving signal drv1 transmitted from the signal combination unit 310 is at a low level and the potential of the second driving signal drv2 is at a high level, the second and third transistors TR2 may be used. , TR3) is turned on. Accordingly, the potential of the second node N2 is at a low level, and the sixth transistor TR6 is turned off. Since the seventh transistor TR7 is also turned off, the potential level of the first node N1 is formed by data output from the first data supply unit 322.

Thereafter, the signal applied to the first node N1 is inverted and driven through the first driver 326 to be transmitted to the first switching unit 328, and the first switching unit 328 is configured to transmit the signal. The pull-up operation for the output node Nout is performed according to the potential.

However, when the potential of the first driving signal drv1 is high and the potential of the second driving signal drv2 is low, the fifth transistor TR5 of the first control unit 324 is turned on and the Since the potential of the second node N2 is at a low level, the sixth transistor TR6 is turned off. In this case, since the seventh transistor TR7 is turned on, the potential of the first node N1 becomes a high level regardless of the signal transmitted from the first data supply unit 322.

The high level potential of the first node N1 is then inverted driven by the first driver 326 and transferred to the first switching unit 328 as a low level potential. The eighth transistor TR8 of the first switching unit 328 is turned on as a low level signal is input to transfer the external supply power VDD to the output node Nout. In this case, the data of the global input / output line GIO or the potential of the selection control signal scnt is at a low level. In this case, the pull-up unit 320 performs a pull-up operation on the output node Nout. .

6 is a circuit diagram showing a detailed configuration of the pull-down section shown in FIG.

The pull-down unit 330 transfers the rising data rdata or the falling data fdata to a third node N3 in response to an input of the rising clock rclk and the falling clock fclk. The second control unit 334 for controlling the potential of the third node N3 in response to the input of the data supply unit 332, the input / output instruction signal iop, and the third and fourth driving signals drv3 and drv4. And a second switch for grounding the output node Nout in response to a signal transmitted from the second driver 336 and the second driver 336 that latches and drives the signal applied to the third node N3. Section 338.

Here, the second data supply unit 332 transmits the third pass gate PG3 and the polling clock to transfer the rising data rdata to the third node N3 under the control of the rising clock rclk. The fourth passgate PG4 transfers the polling data fdata to the third node N3 under the control of fclk.

In addition, the second control unit 334 receives the output signal of the tenth inverter IV10 and the gate terminal of the tenth inverter IV10 that receives the input / output instruction signal iop, and the external supply power source (s) to the source terminal. A third driving signal drv3 is input to a ninth transistor TR9 to which VDD is applied, a gate terminal thereof is connected to a drain terminal of the ninth transistor TR9, and a drain terminal thereof is a fourth node N4. An eleventh transistor TR11 connected to the first transistor TR10 connected to the fourth driving signal drv4 and a drain terminal connected to the fourth node N4, and a tenth transistor connected to the fourth node N4. The output signal of the inverter IV10 is input, the drain terminal is connected to the source terminal of the eleventh transistor TR11, and the source terminal is grounded, and the fourth driving signal drv4 is input to the gate terminal. And the external power supply (VDD) A thirteenth transistor TR13 having a drain terminal connected to the fourth node N4, a gate terminal connected to the fourth node N4, and an external supply power supply VDD applied to a source terminal; The third driving signal drv3 is input to the fourteenth transistor TR14 and the gate terminal of which the terminal is connected to the third node N3, the drain terminal is connected to the third node N3, and the source terminal is grounded. And a fifteenth transistor TR15.

The second driver 336 may include an eleventh inverter IV11 receiving a signal applied to the third node N3, a twelfth inverter IV12 forming a latch structure with the eleventh inverter IV11, The thirteenth and fourteenth inverters IV13 and IV14 for non-inverting driving the output signal of the eleventh inverter IV11 are configured.

Finally, the second switching unit 338 is a sixteenth transistor TR16 having a signal input from the second driver 336 at a gate end thereof, a drain end thereof connected to the output node Nout, and a source end thereof grounded. It consists of

The second data supply unit 332 outputs the rising data rdata when the potential of the rising clock rclk is high level, and outputs the falling data fdata when the potential of the falling clock fclk is high level. Outputs the data to the third node N3.

In this case, when the semiconductor memory device performs a data output operation and the potential of the input / output instruction signal iop becomes a high level and the output signal of the tenth inverter IV10 becomes a low level, the second controller 334 ), The ninth transistor TR9 is turned on and the twelfth transistor TR12 is turned off. At this time, when the potential of the third driving signal drv3 transmitted from the signal combination unit 310 is at a low level and the potential of the fourth driving signal drv4 is at a high level, the tenth and eleventh transistors are provided. (TR10, TR11) are turned on. As a result, the potential of the fourth node N4 becomes high and the fourteenth transistor TR14 is turned off. Since the fifteenth transistor TR15 is also turned off, the potential level of the third node N3 is formed by data output from the first data supply unit 322.

Thereafter, the signal applied to the third node N3 is inverted and driven through the second driver 336 to be transmitted to the second switching unit 338, and the second switching unit 338 is configured to transmit the signal. Optionally, the output node Nout is pulled down depending on the potential.

However, when the potential of the third driving signal drv3 is high and the potential of the fourth driving signal drv4 is low, the thirteenth transistor TR13 of the second control unit 334 is turned on and the Since the potential of the four node N4 is at a high level, the fourteenth transistor TR14 is turned off. At this time, since the fifteenth transistor TR15 is turned on, the potential of the third node N3 is at a low level regardless of the signal transmitted from the second data supply unit 332.

The high level potential of the third node N3 is then inverted by the second driver 336 and transferred to the second switching unit 338 as a high level potential. The sixteenth transistor TR16 of the second switching unit 338 is turned on as a high level signal is input to sink the potential of the output node Nout to the ground level. In this case, when the data of the global input / output line GIO or the potential of the selection control signal scnt is at a high level, the pull-down unit 330 performs a pull-down operation on the output node Nout. .

As described above, the data output circuit of the semiconductor memory device according to the present invention performs a pull-up or pull-down operation according to the potential level of the data of the global input / output line GIO or the selection control signal scnt in the test mode. The output data (odata) is generated. In the test mode, the influence of the rising data rdata and the polling data fdata input from the latch means 20 is reduced, and the output data odata is selected from the data of the global input / output line GIO or the selection. It can be assumed that it is generated by the control signal scnt. The experimenter inputs the data of the global input / output line GIO or the selection control signal scnt to the output driving means 30 to determine whether the operation timing of the data of the global input / output line GIO is abnormal and the selection control signal. It is possible to measure whether the operation timing of scnt is abnormal and to determine the timing margin of the two signals. Therefore, it is possible to improve the test efficiency for implementing a more stable data output operation of the semiconductor memory device.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The data output circuit and the method of the semiconductor memory device of the present invention described above are selected for selecting some of the data of the global I / O line and the timing at which data is transferred from the global I / O line when valid data is not output at the time of data output. By measuring the enable timing of the control signal, it is possible to determine the cause of the malfunction, thereby improving the efficiency of the data output test.

Claims (35)

Data selecting means for selecting some of a plurality of data transferred from the global input / output line according to the control of the selection control signal; And When the test signal is enabled, a clock, an input / output instruction signal, a drive control signal, data output from the data selection means and latched, sequentially transmitted, data of the global input / output line, or the selection control signal are generated to generate output data. Output drive means; And a data output circuit of the semiconductor memory device. The method of claim 1, When the test signal is enabled, the output driving means generates the output data corresponding to the data of the global input / output line or the selection control signal according to the control of the input / output instruction signal and the driving control signal, and the test signal is When disabled, the semiconductor memory device generates the output data by driving data output from the data selection means and sequentially transmitted after being latched under the control of the input / output instruction signal, the driving control signal, and the clock. Data output circuit. The method of claim 1, And wherein the output time is determined by data of the global input / output line or the selection control signal in a test mode. The method of claim 2, The output drive means, A signal combination unit configured to generate first to fourth driving signals by combining the driving control signal, the test signal, the data of the global input / output line, or the selection control signal; A pull-up operation is performed to generate the output data in response to an input of data output from the input / output instruction signal, the first and second driving signals, and the data selection means and sequentially transmitted after being latched. Pull up unit to; And A pull-down operation for generating the output data in response to an input of data output from the input / output instruction signal, the third and fourth driving signals, and the data selection means and sequentially transmitted after being latched and synchronized with the clock; A pull-down unit; And the output data is formed at an output node common to the pull-up unit and the pull-down unit. The method of claim 4, wherein The signal combination unit, A first combination unit configured to generate the first and second driving signals in response to input of the driving control signal, the test signal, the data of the global input / output line, or the selection control signal; And A second combination unit configured to generate the third and fourth driving signals in response to input of the driving control signal, the test signal, the data of the global input / output line, or the selection control signal; And a data output circuit of the semiconductor memory device. The method of claim 5, The first combination portion, A first inverter receiving the driving control signal; A first NAND gate receiving the test signal and the data of the global input / output line or the selection control signal; A second NAND gate receiving the output signal of the first inverter and the output signal of the first NAND gate and outputting the first driving signal; And A second inverter receiving the first driving signal and outputting the second driving signal; And a data output circuit of the semiconductor memory device. The method of claim 5, The second combination portion, A first inverter receiving the driving control signal; A second inverter configured to receive data of the global input / output line or the selection control signal; A first NAND gate receiving the test signal and the output signal of the second inverter; A second NAND gate receiving the output signal of the first inverter and the output signal of the first NAND gate and outputting the third driving signal; And A third inverter configured to receive the third driving signal and output the fourth driving signal; And a data output circuit of the semiconductor memory device. The method of claim 4, wherein The pull-up unit, A data supply unit configured to transfer data synchronized with the clock to a first node in response to an input of the clock; A control unit controlling a potential of the first node in response to input of the input / output instruction signal and the first and second driving signals; A driver configured to latch and drive a signal applied to the first node; And A switching unit controlling a supply of an external supply power to the output node in response to a signal transmitted from the driving unit; And a data output circuit of the semiconductor memory device. The method of claim 8, And the data supply unit includes a pass gate which transmits the data output from the data selection means to the first node after being latched under the control of the clock. The method of claim 8, The control unit, A first transistor to which the input / output instruction signal is input to a gate terminal and the external supply power is applied to a source terminal; A second transistor having a first driving signal input to a gate terminal, a source terminal connected to a drain terminal of the first transistor, and a drain terminal connected to a second node; A third transistor having a second driving signal input to a gate terminal thereof and a drain terminal thereof connected to the second node; A fourth transistor in which the input / output instruction signal is input to a gate terminal, a drain terminal is connected to a source terminal of the third transistor, and a source terminal is grounded; A fifth transistor in which the first driving signal is input to a gate terminal, a drain terminal is connected to the second node, and a source terminal is grounded; A sixth transistor having a gate terminal connected to the second node, a drain terminal connected to the first node, and a source terminal grounded; And A seventh transistor to which the second driving signal is input at a gate end, the external supply power is applied to a source end, and a drain end thereof is connected to the first node; And a data output circuit of the semiconductor memory device. The method of claim 8, The driving unit, A first inverter receiving a signal applied to the first node; And A second inverter forming a latch structure with the first inverter; And a data output circuit of the semiconductor memory device. The method of claim 8, And the switching unit includes a transistor to which a signal output from the driving unit is input at a gate terminal, the external supply power is applied to a source terminal, and a source terminal is connected to the output node. The method of claim 4, wherein The pull-down unit, A data supply unit configured to transfer data synchronized with the clock to a first node in response to an input of the clock; A control unit controlling a potential of the first node in response to input of the input / output instruction signal and the third and fourth driving signals; A driver configured to latch and drive a signal applied to the first node; And A switching unit which grounds the output node in response to a signal transmitted from the driving unit; And a data output circuit of the semiconductor memory device. The method of claim 13, And the data supply unit includes a pass gate which transmits the data output from the data selection means to the first node after being latched under the control of the clock. The method of claim 13, The control unit, An inverter receiving the input / output instruction signal; A first transistor to which an output signal of the inverter is input at a gate end and the external supply power is applied to a source end; A second transistor having a third driving signal input to a gate terminal, a source terminal connected to a drain terminal of the first transistor, and a drain terminal connected to a second node; A third transistor having the fourth driving signal input to a gate terminal thereof and a drain terminal thereof connected to the second node; A fourth transistor in which an output signal of the inverter is input to a gate terminal, a drain terminal is connected to a source terminal of the third transistor, and a source terminal is grounded; A fifth transistor in which the fourth driving signal is input to a gate terminal, an external supply power is applied to a source terminal, and a drain terminal is connected to the second node; A sixth transistor having a gate terminal connected to the second node, the external supply power applied to a source terminal, and a drain terminal connected to the first node; And A seventh transistor having a third driving signal input to a gate terminal, a drain terminal connected to the first node, and a source terminal grounded; And a data output circuit of the semiconductor memory device. The method of claim 13, The driving unit, A first inverter receiving a signal applied to the first node; And A second inverter forming a latch structure with the first inverter; And a data output circuit of the semiconductor memory device. The method of claim 13, And the switching part includes a transistor having a signal input from the driving part at a gate end thereof, a drain end connected to the output node, and a source end being grounded. The method of claim 1, And a latch means for latching the data output from the data selection means and sequentially outputting the latched data to the output driving means under the control of a latch output instruction signal. Data output circuit. The method of claim 18, And the latch output instruction signal is a signal enabled to sequentially output data latched to the latch means. The method of claim 19, And the clock is a rising clock having a high level potential at the rising edge time of the DLL clock or a falling clock having a high level potential at the falling edge time of the DLL clock. The method of claim 20, And the data output from the latching means is rising data synchronized with the rising clock or falling data synchronized with the falling clock. The method of claim 1, And the test signal is a signal generated in a test step to indicate a data output test mode of the data output circuit. The method of claim 1, And the input / output instruction signal is a signal indicating that the semiconductor memory device is in a data input operation or a data output operation according to its potential level. The method of claim 1, And the drive control signal is a signal for causing a data drive operation of the output drive means to be performed when its potential is at a low level. a) selecting some of the plurality of data of the global input / output line according to the control of the selection control signal; And b) When the test signal is enabled, a clock, an input / output instruction signal, a drive control signal, data output in the step a) and latched, and sequentially transmitted, data of the global input / output line, or the selection control signal are input and output data. Generating a; A data output method of a semiconductor memory device comprising a. The method of claim 25, In the step b), when the test signal is enabled, the output signal corresponding to the data of the global input / output line or the selection control signal is generated according to the control of the input / output instruction signal and the driving control signal. And disabling the data outputted in the step a) and the data sequentially transmitted after being latched under the control of the clock to generate the output data. The method of claim 25, The output data is a data output method of a semiconductor memory device, characterized in that the output time is determined by the data of the global input and output lines or the selection control signal. The method of claim 26, B), b-1) generating first to fourth driving signals by combining the driving control signal, the test signal and the data of the global input / output line or the selection control signal; b-2) for generating the output data in response to an input of the input / output instruction signal, the first and second driving signals, the data output in the step a) and latched, and then sequentially transmitted and synchronized with the clock; Performing a pull-up operation; And b-3) for generating the output data in response to the input of the input / output instruction signal, the first and second driving signals, the data output in the step a) and latched, and then sequentially transmitted and synchronized with the clock. Performing a pull-down operation; A data output method of a semiconductor memory device comprising a. The method of claim 28, Step b-2), b-2-) transferring data output in the step a) and latched and delivered to the first node according to the potential level of the clock; b-2-b) controlling the potential of the first node in response to the input of the input / output instruction signal and the first and second driving signals; b-2-) latching and driving a signal applied to the first node; And b-2- d) controlling the supply of the external power supply to the output node in response to the signal output in step b-2- c); A data output method of a semiconductor memory device comprising a. The method of claim 28, Step b-3), b-3-) delivering data to the first node which is output in the step a) and latched according to the potential level of the clock; b-3-b) controlling the potential of the first node in response to the input of the input / output instruction signal and the third and fourth driving signals; b-3-c) latching and driving a signal applied to the first node; And b-3- d) grounding the output node in response to the signal output in step b-3- c); A data output method of a semiconductor memory device comprising a. The method of claim 25, And the clock is a rising clock having a high level potential at the rising edge time of the DLL clock or a falling clock having a high level potential at the falling edge time of the DLL clock. The method of claim 31, wherein The data output method of the semiconductor memory device, characterized in that the data output in step a) and latched, and then sequentially transferred to step b) are rising data synchronized with the rising clock or falling data synchronized with the falling clock. . The method of claim 25, And the test signal is a signal generated in a test step to indicate a data output test mode. The method of claim 25, And the input / output instruction signal is a signal indicating that the semiconductor memory device is in a data input operation or a data output operation according to its potential level. The method of claim 25, And the drive control signal is a signal that is enabled when its potential is at a low level.

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