KR100699816B1 - Semiconductor device for safe at ??? - Google Patents

Abstract

Semiconductor devices safe for electrical over stress (EOS) are disclosed. Data input / output pads, between the data input / output pads and the supply voltage and between the data input / output pads and the ground power supply to protect the internal circuits from electrostatic discharge (hereinafter referred to as ESD). According to an exemplary embodiment of the present disclosure, a semiconductor device including an ESD protection diode connected between the wires is connected to the metal line of the ESD protection diode by a predetermined width or more and inputted through the data input / output line. Electrical Over Stress, hereinafter referred to as EOS), the metal line connected to the ESD protection diode is prevented from being destroyed by the surge, and the width of the metal line connected to the pad and the ESD protection diode connected to the outside is prevented. By widening it to more than 20 μm, EOS resistance to EOS surges can be enhanced, thus destroying semiconductor devices from unwanted EOS surges. It can be minimized.

Description

Semiconductor device for safe at EOS {Semiconductor device for safe at EOS}

1 and 2 are diagrams schematically showing a conventional wiring form connected to a pad.

3 and 4 are views showing embodiments of the metal wiring according to the present invention.

5 is a diagram illustrating metal wiring between a data IN / OUT pad, a supply power VDD, and a ground power VSS pad and an internal circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and, more particularly, to semiconductor devices that are safe against E.S. (hereinafter, referred to as EOS).

EOS refers to any unintended type of pulse that exceeds the product's ratings, and refers to ESD, surge, latch-up, and over voltage / current. That is, a semiconductor device manufacturing company evaluates whether a semiconductor device is defective through EOS evaluation and distributes it to the market. However, to date, EOS evaluation of semiconductor devices is mostly poor evaluation of E.D. (Electro static discharge) and latch-up, and EOS for surge and transient voltage / current is evaluated. It is not true.

As a result of examining field defects of semiconductor devices, the EOS defect share is 30%, and the proportion of defects is very high, and ESD defects are only 7%. In other words, it can be seen that the ratio of failure due to surge and transient voltage / current, which has not been considered in the past, is higher than the failure due to ESD among EOS failures. Hereinafter, for convenience of description, EDS failure of EOS failure is EDS failure, and failure due to surge and transient voltage / current is EOS surge failure.

As such, the reason why ESD defects account for a small portion of EOS defects in semiconductor devices is that the defect improvement due to ESD has been steadily made. However, defects due to impulsive surges classified as EOS surges for semiconductor devices are not considered. Here, impulsive surge refers to an unintentional pulse of a rapid increase and then gradually decrease.In the international standard of surges of set and high power devices, a pulse having a rise time of 0.1us ~ 10us is generally defined as an impulsive surge. have. The most frequent occurrence of defects in semiconductor devices caused by EOS surges is melting of the metal lines connected to the pads.

1 and 2 are diagrams schematically showing a conventional wiring form connected to a pad. Here, FIG. 1 shows a metal wiring form in the case of a customer cell, and FIG. 2 shows a metal wiring form in the case of a standard I / O cell. 1 and 2, reference numerals 16, 18, 34, and 36 denote ESD protection diodes for chip protection by ESD. Reference numerals 10 and 30 represent metal lines connected to VDD, and 14 and 32 represent metal lines connected to Vss, respectively. Reference numerals 12 and 38 denote pads to be connected to the outside, and 20a to 20d and 40a to 40e denote metal lines to be connected to the ESD protection diodes, respectively.

1 and 2, the ESD protection diodes 16, 18, 34, and 36 may include pads 12 and 38 and VDD lines 10 and 30 to protect internal circuits by static electricity input from the outside. And between the pads 12 and 38 and the Vss lines 14 and 32 by metal lines 20a to 20d and 40a to 40e, respectively. At this time, the metal lines 20a to 20d and 40a to 40e connected to the ESD protection diodes 16, 18, 34, and 36 are very narrow, such as 5 μm. Therefore, when the EOS surge is input through the pads 12 and 38 from the outside, the EOS lines melt and cannot withstand the metal lines 20a to 20d and 40a to 40e.

Therefore, in order to improve the defect of the semiconductor device, EOS evaluation by surge and transient voltage / current should be performed before shipping the semiconductor device on the market, and the improvement of the characteristics of the semiconductor device is enhanced so that EOS resistance by surge and transient voltage / current is stronger. Required.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device that is safe for EOS by enhancing EOS resistance due to surge and transient voltage / current.

To accomplish this task, between the data input / output pad and the power supply voltage and between the data input / output pad and the power supply voltage to protect the data input / output pad, the internal circuits from electrostatic discharge (hereinafter referred to as ESD). The semiconductor device according to the present invention includes an ESD protection diode connected between an output pad and a ground power supply, respectively, and the metal line of the ESD protection diode is wired to a predetermined width or more to be input through the data input / output line. The electrical over stress (hereinafter, referred to as EOS) surge prevents the metal line connected to the ESD protection diode from being destroyed by the surge.

Hereinafter, with reference to the accompanying drawings a semiconductor device safe for EOS according to the present invention will be described as follows.

Generally, there are many set-level product immunity testing methods, but semiconductor chip-level immunity testing methods include only ESD, EMI, and latch-up levels. Semiconductor manufacturers ship products that pass all of these ESD, EMI, and latch-up tests as good products. However, the EOS impact test is not performed at the semiconductor chip level. Therefore, even if the product passes all ESD, EMI, and latch-up tests, defects caused by the EOS impact are not reduced. Here, the form of the defect caused by the EOS impact is the melting of metal lines connected to the outside via pads, breakage of contacts and PN junctions, breakage of epi-bias junctions, and F.T. Defects in the form of breakage of the (FET) junction, etc., occur. As mentioned above, the melting of the metal line is most frequently occurred, as described above, of 60% or more.

3 and 4 are views showing embodiments of the metal wiring according to the present invention. Here, FIG. 3 shows the metal interconnection form of the customer cell, and FIG. 4 shows the metal interconnection form of the standard I / O cell. 3 and 4, reference numerals 104, 106, 134, and 136 denote ESD protection diodes for chip protection by ESD. Reference numerals 100 and 130 denote metal lines connected to VDD, and 108 and 132 denote metal lines connected to Vss, respectively. Reference numerals 102 and 138 denote pads connected to the outside, and 110a to 110d and 140a to 140e denote metal lines connected to the ESD protection diodes, respectively.

3 and 4, ESD protection diodes 16, 18, 34, 36 are disposed between pads 102 and 138 and VDD lines 100 and 130 to protect internal circuits by static electricity input from the outside. The pads 102 and 138 and the Vss lines 108 and 132 are connected by metal lines 110a to 110d and 140a to 140d, respectively. At this time, the metal lines 110a to 110d and 140a to 140d connected to the ESD protection diodes 104, 106, 134 and 136 have their widths wider than a predetermined width so that EOS surges may be input from the outside through the pads 12 and 38. Metal lines (110a ~ 110d, 140a ~ 140d) to withstand. In this case, the widths of the metal lines 110a to 110d and 140a to 140d may be determined according to the EOS surge voltage.

In general, the frequency of occurrence of the EOS surge voltage of 15 V or less in the semiconductor device is high, and therefore, a lot of defects are caused by the EOS surge voltage of 15 V or less. Therefore, the EOS defect improvement of the semiconductor element with respect to EOS surge voltage of 15V or less is essential. As such, the metal lines 110a to 110d and 140a to 140d may have a width of about 20 μm in order to withstand the EOS surge voltage of 15V or less. In some cases, an EOS surge voltage of 15 V to 20 V may be applied to the semiconductor element. As such, in order for the metal lines 110a to 110d and 140a to 140d to withstand the EOS surge voltage of 15V to 20V, the width of the metal lines 110a to 110d and 140a to 140d may be about 30 μm. In addition, EOS surge voltage of 20V or more is hardly applied in the semiconductor device. Therefore, the defect by EOS surge voltage of 20V or more hardly occurs.

As a result, the EOS surge voltage for the semiconductor device is 15 V or less or 20 V or less, and in order to improve the defect of the semiconductor device caused by the EOS surge voltage, it is preferable to set the EOS metal lines 110a to 110d and 140a to 140um to 20um or 30um. desirable.

5 is a diagram illustrating metal wiring between a data IN / OUT pad, a supply power VDD, and a ground power VSS pad and an internal circuit. In FIG. 5, reference numeral 170 denotes a data input (IN) pad, 180 denotes a data output (OUT) pad, 160 denotes a VDD pad, and 190 denotes a VSS pad. Reference numerals 172 to 178 denote ESD protection diodes, respectively, and 200 denote internal logic circuits.

Referring to FIG. 5, the metal lines connected to the pads 170 and 180 for inputting / outputting data from outside are widened to 20 μm or more, and the metal lines connected to the internal logic circuits are wired about 5 μm. Since the metal line directly affected by the EOS surge voltage is the metal line connected to the data input / output pads 170 and 180, the EOS is made by widening the width of the metal line connected to the data input / output pads 170 and 180. The defect of a semiconductor element by a surge can be prevented. On the other hand, since the EOS surge voltage is not affected by the internal logic circuit 200, the metal line width of the internal logic circuit 200 may be narrowed to about 5 μm.                     

As described above, the semiconductor device according to the present invention can minimize the destruction of the semiconductor device from unwanted EOS surges by widening the width of the pad connected to the outside and the metal line connected to the ESD protection diode to 20 μm or more. .

As described above, the semiconductor device according to the present invention can increase the EOS resistance to EOS surge by widening the width of the pad connected to the outside and the metal line connected to the ESD protection diode to 20 μm or more, and thus unwanted. The destruction of the semiconductor device from the EOS surge can be minimized.

Claims (3)

Data input / output pads, between the data input / output pads and the supply voltage and between the data input / output pads and the ground power supply to protect the internal circuits from electrostatic discharge (hereinafter referred to as ESD). A semiconductor device having an ESD protection diode connected to each other by metal lines therebetween, By wiring the metal line of the ESD protection diode to a predetermined width or more, the ESD protection diode is prevented by an electrical over stress (hereinafter, referred to as EOS) surge input through the data input / output pad. An EOS-safe semiconductor device, characterized by preventing metal lines from being destroyed. The device of claim 1, wherein the width of the metal line of the ESD protection diode is 20 μm or more to protect the metal line of the ESD protection diode against an EOS surge voltage of 15 V or less. The device of claim 2, wherein the width of the metal line of the ESD protection diode is 30 μm or more to protect the metal line of the ESD protection diode against an EOS surge voltage of 20 V or less.

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