KR100659712B1 - Light emitting display and driving method thereof - Google Patents

Abstract

A light emitting display device and a driving method thereof are provided to normally display an image even if a display panel is turned by 180 degrees. A light emitting display device includes plural scan lines(S1~S6) transmitting selection signals, respectively; a bi-directional shift register(210) outputting plural shift signals in order with shifting a first signal in a first direction correspondingly to a first period in response to a first control signal and outputting plural shift signals in order with shifting the first signal in a second direction correspondingly to the first period in response to a second control signal; a first driving unit generating the selection signals of the odd scan lines by carrying out a logic operation for two of plural shift signals and a first sub clock signal(SCLK1); and a second driving unit generating the selection signals of the even scan lines by carrying out a logic operation for two signals and a second sub clock signal(SCLK2) shifted from the first sub clock signal as long as a second period.

Description

LIGHT EMITTING DISPLAY AND DRIVING METHOD THEREOF

1 illustrates an organic light emitting diode display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of a pixel circuit according to an exemplary embodiment of the present invention.

3 is a view illustrating the scan driver of FIG. 1.

4 is a diagram illustrating a scan driver including a plurality of bidirectional controllers according to an exemplary embodiment of the present invention.

5 is a diagram illustrating in detail a plurality of bidirectional control units according to a first embodiment of the present invention.

6 and 7 illustrate a signal output according to an input signal according to the first embodiment of the present invention, respectively, in the forward and reverse directions.

8 is a view showing a scan driver according to a second embodiment of the present invention.

The present invention relates to a light emitting display device and a driving method thereof.

When the upper and lower sides of the screen of the display panel are rotated by 180 ° in the light emitting display device, the light emitting display device may include a bidirectional shift register configured to bidirectionally apply a selection signal applied to the scan line of the scan driver. When the selection signal is sequentially applied from the top to the bottom of the display panel (hereinafter referred to as 'forward scanning') and when the selection signal is sequentially applied from the bottom to the top by rotating 180 ° to the bottom (hereinafter 'backward') The selection signal must be changed.

An organic light emitting display device having a configuration to solve this problem includes at least one flip-flop for each row to scan a selection signal to a plurality of pixel circuits positioned in each row of the display panel. Accordingly, there is a problem in that flip-flops are required at least as many as the number of rows of the display panel and thus occupy a large space with many transistors.

Accordingly, the present invention provides a light emitting display device and a method of driving the light emitting display device which can be bidirectionally scanned and applied to each pixel circuit in a forward or reverse direction, occupy less space, and reduce the number of transistors. To provide.

A light emitting display device according to an aspect of the present invention sequentially shifts a plurality of shift signals while shifting a first signal in a first direction by a first period in response to a first control signal and a plurality of scan lines respectively transmitting a selection signal. And a bidirectional shift register configured to sequentially output the plurality of shift signals while shifting the first signal in a second direction by the first period in response to a second control signal, and two of the plurality of shift signals; A first driver configured to logically operate a first sub clock signal to generate the selection signal of an odd-numbered scan line among the plurality of scan lines, and a second period shifted with respect to the two signals and the first sub clock signal by a second period A second driver configured to logically perform two sub-clock signals to generate the selection signal of an even-numbered scan line among the plurality of scan lines It includes.

In accordance with another aspect of the present invention, a light emitting display device includes: a plurality of scan lines for transmitting a selection signal, first and second flip-flops for shifting and outputting an input signal by a first period, and the first control signal in response to a first control signal; A bidirectional control unit coupling an output terminal of a flip flop to an input terminal of the second flip flop, and connecting an output terminal of the second flip flop to an input terminal of the first flip flop in response to a second control signal; A first logic circuit that receives an output signal of a flip-flop and a first signal and outputs the selection signal to a corresponding first scan line among the plurality of scan lines, and an output signal of the first and second flip-flops and the first signal And a second logic circuit configured to receive a second signal shifted by a second period with respect to the signal, and output the selection signal to a second scan line adjacent to the first scan line.

According to another aspect of the present invention, a method of driving a light emitting display device transmits a plurality of selection signals to each of a plurality of scan lines, and transmits the first signal in a first direction or a second direction in response to a first or second control signal. Outputting a plurality of shift signals sequentially while shifting by a first period, and generating the selection signal of an odd-numbered scan line among the plurality of scan lines by performing a logic operation on two signals of the plurality of shift signals and a first sub clock signal And generating a selection signal of an even-numbered scan line among the plurality of scan lines by performing a logic operation on the second sub-clock signal shifted by a second period with respect to the two signals and the first sub-clock signal. .

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only the "directly connected" but also the "electrically connected" between other elements in between. In addition, when any part "includes" any component, this means that it may further include other components, except to exclude other components unless otherwise stated.

Hereinafter, an organic light emitting diode display and a scan driver, which is an embodiment of the display device, will be described in detail with reference to the accompanying drawings.

1 illustrates an organic light emitting diode display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the organic light emitting diode display according to the exemplary embodiment includes a display unit 100, a scan driver 200, a data driver 300, and a signal controller 400. In the organic light emitting diode display according to the exemplary embodiment of the present invention, bidirectional display is possible on the display unit 100 under the control of the signal controller 400. The scan driver 200 may output the selection signal to the display unit 100 in the forward and reverse directions according to the forward and reverse control signals CON_F and CON_R of the signal controller 400.

The display unit 100 includes a plurality of scan lines S1 -Sn, a plurality of data lines D1 -Dm, and a plurality of pixels 110. The plurality of scan lines S1 -Sn extend in a row direction and each transmit a selection signal, and the plurality of data lines D1 -Dm extend in a column direction and each transmit a data signal. Each pixel 110 is formed in a pixel region defined by a corresponding scan line among the plurality of scan lines S1 -Sn and a corresponding data line among the plurality of data lines D1 -Dm. In this case, the data signal is a current when the pixel 110 is a current write type pixel, and the data signal is a voltage when the pixel is a voltage write type pixel.

Meanwhile, in order to implement color display, each pixel uniquely displays one color of the primary colors or each pixel alternately displays the primary colors with time, so that a desired color is recognized by a spatial or temporal sum of these primary colors. Examples of primary colors include red (R), green (G), and blue (B). In this case, when colors are displayed by a time sum, R, G, and B colors are alternately displayed in one pixel to realize one color. In the case of displaying colors by spatial sum, one color is implemented by three pixels of the R pixel, the G pixel, and the B pixel, so that each pixel is referred to as a subpixel and three subpixels are referred to as one pixel. In addition, in the case of displaying colors in a spatial sum, R pixels, G pixels, and B pixels may be alternately arranged in a row direction or a column direction, or three pixels may be arranged at positions corresponding to three vertices of a triangle. .

The scan driver 200 is connected to the scan lines S1 -Sn of the display unit 100 to apply a selection signal, which is a combination of a gate on voltage and a gate off voltage, to the scan lines S1 -Sn. In this case, the scan driver 200 may apply the selection signal such that the plurality of selection signals respectively applied to the plurality of scan lines S1 -Sn have the gate-on voltage. When the selection signal has a gate-on voltage, the switching transistor connected to the corresponding scan line is turned on. The scan driver 200 determines the scan direction according to the forward control signal CON_F and the reverse control signal CON_R received from the signal controller 400. In the case of the forward scan according to the forward control signal CON_F, the selection signals are sequentially applied from the scan lines S1 to the scan lines Sn in the plurality of scan lines S1 -Sn. On the other hand, in the case of the reverse scanning according to the reverse control signal CON_R, the selection signals are sequentially applied from the scanning lines Sn to the scanning lines S1 in the plurality of scanning lines S1 -Sn.

The data driver 300 is connected to the data lines D1 -Dm of the display unit 100 to apply a data signal indicating a gray level to the data lines D1 -Dm. The data driver 300 converts input image data DR, DG, and DB having a gray level input from the signal controller 400 into a data signal in the form of voltage or current.

The signal controller 400 receives an input control signal for controlling the input image data DR, DG, DB and its display from an external graphic controller (not shown). The input control signal includes, for example, a horizontal sync signal Hsync, a vertical sync signal Vsync, and a main clock MCLK. The signal controller 400 transmits the input image data DR, DG, and DB to the data driver 300, generates a scan control signal CONT1, a forward control signal CON_F, and a reverse control signal CON_R to scan the input image data DR, DG, and DB. The controller 200 transmits the data control signal CONT2 to the data driver 300. The scan control signal CONT1 includes a scan start signal SP indicating a scan start, a clock signal CLK, and an inverted clock signal / CLK, and the data control signal CONT2 includes one pixel 110 in a row. ) And a horizontal synchronization start signal (STH) and a clock signal for instructing transfer of input image data.

On the other hand, when the signal control unit 400 transmits the input image data corresponding to one row to the data driver 300, the input image data (DR, DG, DB) may be transmitted for each color through three channels, Input image data DR, DG, and DB may be sequentially transmitted through one channel.

Next, the structure of the pixel circuit according to the embodiment of the present invention will be described with reference to FIG.

2 is an equivalent circuit diagram of a pixel circuit according to an exemplary embodiment of the present invention.

In FIG. 2, only the pixel circuit connected to the m-th data line Dm and the n-th scan line Sn is illustrated for convenience of description.

As shown in FIG. 2, the pixel circuit 110 according to an exemplary embodiment of the present invention includes transistors M1 and M2, a capacitor Cst, and an organic light emitting diode OLED. Such an organic light emitting device has a diode characteristic and is called an organic light emitting diode, and generally has a structure of an anode electrode, an organic thin film, and a cathode electrode.

The transistor M1 is a driving transistor for driving the organic light emitting diode OLED. The transistor M1 is connected between the power supply for supplying the voltage VDD and the organic light emitting diode OLED, and is connected to the organic light emitting diode by a voltage applied to the gate. Control the current flowing through the OLED. One electrode A of the capacitor Cst is connected to the gate of the transistor M1, and a power source for supplying the other electrode B of the capacitor Cst and the voltage VDD is connected to a source of the transistor M1. The anode of the organic light emitting diode OLED is connected to the drain of the transistor M1. The source of the transistor M2 is connected to the data line Dm, the drain is connected to one electrode A of the capacitor Cst, and the gate is connected to the scan line Sn. The transistor M2 transfers data from the data line Dm to one electrode A of the capacitor Cst in response to the selection signal from the scan line Sn. While turned on by the voltage difference between the gate and the source of the transistor M1, and while the voltage difference is maintained by the capacitor Cst, a current corresponding to the gate-source voltage is supplied to the organic EL element OLED, whereby the organic light emitting element OLED emits light. The OLED emits light in response to an input current. According to the exemplary embodiment of the present invention, the voltage VSS connected to the cathode of the organic light emitting diode OLED is a voltage lower than the voltage VDD, and a ground voltage or a negative voltage may be used.

The pixel circuit according to an embodiment of the present invention has been described so far as including two transistors and one capacitor, but the present invention is not limited thereto and may be applied to all pixel circuits operated by one or more selection signals.

Next, a scan driver 200 according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4.

3 is a diagram schematically illustrating the scan driver 200 of FIG. 1.

As shown in FIG. 3, the scan driver 200 includes a bidirectional shift register 210 and a plurality of NAND gates NAND1-NAND6 corresponding to the plurality of scan lines S1-S6, respectively. In the embodiment of the present invention, only six NAND gates NAND1-NAND6 corresponding to six rows (that is, scan lines S1-S6) are illustrated for convenience of description among the n NAND gates. In this case, the bidirectional shift register 210 has four output stages O1-O4 more than one half (3) of the number of rows 6.

The bidirectional shift register 210 receives a start signal SP, a forward control signal CON_F, a reverse control signal CON_R, a clock signal CLK, and an inverted clock signal / CLK. The bidirectional shift register 210 outputs the start signal SP to the plurality of output terminals O1 to O4 while shifting the start signal SP in the forward direction by a half clock CLK in response to the forward control signal CON_F. At this time, the bidirectional shift register 210 outputs while sequentially shifting the start signal SP by a half clock CLK in the order of the output terminal O4 through the output terminal O1, the output terminal O2, and the output terminal O3. . On the contrary, in response to the reverse control signal CON_R, the start signal SP is sequentially output to the plurality of output terminals O1 to O4 while shifting the start signal SP by half the clock CLK in the reverse direction. At this time, the start signal SP is sequentially shifted by the half clock CLK in order from the output terminal O4 to the output terminal O3 and the output terminal O2 in the order of the output terminal O1.

Each of the NAND gates NAND1 to NAND6 receives a signal output from two corresponding output terminals among the plurality of output terminals and one of the first and second sub clock signals SCLK1 and SCLK2 to output a selection signal. The NAND gates NAND1-NAND6 output a low level select signal when both the signal output from the two output terminals and the one sub clock signal SCLK1 and SCLK2 are high level. In addition, the scan driver 200 according to an exemplary embodiment of the present invention may include a buffer for each scan line that stores and outputs a selection signal output from each of the NAND gates NAND1 to NAND6 for a predetermined time.

4 is a diagram illustrating the bidirectional shift register 210 of FIG. 3.

As shown in FIG. 4, the bidirectional shift register 210 includes a plurality of bidirectional control units BC11-BC14 and a plurality of flip-flops SR1-SR4.

Specifically, in the bidirectional shift register 210, each bidirectional control unit BC11-BC14 receives the forward and reverse control signals CON_F and CON_R, and the bidirectional control unit BC11 receives the start signal SP in the forward direction. The bidirectional control unit BC14 receives the start signal SP in the reverse direction. The output terminals out1-out4 of the bidirectional control units BC11-BC14 are connected to the input terminals P1-P4 of the flip-flops SR1-SR4, respectively. The bidirectional control units BC11-BC14 configure the paths of the plurality of flip props SR1-SR4 in the forward or reverse directions according to the forward and reverse control signals CON_F and CON_R. When the forward control signal CON_F is applied to each of the bidirectional control units BC11-BC14, ① which is sequentially connected from the flip-flop SR1 to the flip-flop SR4 through the flip-flop SR2 and the flip-flop SR3. Form a forward path such as When the reverse control signal CON_R is applied to each of the bidirectional control units BC11-BC14,? Which is sequentially connected from the flip-flop SR4 to the flip-flop SR1 via the flip-flop SR3 and the flip-flop SR2. Form a reverse path such as The clock signal CLK is input to the flip-flop SR1, and the output terminal Q1 is connected to an input terminal of the bidirectional controller BC12 and an input terminal of the NAND gates NAND1 and NAND2. The inverted clock signal / CLK is input to the flip-flop SR2, and the output terminal Q2 is connected to an input of the bidirectional controllers BC1 and BC3 and an input of the NAND gates NAND1 to NAND4, respectively. The clock signal CLK is input to the flip-flop SR3, and the output terminal is connected to an input of the bidirectional controllers BC12 and BC14 and an input of the NAND gates NANA3-NAND6, respectively. The inverted clock signal / CLK is input to the flip-flop SR4, and the output terminal is connected to an input of the bidirectional controller BC13 and an input of the NAND gates NAND5 and NAND6, respectively. The flip-flop SR1-SR4 outputs the output signal in the forward direction by using the start signal SP, the clock signal CLK, and the inverted clock signal / CLK when the forward path ① is formed according to the forward control signal CON_F. (sri: i is one of the natural numbers from 1 to 4) and is output while shifting the start signal SP by half a clock CLK. On the other hand, when the reverse path ② is formed according to the reverse control signal CON_R, the start signal is output to the output signal sri in the reverse direction by using the start signal SP, the clock signal CLK, and the inverted clock signal / CLK. Outputs SP while shifting by half a clock CLK.

The NAND gates NAND1-NAND6 receive two output signals sri and sr (i + 1) and one of the first and second sub-clock signals SCLK1 and SCLK2, respectively, and select signals (select [1] −). output select [6]). The (2j-1) th NAND gate NAND (2j-1) is an output signal sri of the jth flip-flop SRj and an output signal of the (j + 1) th flip-flop SR (j + 1). (sr (i + 1)) and the first sub-clock signal SCLK1 are NAND-operated to output the (2j-1) th select signal select [2j-1]. The (2j) th NAND gate NAND (2j) is an output signal of the jth flip-flop SRj, an output signal of the (j + 1) th flip-flop SR (j + 1), and a second sub clock signal ( The NLK operation of SCLK2) outputs the (2j) th select signal select [2j]. According to an embodiment of the present invention j is a natural number from 1 to 3.

FIG. 5 is a diagram illustrating the plurality of bidirectional control units BC1k in the scan driver 200 according to the first embodiment of the present invention. According to an embodiment of the present invention k is a natural number from 1 to 4.

The bidirectional controller BC1k includes a transmission gate TG 2k-1 included in the forward path and a transmission gate TG 2k included in the reverse path. In the bidirectional control unit BC1k, the forward control signal CON_F is applied to the control electrode of the n-channel element of the transmission gate TG 2k-1, and the reverse control signal CON_R is applied to the control electrode of the p-channel element. . The signal sr (k-1) output from the flip-flop SR (k-1) is applied to the first electrode of the n-channel and p-channel elements of the transmission gate TG (2k-1) and the second electrode of the transfer gate TG (2k-1). The electrode is connected to the input terminal of the flip-flop SRk. The reverse control signal CON_R is applied to the control electrode of the n channel element of the transfer gate TG (2k), and the forward control signal CON_F is applied to the control electrode of the p channel element of the transfer gate TG (2k). do. The signal sr (k + 1) output from the flip-flop SR (k + 1) is applied to the first electrode of the n-channel and p-channel elements of the transmission gate TG (2k), and the second electrode It is connected to the input terminal of the flip flop SRk. However, the start signal SP is applied to the first electrodes of the n-channel and p-channel devices of the transfer gate TG1, and the start signal SP is applied to the first electrodes of the n-channel and p-channel devices of the transfer gate TG1. Is applied.

6 and 7, the operation of the scan driver according to the first embodiment of the present invention will be described.

FIG. 6 illustrates signals sr1-sr4, select [1] -select [6] outputted according to the input signals CON_F, CON_R, SP, CLK, / CLK, SCLK1, and SCLK2 in the forward direction. . FIG. 7 illustrates signals sr1-sr4, select [1] -select [6] outputted according to the input signals CON_F, CON_R, SP, CLK, / CLK, SCLK1, and SCLK2 in the reverse direction. .

As illustrated in FIG. 6, when the forward control signal CON_F is at a high level and the reverse control signal CON_R is at a low level, the transfer gates TG1 and TG3 included in the forward paths of the respective bidirectional controllers BC11-BC14. The n channel and p channel elements of the TG5 and TG7 are turned on, and the n channel and p channel elements of the transmission gates TG2, TG4, TG6 and TG8 included in the reverse path are turned off to form a forward path. Then, the start signal SP is input to the flip-flop SR1 and shifted by half a clock to generate a signal sr1. The generated signal sr1 is input to the flip-flop SR2 and shifted by half a clock to generate a signal sr2. In this manner, flip-flop SR3 and flip-flop SR4 are shifted by half a clock to generate signal sr3 and signal sr4, respectively. The output signal sr1 is input to the NAND gates NAND1 and NAND2, and the signal sr2 is input to the NAND gates NAND1-NAND4. The signal sr3 is input to the NAND gates NAND3-NAND6, and the signal sr4 is input to the NAND gates NAND5 and NAND6. The NAND gate NAND1 generates a select signal select [1] in which the first sub-clock signal SCLK1 and the signals sr1 and sr2 both have a low level in the high level period T11, and the NAND gate NAND2 ) Generates a select signal select [2] having a low level in both the second sub-clock signal SCLK2 and the signals sr1 and sr2 in the high level period T12. In this manner, the NAND gates NAND3-NAND6 generate select signals (select [1] -select [6]) having low-level pulses in the periods T13-T16, respectively. Each period of the first and second sub-clock signals SCLK1 and SCLK2 is equal to half of the clock signal CLK period, and may alternately have a high level and a low level. In the first and second sub-clock signals according to an embodiment of the present invention, the high level section is shorter than the low level section. Then, it is possible to prevent the section where the select signal select [n-1] rises from the low level to the high level and the section where the select signal select [n] changes from the high level to the low level.

Hereinafter, the reverse scanning drive will be described with reference to FIG.

As illustrated in FIG. 7, when the forward control signal CON_F is at a low level and the reverse control signal CON_R is at a high level, the transmission gates TG2 and TG4 included in the reverse paths of the respective bidirectional controllers BC11-BC14. The n-channel and p-channel elements of the TG6 and TG8 are turned on, and the n-channel and p-channel elements of the transmission gates TG1, TG3, TG5 and TG7 included in the forward path are turned off to form a reverse path. Then, the start signal SP is input to the flip-flop SR4 and shifted by half a clock to generate a signal sr4. The generated signal sr4 is input to the flip-flop SR3 and shifted by half a clock to generate a signal sr3. In this manner, flip-flop SR2 and flip-flop SR1 are shifted by half a clock to generate signal sr2 and signal sr1, respectively. The output signal sr4 is input to the NAND gates NAND5 and NAND6, and the signal sr3 is input to the NAND gates NAND3-NAND6. The signal sr2 is input to the NAND gates NAND1-NAND4, and the signal sr1 is input to the NAND gates NAND1 and NAND2. The NAND gate NAND6 generates a select signal select [6] in which the second sub clock signal SCLK2 and the signals sr3 and sr4 both have a low level in the high level period T21, and the NAND gate NAND5 ) Generates a selection signal select [5] in which the first sub-clock signal SCLK1 and the signals sr3 and sr4 both have a low level in the high level period T22. In this manner, the NAND gates NAND1-NAND4 generate select signals (select [1] -select [4]) having low-level pulses in the periods T23-T26, respectively.

The bidirectional controllers BC11-BC14 of the scan driver 200 according to the first embodiment of the present invention have different forward and reverse control signals, but can control forward and reverse directions using one control signal. Specifically, when using one control signal having a high level in the forward path and a low level in the reverse path, n-channel and p-channel having a control electrode to which a reverse control signal is input at each transmission gate TG1-TG8. An inverter may be added between the control electrode of the device and the wiring to which the control signal is applied to control the forward and reverse paths.

As such, even when the display panel including the pixel circuit operated based on the selection signal is rotated 180 °, the same image may be displayed through reverse scanning. In addition, when the scan driver is used, the number of flip-flops required for the plurality of pixel circuit rows in the display panel corresponds to half the number of rows, so that the number of transistors is greatly reduced by reducing the number of flip-flops. The space occupied by the scan driver can also be greatly reduced.

Hereinafter, the scan driver 200 according to the second embodiment of the present invention will be described with reference to FIG. 8.

8 shows a circuit of a scan driver 200 according to a second embodiment of the present invention.

As shown in FIG. 8, in the scan driver 200 according to the second embodiment of the present invention, the bidirectional controllers BC21-BC24 have NAND gates N1-N4 and UN1-1 as compared with the first embodiment of the present invention. Two-way control can be performed using UN4, DN1-DN4).

The start signal ST and the forward control signal CON_F are input to the NAND gate UN1, and the output signal of the reverse control signal CON_R and the flip-flop SR2 are input to the NAND gate DN1. The outputs of the NAND gate UN1 and the NAND gate DN1 are input to the NAND gate N1. The output of the NAND gate N1 is input to the flip-flop SR1. The output signal of the flip-flop SR1 becomes one input of the NAND gate UN2. The output signal of the flip-flop SR1 and the forward control signal CON_F are input to the NAND gate UN2. In addition, the output signal of the reverse control signal CON_R and the flip-flop SR3 is input to the NAND gate DN2. The outputs of the NAND gate UN2 and the NAND gate DN2 are input to the NAND gate N2, and the output of the NAND gate N2 is input to the flip-flop SR2. The output signal of the flip-flop SR2 and the forward control signal CON_F are input to the NAND gate UN3, and the output signal of the reverse control signal CON_R and the flip-flop SR4 are input to the NAND gate DN3. The outputs of the NAND gate UN3 and the NAND gate DN3 are input to the NAND gate N3, and the output of the NAND gate N3 is input to the flip-flop SR3. The output signal of the flip-flop SR3 and the forward control signal CON_F are input to the NAND gate UN4, and the reverse control signal CON_R and the start signal ST are input to the NAND gate DN4. The outputs of the NAND gate UN4 and the NAND gate DN4 are input to the NAND gate N4, and the output of the NAND gate N4 is input to the flip-flop SR4.

Since the connection relationship and configuration of the NAND gates NAND1 to NAND6 are the same as those of the scan driver 200 according to the first embodiment of the present invention, a description thereof will be omitted.

Hereinafter, the forward scanning operation of the scan driver 200 according to the second embodiment of the present invention will be described.

First, when one input signal is at a low level, the NAND gate outputs a high level signal regardless of the other input signal. When the one input signal is at a high level, the NAND gate outputs an inverted signal of the other input signal. In the forward path, when the forward control signal has a high level and the reverse control signal has a low level, since one input of the NAND gates DN1-DN4 is the reverse control signal CON_R, the NAND gates DN1-DN4 are always present. A high level signal is output to one input of the NAND gates N1-N4. In addition, since one input signal is a high level forward control signal CON_F, the NAND gates UN1-UN4 output the inverted signal of the other input signal. Accordingly, since the NAND gates N1-N4 always have a high level, one of the NAND gates N1-N4 inverts the signal output from the other input, that is, the NAND gates UN1-UN4.

The NAND gate UN1 outputs the inverted start signal / ST by performing the NAND operation of the forward control signal CON_F and the start signal ST of the high level, and the NAND gate N1 outputs the inverted start signal. It receives (/ ST) and outputs the start signal ST as flip-flop SR1. The flip-flop SR1 shifts the input start signal ST by half a clock based on the clock signal CLK, and the NAND gate UN2 and the NAND gate at the rising edge timing of the clock signal CLK. The signal sr1 is outputted as (NAND1-NAND2). The NAND gate UN2 outputs the inverted signal / sr1 by performing the NAND operation of the high level forward control signal CON_F and the signal sr1, and the NAND gate N2 outputs the inverted signal / sr1. ) Is input to output the signal sr1 as a flip-flop SR2. The flip-flop SR2 outputs the signal sr2 to the NAND gate UN3 and the NAND gates NAND1-NAND4 by shifting the input signal sr1 by a half clock based on the clock signal CLK. The NAND gate UN3 outputs the inverted signal / sr2 by performing the NAND operation of the high level forward control signal CON_F and the signal sr2, and the NAND gate N3 outputs the inverted signal / sr2. ) Is input to output the signal sr2 to the flip-flop SR3. The flip-flop SR3 shifts by half a clock of the clock signal CLK and outputs a signal sr3 to the NAND gate UN4 and the NAND gates NAND3-NAND6. The NAND gate UN4 outputs the inverted signal / sr3 by performing the NAND operation of the high level forward control signal CON_F and the signal sr3, and the NAND gate N4 outputs the inverted start signal / The sr3 is input to output the signal sr3 as the flip-flop SR4. The flip-flop SR4 shifts by half a clock of the clock signal CLK to output the signal sr4 to the NAND gates NAND5 and NAND6.

In this manner, the start signal ST is sequentially transmitted from the flip-flop SR1 to the flip-flop SR2 and the flip-flop SR4 through the flip-flop SR3, and each flip-flop SR1-SR4 is clocked. The start signal SP is sequentially shifted by half a clock of the signal CLK to output the signals sr1-sr4.

Next, the reverse scanning operation of the scan driver 200 according to the second embodiment of the present invention will be described.

Like forward signal transmission, the NAND gate outputs a high level signal regardless of the other input signal when one input signal is low level, and outputs an inverted signal of the other input signal when one input signal is high level. The reverse control signal CON_R has a high level and the forward control signal CON_F has a low level in order to apply the selection signals select [1] -select [6] to the respective scan lines S1-S6 through the reverse path. Have Then, since one input of the NAND gates UN1-UN4 is the forward control signal CON_F, the NAND gates UN1-UN4 always output a high level signal to one input of the NAND gates N1-N4. In addition, since one input signal is the reverse control signal CON_R, the NAND gates DN1-DN4 output the inverted signal of the other input signal. Therefore, since the NAND gates N1-N4 always have a high level, one of the NAND gates N1-N4 inverts the signal output from the other input, that is, the NAND gates DN1-DN4.

The NAND gate DN4 outputs the inverted start signal / ST by performing the NAND operation of the high level reverse control signal CON_R and the start signal ST, and the NAND gate N4 outputs the inverted start signal. It receives (/ ST) and outputs the start signal ST as flip-flop SR4. The flip-flop SR4 shifts the input start signal ST by half a clock based on the clock signal CLK to the NAND gates DN3 and NAND gates NAND5 and NAND6 at a rising edge timing. Output the signal sr4. The NAND gate UN3 outputs the inverted signal / sr4 by performing the NAND operation of the high level reverse control signal CON_R and the signal sr4, and the NAND gate N3 outputs the inverted signal / sr4. ) Is input to output the signal sr4 to the flip-flop SR3. The flip-flop SR3 shifts the input signal sr4 by a half clock based on the clock signal CLK and outputs a signal sr3 to the NAND gates DN2 and NAND3-NAND6. The NAND gate DN2 performs the NAND operation of the high level reverse control signal CON_R and the signal sr3 to output the inverted signal / sr3, and the NAND gate N2 outputs the inverted signal / sr3. ) Is input to output the signal sr3 to the flip-flop SR2. The flip-flop SR2 outputs the signal sr2 to the NAND gates DN1 and the NAND gates NAND1-NAND4 by shifting by half a clock of the clock signal CLK. The NAND gate DN1 outputs the inverted signal / sr2 by performing the NAND operation of the high level reverse control signal CON_R and the signal sr2, and the NAND gate N1 outputs the inverted start signal / The sr2 is input to output the signal sr2 as the flip-flop SR1. The flip-flop SR1 shifts by half a clock of the clock signal CLK and outputs a signal sr4 to the NAND gates NAND1 and NAND2.

In this manner, the start signal ST is sequentially transferred from the flip-flop SR4 to the flip-flop SR3 and the flip-flop SR2 through the flip-flop SR2, and each flip-flop SR1-SR4 is clocked. The start signal SP is sequentially shifted by half a clock of the signal CLK to output the signals sr1-sr4.

Since operations of the NAND gates NAND1-NAND6 in the forward and reverse paths are the same as those of the scan driver according to the first embodiment of the present invention, description thereof is omitted.

The scan driver 200 according to the second embodiment of the present invention includes forward and bidirectional control signals input to the bidirectional controllers BC21 to BC24, respectively, but one control signal may be used to control forward and bidirectional directions. . Specifically, if a control signal having a high level in the forward path and a low level in the reverse path is used, the inverter further includes an inverter at one input terminal to which the reverse control signals of the respective NAND gates DN1-DN4 are input. Reverse control is possible.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to an embodiment of the present invention, there is provided a light emitting display device and a driving method thereof capable of displaying an image normally even when the display panel of the light emitting display device is rotated 180 degrees.

Further, according to an exemplary embodiment of the present invention, a light emitting display device and a method of driving the same may be provided by reducing the number of flip-flops of a scan driver, thereby reducing the required space.

Claims (14)

A plurality of scan lines each carrying a selection signal, Outputting a plurality of shift signals sequentially while shifting the first signal in a first direction in a first direction in response to a first control signal, and outputting the first signal in a second direction in response to a second control signal A bidirectional shift register for sequentially outputting the plurality of shift signals while shifting by a period; A first driver configured to logically operate two signals of the plurality of shift signals and a first sub clock signal to generate the selection signal of an odd-numbered scan line among the plurality of scan lines, and And a second driver configured to logically operate the two signals and the second sub-clock signal shifted with respect to the first sub-clock signal by a second period to generate the selection signal of an even-numbered scan line among the plurality of scan lines. Light emitting display device. The method of claim 1, The bidirectional shift register, A plurality of flip-flops each outputting the plurality of shift signals while shifting the first signal by the first period, and An output terminal is connected to an input terminal of each of the flip-flops to connect the plurality of flip-flops in the first direction in response to the first control signal, and connect the plurality of flip-flops in response to the second control signal. A light emitting display device comprising a plurality of bidirectional control units connected in two directions. The method of claim 2, The bidirectional control unit, A first gate transferring the shift signal from each flip-flop to an adjacent flip-flop in the first direction in response to the first control signal, and And a second gate transferring the shift signal from each flip-flop to adjacent flip-flops in the second direction in response to the second control signal. The method of claim 2, The bidirectional control unit, A first gate configured to receive a shift signal and the first control signal output from flip-flops adjacent in the second direction of a corresponding flip-flop among the plurality of flip-flops; A second gate configured as an input of a shift signal and a second control signal output from flip-flops adjacent in the first direction of a corresponding flip-flop among the plurality of flip-flops; And The outputs of the first and second gates are input, and if the first control signal is at the first level, the output signal is determined by the output of the first gate. A light emitting display device comprising a third gate from which a signal is determined. The method according to any one of claims 1 to 4, The first sub clock signal alternately has a first pulse of a first level and a second pulse of a second level, and the second period corresponds to half of the first period. The method of claim 5, The shift signal has a third pulse of the first level for a third period of time, The first driver generates the selection signal during a period in which two signals of the plurality of shift signals and the first sub clock signal have the first level in common. And the second driver generates the selection signal during a period in which the two signals and the second sub clock signal have the first level in common. The method of claim 6, The first level is a high level, the second level is a low level, The first and second driving units each include a plurality of NAND gates. The method of claim 6, The light emitting display device of which the width of the first pulse is shorter than the width of the second pulse. A plurality of scan lines each transmitting a selection signal; First and second flip-flops for shifting and outputting the input signal by a first period, Connect the output end of the first flip-flop to an input of the second flip-flop in response to a first control signal, and connect the output end of the second flip-flop to an input of the first flip-flop in response to a second control signal. Bidirectional control unit, A first logic circuit receiving the output signals and the first signals of the first and second flip-flops and outputting the selection signal to a corresponding first scan line of the plurality of scan lines; and A second logic for receiving the output signals of the first and second flip-flops and a second signal shifted with respect to the first signal by a second period and outputting the selection signal to a second scan line adjacent to the first scan line A light emitting display device comprising a circuit. The method of claim 9, The bidirectional control unit, A first switch connected between an output terminal of the first flip flop and an input terminal of the second flip flop and turned on in response to the first control signal; and And a second switch connected between an output terminal of the second flip flop and an input terminal of the first flip flop and turned on in response to the second control signal. The method according to any one of claims 9 to 10, And the first signal alternately has a first level and a second level, and the second period corresponds to half of the first period. The method of claim 11, Each of the signals output from the first and second flip-flops has a first level for a third period of time, The first logic circuit generates the selection signal during a period in which the signal output from the first and second flip-flops and the first signal have the first level in common; And the second logic circuit generates the selection signal during a period in which the signal output from the first and second flip-flops and the second signal have the first level in common. A driving method of a light emitting display device which transmits a plurality of selection signals to each of a plurality of scan lines. Sequentially outputting a plurality of shift signals while shifting the first signal in a first direction or a second direction by a first period in response to the first or second control signal, Generating the selection signal of an odd-numbered scan line among the plurality of scan lines by performing a logic operation on two signals of the plurality of shift signals and a first sub clock signal; and Generating a selection signal of an even-numbered scan line among the plurality of scan lines by performing a logic operation on the two sub-clock signals shifted by a second period with respect to the two signals and the first sub-clock signal. Method of driving. The method of claim 13, Coupling a plurality of flip-flops for shifting an input signal by the first period in response to the first control signal in the first direction; Connecting the plurality of flip-flops in the second direction in response to the second control signal.

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