KR100626858B1 - 단일 적재 워드를 형성하기 위해서 별개의 저장 버퍼 엔트리들로부터의 개별 바이트들의 전송을 적재하는 저장 시스템 - Google Patents

단일 적재 워드를 형성하기 위해서 별개의 저장 버퍼 엔트리들로부터의 개별 바이트들의 전송을 적재하는 저장 시스템 Download PDF

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KR100626858B1
KR100626858B1 KR1020017003691A KR20017003691A KR100626858B1 KR 100626858 B1 KR100626858 B1 KR 100626858B1 KR 1020017003691 A KR1020017003691 A KR 1020017003691A KR 20017003691 A KR20017003691 A KR 20017003691A KR 100626858 B1 KR100626858 B1 KR 100626858B1
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storage
load
byte
queue
address
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KR1020017003691A
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Korean (ko)
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KR20010073182A (ko
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위트데이비드비.
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824Operand accessing
    • G06F9/3834Maintaining memory consistency
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018Bit or string instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824Operand accessing
    • G06F9/3826Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
KR1020017003691A 1998-09-22 1999-04-03 단일 적재 워드를 형성하기 위해서 별개의 저장 버퍼 엔트리들로부터의 개별 바이트들의 전송을 적재하는 저장 시스템 KR100626858B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/158,465 US6141747A (en) 1998-09-22 1998-09-22 System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word
US09/158,465 1998-09-22

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KR20010073182A KR20010073182A (ko) 2001-07-31
KR100626858B1 true KR100626858B1 (ko) 2006-09-22

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KR1020017003691A KR100626858B1 (ko) 1998-09-22 1999-04-03 단일 적재 워드를 형성하기 위해서 별개의 저장 버퍼 엔트리들로부터의 개별 바이트들의 전송을 적재하는 저장 시스템

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US (1) US6141747A (US07585860-20090908-C00162.png)
EP (1) EP1116103B1 (US07585860-20090908-C00162.png)
JP (1) JP3871884B2 (US07585860-20090908-C00162.png)
KR (1) KR100626858B1 (US07585860-20090908-C00162.png)
DE (1) DE69932066T2 (US07585860-20090908-C00162.png)
WO (1) WO2000017746A1 (US07585860-20090908-C00162.png)

Families Citing this family (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU1634600A (en) * 1998-12-30 2000-07-24 Intel Corporation Memory array organization
US7779236B1 (en) * 1998-12-31 2010-08-17 Stmicroelectronics, Inc. Symbolic store-load bypass
US6247097B1 (en) * 1999-01-22 2001-06-12 International Business Machines Corporation Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
US6594754B1 (en) 1999-07-07 2003-07-15 Intel Corporation Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters
US6625723B1 (en) * 1999-07-07 2003-09-23 Intel Corporation Unified renaming scheme for load and store instructions
US6385676B1 (en) * 1999-07-12 2002-05-07 Hewlett-Packard Company Coherent ordering queue for computer system
US6481251B1 (en) 1999-10-25 2002-11-19 Advanced Micro Devices, Inc. Store queue number assignment and tracking
US6523109B1 (en) 1999-10-25 2003-02-18 Advanced Micro Devices, Inc. Store queue multimatch detection
US6591342B1 (en) * 1999-12-14 2003-07-08 Intel Corporation Memory disambiguation for large instruction windows
US6970996B1 (en) * 2000-01-04 2005-11-29 National Semiconductor Corporation Operand queue for use in a floating point unit to reduce read-after-write latency and method of operation
US7065632B1 (en) * 2000-04-07 2006-06-20 Ip First Llc Method and apparatus for speculatively forwarding storehit data in a hierarchical manner
US6678807B2 (en) * 2000-12-21 2004-01-13 Intel Corporation System and method for multiple store buffer forwarding in a system with a restrictive memory model
US7739483B2 (en) * 2001-09-28 2010-06-15 Intel Corporation Method and apparatus for increasing load bandwidth
US20030177312A1 (en) * 2002-03-15 2003-09-18 Aravindh Baktha Controlling a store data forwarding mechanism during execution of a load operation
US7085889B2 (en) 2002-03-22 2006-08-01 Intel Corporation Use of a context identifier in a cache memory
US7202942B2 (en) * 2003-05-28 2007-04-10 Doppler, Ltd. System and method for measuring velocity using frequency modulation of laser output
EP1462934A1 (en) * 2003-03-29 2004-09-29 Deutsche Thomson-Brandt Gmbh Method and apparatus for forwarding of results
US7177982B2 (en) * 2004-01-16 2007-02-13 International Business Machines Corporation Method to maintain order between multiple queues with different ordering requirements in a high frequency system
US7376817B2 (en) * 2005-08-10 2008-05-20 P.A. Semi, Inc. Partial load/store forward prediction
US7461238B2 (en) * 2006-06-07 2008-12-02 International Business Machines Corporation Simple load and store disambiguation and scheduling at predecode
US20070288725A1 (en) * 2006-06-07 2007-12-13 Luick David A A Fast and Inexpensive Store-Load Conflict Scheduling and Forwarding Mechanism
US7594100B2 (en) * 2006-09-29 2009-09-22 Sun Microsystems, Inc. Efficient store queue architecture
US7600098B1 (en) * 2006-09-29 2009-10-06 Sun Microsystems, Inc. Method and system for efficient implementation of very large store buffer
US7752393B2 (en) * 2006-11-16 2010-07-06 International Business Machines Corporation Design structure for forwarding store data to loads in a pipelined processor
US7640414B2 (en) * 2006-11-16 2009-12-29 International Business Machines Corporation Method and apparatus for forwarding store data to loads in a pipelined processor
US7721066B2 (en) * 2007-06-05 2010-05-18 Apple Inc. Efficient encoding for detecting load dependency on store with misalignment
US8447911B2 (en) * 2007-07-05 2013-05-21 Board Of Regents, University Of Texas System Unordered load/store queue
US7849290B2 (en) * 2007-07-09 2010-12-07 Oracle America, Inc. Store queue architecture for a processor that supports speculative execution
US8645670B2 (en) * 2008-02-15 2014-02-04 International Business Machines Corporation Specialized store queue and buffer design for silent store implementation
US8627047B2 (en) 2008-02-15 2014-01-07 International Business Machines Corporation Store data forwarding with no memory model restrictions
WO2010050947A1 (en) * 2008-10-30 2010-05-06 Hewlett-Packard Development Company, L.P. Redundant array of independent disks (raid) write cache sub-assembly
US20100250850A1 (en) * 2009-03-25 2010-09-30 Faraday Technology Corp. Processor and method for executing load operation and store operation thereof
US8914617B2 (en) * 2009-12-26 2014-12-16 Intel Corporation Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register
US10157060B2 (en) 2011-12-29 2018-12-18 Intel Corporation Method, device and system for control signaling in a data path module of a data stream processing engine
US9128725B2 (en) 2012-05-04 2015-09-08 Apple Inc. Load-store dependency predictor content management
US9600289B2 (en) 2012-05-30 2017-03-21 Apple Inc. Load-store dependency predictor PC hashing
US20140244984A1 (en) * 2013-02-26 2014-08-28 Advanced Micro Devices, Inc. Eligible store maps for store-to-load forwarding
US9619382B2 (en) 2013-08-19 2017-04-11 Intel Corporation Systems and methods for read request bypassing a last level cache that interfaces with an external fabric
US9665468B2 (en) 2013-08-19 2017-05-30 Intel Corporation Systems and methods for invasive debug of a processor without processor execution of instructions
US9632947B2 (en) * 2013-08-19 2017-04-25 Intel Corporation Systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early
US9361227B2 (en) 2013-08-30 2016-06-07 Soft Machines, Inc. Systems and methods for faster read after write forwarding using a virtual address
US10331583B2 (en) 2013-09-26 2019-06-25 Intel Corporation Executing distributed memory operations using processing elements connected by distributed channels
US9710268B2 (en) 2014-04-29 2017-07-18 Apple Inc. Reducing latency for pointer chasing loads
US9483409B2 (en) 2015-02-05 2016-11-01 International Business Machines Corporation Store forwarding cache
US9891824B2 (en) 2015-04-24 2018-02-13 International Business Machines Corporation Sub-block input/output (I/O) commands for storage device including byte stream buffer
US10514925B1 (en) 2016-01-28 2019-12-24 Apple Inc. Load speculation recovery
US10437595B1 (en) 2016-03-15 2019-10-08 Apple Inc. Load/store dependency predictor optimization for replayed loads
US10402168B2 (en) 2016-10-01 2019-09-03 Intel Corporation Low energy consumption mantissa multiplication for floating point multiply-add operations
US10558575B2 (en) 2016-12-30 2020-02-11 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10474375B2 (en) * 2016-12-30 2019-11-12 Intel Corporation Runtime address disambiguation in acceleration hardware
US10572376B2 (en) * 2016-12-30 2020-02-25 Intel Corporation Memory ordering in acceleration hardware
US10416999B2 (en) 2016-12-30 2019-09-17 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10467183B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods for pipelined runtime services in a spatial array
US10515046B2 (en) 2017-07-01 2019-12-24 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10515049B1 (en) 2017-07-01 2019-12-24 Intel Corporation Memory circuits and methods for distributed memory hazard detection and error recovery
US10469397B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods with configurable network-based dataflow operator circuits
US10445451B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features
US10445234B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features
US10387319B2 (en) 2017-07-01 2019-08-20 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features
US11086816B2 (en) 2017-09-28 2021-08-10 Intel Corporation Processors, methods, and systems for debugging a configurable spatial accelerator
US10496574B2 (en) 2017-09-28 2019-12-03 Intel Corporation Processors, methods, and systems for a memory fence in a configurable spatial accelerator
US10445098B2 (en) 2017-09-30 2019-10-15 Intel Corporation Processors and methods for privileged configuration in a spatial array
US10380063B2 (en) 2017-09-30 2019-08-13 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator having a sequencer dataflow operator
US10417002B2 (en) 2017-10-06 2019-09-17 International Business Machines Corporation Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
US11175924B2 (en) 2017-10-06 2021-11-16 International Business Machines Corporation Load-store unit with partitioned reorder queues with single cam port
US10394558B2 (en) 2017-10-06 2019-08-27 International Business Machines Corporation Executing load-store operations without address translation hardware per load-store unit port
US10606591B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10572256B2 (en) 2017-10-06 2020-02-25 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10579387B2 (en) 2017-10-06 2020-03-03 International Business Machines Corporation Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor
US10606590B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Effective address based load store unit in out of order processors
US10417175B2 (en) 2017-12-30 2019-09-17 Intel Corporation Apparatus, methods, and systems for memory consistency in a configurable spatial accelerator
US10445250B2 (en) 2017-12-30 2019-10-15 Intel Corporation Apparatus, methods, and systems with a configurable spatial accelerator
US10565134B2 (en) 2017-12-30 2020-02-18 Intel Corporation Apparatus, methods, and systems for multicast in a configurable spatial accelerator
US11307873B2 (en) 2018-04-03 2022-04-19 Intel Corporation Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging
US10564980B2 (en) 2018-04-03 2020-02-18 Intel Corporation Apparatus, methods, and systems for conditional queues in a configurable spatial accelerator
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US10891240B2 (en) 2018-06-30 2021-01-12 Intel Corporation Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator
US10853073B2 (en) 2018-06-30 2020-12-01 Intel Corporation Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator
US10459866B1 (en) 2018-06-30 2019-10-29 Intel Corporation Apparatuses, methods, and systems for integrated control and data processing in a configurable spatial accelerator
US10678724B1 (en) 2018-12-29 2020-06-09 Intel Corporation Apparatuses, methods, and systems for in-network storage in a configurable spatial accelerator
US11029927B2 (en) 2019-03-30 2021-06-08 Intel Corporation Methods and apparatus to detect and annotate backedges in a dataflow graph
US10817291B2 (en) 2019-03-30 2020-10-27 Intel Corporation Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator
US10915471B2 (en) 2019-03-30 2021-02-09 Intel Corporation Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator
US10965536B2 (en) 2019-03-30 2021-03-30 Intel Corporation Methods and apparatus to insert buffers in a dataflow graph
US11037050B2 (en) 2019-06-29 2021-06-15 Intel Corporation Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator
US11907713B2 (en) 2019-12-28 2024-02-20 Intel Corporation Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator
US11379241B2 (en) * 2020-07-30 2022-07-05 International Business Machines Corporation Handling oversize store to load forwarding in a processor

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69429612T2 (de) * 1993-10-18 2002-09-12 Via Cyrix Inc Schreibpuffer für einen superskalaren Mikroprozessor mit Pipeline
US5471598A (en) * 1993-10-18 1995-11-28 Cyrix Corporation Data dependency detection and handling in a microprocessor with write buffer
US5878245A (en) * 1993-10-29 1999-03-02 Advanced Micro Devices, Inc. High performance load/store functional unit and data cache
US5588126A (en) * 1993-12-30 1996-12-24 Intel Corporation Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system
US5784586A (en) * 1995-02-14 1998-07-21 Fujitsu Limited Addressing method for executing load instructions out of order with respect to store instructions
US5802588A (en) * 1995-04-12 1998-09-01 Advanced Micro Devices, Inc. Load/store unit implementing non-blocking loads for a superscalar microprocessor and method of selecting loads in a non-blocking fashion from a load/store buffer
US5832297A (en) * 1995-04-12 1998-11-03 Advanced Micro Devices, Inc. Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations
US5835747A (en) * 1996-01-26 1998-11-10 Advanced Micro Devices, Inc. Hierarchical scan logic for out-of-order load/store execution control
US6021485A (en) * 1997-04-10 2000-02-01 International Business Machines Corporation Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching

Also Published As

Publication number Publication date
EP1116103A1 (en) 2001-07-18
EP1116103B1 (en) 2006-06-21
DE69932066T2 (de) 2007-06-21
WO2000017746A1 (en) 2000-03-30
JP2002525742A (ja) 2002-08-13
JP3871884B2 (ja) 2007-01-24
US6141747A (en) 2000-10-31
KR20010073182A (ko) 2001-07-31
DE69932066D1 (en) 2006-08-03

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