KR100601484B1 - Hybrid flip-chip package substrate and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip package substrate and a method of manufacturing the same. In particular, a flip chip package substrate using a hybrid material in which a high dielectric constant ceramic powder is uniformly dispersed in a polymer such as epoxy and an insulating material between a power board and a ground plate. It relates to a manufacturing method.

In addition, according to the present invention, a plurality of circuit layers for providing a signal input from the outside to the flip chip; A plurality of power layers having a circuit pattern for providing power input from the outside to the flip chip and having an insulating ink filled in the spaces between the patterns; A plurality of ground layers formed with a circuit pattern for providing ground to the power input through the power layer, and filled with insulating ink in a space between the patterns; A first layer laminated between the plurality of circuit layers and the plurality of power supply layers or between the plurality of circuit layers and the plurality of ground layers, the plurality of interlayer via holes made of an insulating material and filled with insulating ink; Insulating layer; And a high capacity hybrid material composed of a high dielectric constant ceramic powder and a resin laminated between the power supply layer and the grounding layer paired with each other in the plurality of power supply layers and the plurality of grounding layers, and filled with insulating ink. A hybrid flip chip package substrate comprising a second insulating layer having interlayer via holes is provided.

Flip Chip Packages, Hybrid Materials, Ceramic

Description

Hybrid flip-chip package substrate and manufacturing method             

1 is a conceptual diagram for explaining generation of high frequency noise (SSN).

2 is a cross-sectional view of a six-layer flip-chip package substrate according to the prior art.

3 is a conceptual diagram in which a low inductance chip decoupling capacitor is mounted on the power / ground plate of a flip-chip package substrate.

 4 shows a low inductance chip capacitor (LICC) mounted on a flip-chip package substrate for a CPU and a chipset.

5 is a cross-sectional view of the hybrid flip chip package substrate according to an embodiment of the present invention.

6A to 6G are flowcharts illustrating a method of manufacturing a hybrid flip chip package substrate according to an embodiment of the present invention.

7 is an exemplary view showing the polishing process of FIG. 6C.

8A to 8D are graphs for comparing the impedance simulation results of the prior art with the present invention.

<Explanation of symbols for the main parts of the drawings>

501 to 504: Insulation layer 601: Insulation layer

602: circuit layer 603: via hole

604 plating layer 605 ink

608: insulating layer 609: blind via hole

612: insulating layer 614: circuit layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip package substrate and a method of manufacturing the same. In particular, a flip chip package substrate using a hybrid material in which a high dielectric constant ceramic powder is uniformly dispersed in a polymer such as epoxy and an insulating material between a power board and a ground plate. It relates to a manufacturing method.

In general, a semiconductor package is to protect semiconductor chips such as single devices and integrated circuits formed by stacking various electronic circuits and wirings from various external environments such as dust, moisture, electricity, and mechanical loads, and to improve electrical performance of the semiconductor chips. In order to optimize and maximize, a signal input / output terminal to a main board is formed by using a lead frame or a printed circuit board (PCB), and molded using a sealing means.

Such semiconductor packages are required to be thin and small and high reliability in order to support the recent integration of semiconductor chips and miniaturization of electronic devices. An array type semiconductor package and a pin grid array using lead frames are required. The demand for (pin grid array, PGA) semiconductor packages, ball grid array (BGA) semiconductor packages (hereinafter referred to as 'BGA packages') is increasing.

The BGA package was developed to accommodate high-density semiconductor chips and multi-pinning needs. The BGA package has a plurality of conductive balls, such as solder balls, arranged in a uniform shape on the bottom for mounting on a main board. It is a type of surface mount package. In such a ball grid array, solder balls on the ball grid array substrate are electrically bonded to correspond to conductive connection patterns of a printed circuit board for mounting.

Most of the four or more flip-chip package substrates now include one or more power / ground planes.

As such, the passive and active components mounted on the printed circuit board have a power supply terminal called a power / ground plate inside the board for power supply required for operation.

In general, the power plate is the part where the power is supplied, and the ground plate is the purpose of the signal ground, and mainly means the reference point of the signal. That is, all of the four or more layers of flip chip package substrates have a power / ground plate for power supply, which is present in a plane form inside the substrate.

In particular, in the case of a flip-chip package board, active devices such as an integrated circuit (IC) clock MPU or a chipset are mounted, so that a plurality of chips can be supplied for stable power supply in a shorter time. A power / ground plate is needed.

For example, in the case of a high speed product employing a flip-chip bonding method, a clock of a CPU or a graphic chip set operates at a high speed of 2 GHz or more. These CPUs and chipsets require short rise times and more current, and signal lines with ICs, flip chip package substrates, and mother boards to operate at high speeds. It is designed to keep the gap short.

However, as the component speed increases, voltage fluctuations occur in the power supply / ground wires, and eventually high frequency noise called SSN (Simultaneous Switching Noise) or Delta-I (ΔI) is generated.

These high frequency noises (SSNs) can cause delays or logic faults in the system, resulting in poor system performance and poor system reliability.

1 is a conceptual diagram in which a high frequency noise (SSN) is generated (Equation 1) is a formula for generating the cause of SSN.

DV = L (DI / Dt)

In Equation 1, DV is high frequency noise (SSN), L is parasitic inductance, DI is current supplied to the chip, and Dt is the clock speed of the operating chip.

As shown in Equation 1, as the clock speed of the current chip increases, more and more current is required in the chip.

As a result, the chip's Simultaneous switching output buffers increase the SSN, reducing the reliability of the overall system.

To reduce the SSN, one of the effective methods is to reduce the inductance of the power / ground wiring when the current required for the device operation and switching speed cannot be changed.

At present, CPUs and chipsets operating at high speeds are applied to a high speed by applying a flip-chip package method.

Conventionally, in the case of a flip-chip package substrate having four or more layers, a power / ground plate for power supply uses a polymer resin such as general FR-4.

2 is a cutaway view of a six-layer flip-chip package substrate according to the prior art.

As shown in Fig. 2, the first layer is the signal layer, the second layer is the ground plate, the third layer is the power plate, the fourth layer is the power plate, the fifth layer is the ground plate, and the sixth layer is the signal layer.

Here, the two-layer ground plate and the three-layer power plate form a pair to supply power to the semiconductor package, and the four-layer power plate and the five-layer ground plate form a pair to supply the semiconductor package. Supplying power.

At this time, the insulating material constituting the power supply / ground plate is an epoxy resin like the general FR-4. Currently, the power / ground plane insulation material used in flip-chip package substrates worldwide is Ajinomoto Build-Up Film (ABF) insulation material of Ajinomoto of Japan.

The properties and content of ABF materials are described in detail in patent US 6,133,377 (Composition of Epoxy Resin, Phenol-Triazine-Aldehyde Condensate and Rubber).

Representative characteristics of ABF materials for flip-chip package substrates implemented in US Pat. No. 6,133,377 are dielectric constants of 3.4 to 3.8, dielectric loss of 0.017 to 0.023, and film thickness. Is 30-50 micrometers.

An epoxy material such as ABF is used as an insulating material between the two- and five-layer ground layers and the three- and four-layer power layers of FIG. 2 to fabricate flip-chip package substrates for MPUs and chipsets. have. Power line voltage fluctuation also occurs in the power wiring of the power / ground plate made of epoxy insulating material, and a low inductance chip decoupling capacitor (Low inductance) for high frequency is used to reduce the voltage fluctuation. By mounting a chip decoupling capacitor to directly supply the current required for circuit switching, the SSN can be reduced by significantly reducing the voltage drop effect by shielding the inductance of the power wiring.

3 is a conceptual diagram in which a low inductance chip decoupling capacitor is mounted on a power / ground plate of a flip-chip package substrate.

As shown in FIG. 3, a decoupling chip capacitor is mounted on a PCB main board and a low inductance chip capacitor is mounted on a flip-chip package substrate. It is connected to the power supply / ground plate to supply current for smooth system operation even in high frequency range.

4 shows a low inductance chip capacitor (LICC) mounted on a flip-chip package substrate for a CPU and a chipset.

As shown in FIG. 4, a LICC having a capacitance of 0.1 to 1 GHz on a CPU having a high speed and a flip chip package substrate for a chip set is an array type or an array type. In this case, it is mounted about 9 ~ 20 and supplies the current necessary for switching the IC. As the system speeds up in the future, current LICCs also have power loop inductance, via inductance, and Decoupling capacitor (MLCC or LICC) made of ceramic chip itself, and parasitic inductance generated at solder contact when MLCC or LICC is mounted on a substrate. When the noise (SSN) occurs, as the power voltage level decreases, the supply current of the driver decreases, thereby increasing the signal delay and causing EMI problems.

As the system gets faster and faster in the future, simply connecting a lot of LICCs to the power / ground will not cause the SSN to drop.

To overcome these problems, the power wiring must be shortened and parasitic inductance must be reduced at the same time. As a result, there is a need for a more stable power supply / grounding insulation material having a lower power supply / grounding inductance than a power supply / grounding plate made of an insulating material such as epoxy.

The problems of the prior art are summarized as follows.

Iii. High Power / Ground Inductance Generation

Dielectric constant 3.4 ~ 3.8, power supply / ground plate composed of the existing epoxy material of the insulation distance 30 ~ 50㎛ high power / ground impedance will generate a high voltage fluctuation on the power / ground plate. As a result, high frequency noise (SSN) of a system operating at a high speed causes errors in the high-speed operating chip.

Ii. Increased signal delay and EMI:

Decoupling capacitors (MLCC or LICC) made of ceramic chips on the power / ground plate made of existing epoxy materials and MLCCs or LICCs can be SMT mounted on a flip-chip package substrate. Due to the parasitic inductance at the solder contacts, a lot of high frequency noise (SSN) is generated in the power supply / ground plate, and as the power voltage level decreases, the supply current of the driver decreases, which increases the signal delay. And EMI problem occurs.

The present invention for solving the above problems, relates to a flip chip package substrate and a method of manufacturing the same to prevent the generation of high power / ground impedance to prevent the generation of high frequency noise due to voltage fluctuations.

Another object of the present invention is to provide a flip chip package substrate and a method of manufacturing the same, which can suppress parasitic inductance generation, prevent signal delay, and suppress EMI generation.

The present invention as described above, a plurality of circuit layers for providing a signal input from the outside to the flip chip; A plurality of power layers having a circuit pattern for providing power input from the outside to the flip chip and having an insulating ink filled in the spaces between the patterns; A plurality of ground layers formed with a circuit pattern for providing ground to the power input through the power layer, and filled with insulating ink in a space between the patterns; A first layer laminated between the plurality of circuit layers and the plurality of power supply layers or between the plurality of circuit layers and the plurality of ground layers, the plurality of interlayer via holes made of an insulating material and filled with insulating ink; Insulating layer; And a high capacity hybrid material composed of a high dielectric constant ceramic powder and a resin laminated between the power supply layer and the grounding layer paired with each other in the plurality of power supply layers and the plurality of grounding layers, and filled with insulating ink. And a second insulating layer having interlayer via holes.

In addition, the present invention comprises a first step of forming a power supply layer on both sides of the core layer and a through hole for interlayer conduction; A second step of filling the through hole with ink and polishing the cured ink; Stacking a high capacity hybrid material composed of a high dielectric constant ceramic powder and a resin; And a fourth step of forming a blind via hole after the ground layer is formed on the insulating layer of the third step.

Now, a preferred embodiment of the present invention will be described in detail with reference to the drawings of FIG. 5.

5 is a cross-sectional view of a hybrid flip chip package substrate according to an embodiment of the present invention.

As shown in FIG. 5, one layer of a hybrid flip chip package substrate according to an embodiment of the present invention is a signal layer, two layers are ground plates, three layers are power plates, and four layers are power plates, and five layers. Is the ground plane and the sixth layer is the signal layer.

Here, the two-layer ground plate and the three-layer power plate form a pair to supply power to the semiconductor package, and the four-layer power plate and the five-layer ground plate form a pair to supply the semiconductor package. Supplying power.

At this time, the insulating materials 502 and 504 constituting the power supply / ground plate are made of a hybrid film made of a high capacity hybrid material composed of a high dielectric constant ceramic powder and a resin.

In this case, the hybrid film is a high dielectric constant material having a high capacitance, and a composite material in which BaTiO ₃ ceramic powder having a high dielectric constant having a dielectric constant of 1,000 to 10,000 is mixed with a resin such as a thermosetting epoxy resin or polyimide. BaTiO ₃ powder is implemented in two forms (Bimodal), the size is 0.5 ~ 1.0 ㎛ diameter powder and 20 ~ 50nm diameter micro powder in a volume ratio of 3: 1 to 5: 1 by mixing More preferably, it is in the form of a polymer ceramic composite having a high dielectric constant of about 20 to 60 evenly dispersed in the resin.

In addition, to reduce the inductance of the power supply / ground plate, the insulation distance of the power supply / ground is formed to a very thin thickness within 10 μm.

6A to 6G are flowcharts illustrating a method of manufacturing a hybrid flip chip package substrate according to an embodiment of the present invention.

6A is a three- and four-layered cross-section in which a circuit of a six-layer flip-chip package substrate is formed. An insulation material is formed on the core layer 601 with a thickness of 100 to 1000 μm, and the core layer 601 is formed. 2-20 micrometer copper foil 602 is bonded by both sides, and constitutes CCL (Copper Clad Laminate).

Here, the copper foil 602 is etched to form circuit wiring, and the via hole 603 is formed by a mechanical drill to electrically conduct the upper and lower portions of the CCL and is conducted to the copper plating layer 604. The third and fourth floors are electrically used as power plates.

6B and 6C fill the via holes, flatten the pattern, and perform buffering, as described in detail in No. 2896116 to Noda Screen.

In brief, it is shown that the three- and four-layer circuit wiring 602 and the via hole 603 of the flip-chip package substrate on which the circuit of FIG. 6A is formed are simultaneously filled with ink 605. give.

In this case, the ink is a light curable resin and is printed on the substrate through a printing process. The reason for such a flat coating is that the high capacity hybrid material 608 without flow does not completely fill the space between the circuit wiring 602 and the wiring or the via hole 603 at the time of lamination or printing. Hybrid materials 608 are formed before lamination or printing to prevent void defects from occurring.

6C shows that after curing the ink 605, the substrate circuit wiring is exposed by polishing, whereby it is important to polish the circuit wiring 602 and the cured ink 605 to the same height. A more detailed process is shown in Figure 7, which uses a ceramic buffer 710 to polish the circuit wiring 602 and the cured ink 605 to the same height.

Subsequently, referring to FIG. 6D, a hybrid film 608 made of a high capacity hybrid material composed of a high dielectric constant ceramic powder and a resin may be formed of three layers used as power plates of a flip-chip package substrate. It is laminated or printed on top of four layers to form a dielectric layer.

In this case, the hybrid film 608 is a high dielectric constant material having a high capacitance, and a BaTiO ₃ ceramic powder having a high dielectric constant having a dielectric constant of 1,000 to 10,000 is preferably a composite form in which a resin such as a thermosetting epoxy resin or a polyimide is mixed. The material is implemented in two forms (Bimodal) of the size of the BaTiO ₃ powder, the size is 0.5 ~ 1.0 ㎛ diameter powder and 20 ~ 50nm diameter micro powder of 3: 1-5: 1 volume ratio It is more preferable to form a polymer ceramic composite having a high dielectric constant of about 20 to 60 by mixing and dispersing evenly in the polymer resin.

In addition, to reduce the inductance of the power supply / ground plate, the insulation distance of the power supply / ground is formed to a very thin thickness within 10 μm.

Next, referring to FIG. 6E, a micro drill 609 is formed in the laser drill to electrically conduct the layers 2 and 4, which are electrical wiring layers, and the layers 3 and 4, which are power plates. At this time, the upper portion of the hybrid film 608 and the inner wall of the micro via 609 are electroless copper plating and electrolytic copper plating to form a copper conductive layer.

In addition, reference numeral 610 denotes a circuit and an electrode wiring made using a PCB circuit forming process as a copper conductive layer. Layers 2 and 5 are electrically used as ground wiring layers.

Referring to FIG. 6F, an insulating layer 612 having a dielectric constant of about 2 to 4.5 is formed to electrically insulate the first and sixth layers in which a signal line is formed and the second and fifth layers, which are ground layers. In this case, the process of forming the insulating layer is a process widely used in a printed circuit board (PCB).

Later, referring to FIG. 6G, a micro via 613 using a laser drill is used to electrically conduct the ground layers 2 and 5 and the layers 1 and 6 where signal lines are formed. ). At this time, the upper portion of 612 and the inner wall of 613 is electroless copper plating and electrolytic copper plating to form a copper conductive layer. Reference numeral 614 denotes a circuit and electrode wiring in which the copper conductive layer is formed using a PCB circuit forming process. The first and sixth layers are electrically used as signal wiring layers.

8A to 8D are graphs for comparing the impedance simulation results of the prior art and the present invention. The power / ground impedance of a four-layer flip chip package substrate using a "Speed 2000" program, which is a simulation program for power integrity analysis of Sigrity. Simulation result. First, the input variables required for the simulation are shown in Table 1 below.

Type A (Existing General Power / Ground) Type B (Chip Capacitor Mounted on Existing Power / Ground) Type C (thin high capacity hybrid power supply / ground) Permittivity (Dk) 3.8 3.8 29 Dielectric loss (Df) 0.027 0.027 0.019 Power / Ground Insulation Distance (um) 30 30 10

FIG. 8A is a diagram illustrating impedance simulation results of a power supply / ground plate according to the prior art, FIG. 8B is a graph illustrating impedance simulation results of power supply / ground when a chip capacitor is mounted according to the prior art, and FIG. In the case of using a hybrid film according to an embodiment of the present invention is a view showing the impedance simulation results.

8A is a impedance graph of a power / ground plate of a four-layer flip-chip package substrate made of a conventional epoxy material having a dielectric constant of 3.4 to 3.8 and an insulation distance of 30 to 50 μm. 8B shows four ESL 400pH, ESR 0.3ohm, capacitance 220nF ceramic chip decoupling capacitors to reduce the impedance of the power / ground plane of the zone's four-layer flip-chip package substrate. Mounted.

FIG. 8C is a four-layer flip-chip package substrate in which a thin plate high capacity hybrid power / ground plate having a dielectric constant of 29 and an insulating distance of 10 μm is described. FIG. 8D is a graph showing the same X-Y scale of FIGS. 8A, 8B, and 8C.

As the results show, the thin, high-capacity hybrid power supply / ground plate exhibits much lower impedance curves than conventional conventional power / ground plates. This is because hybrid power / ground plates have higher capacitance than normal power / ground.

In other words, in the case of a hybrid material in which high dielectric constant ceramic powder is evenly dispersed in a polymer such as epoxy, the capacitance of the power / ground plate is lowered by generating a much higher capacitance than a material composed solely of ordinary epoxy. The equation of complex impedance is introduced in (Equation 2).

Z is impedance, R is resistance, L is inductance, and C is capacitance. In other words, if dielectric constant increases, C increases and Z decreases, resulting in a stable power / ground plate. In addition, the lower the insulation distance of the power supply / ground plate, the more the capacitance present on the power supply / ground plate increases, thereby simultaneously lowering impedance.

The thin-layer high-capacity hybrid power / ground plate inserted 4-layer flip-chip package substrate is a 4-layer flip-chip package substrate in which a high-capacity ceramic chip capacitor is mounted on a general power / ground plate. lower impedance than the package substrate).

According to the present invention as described above thin plate high capacity hybrid power / ground plane (Hybrid Power / Ground Plane) has the effect that can have a lower impedance than the power / ground plate made of a conventional general epoxy.

In addition, according to the present invention, there is an effect that the hybrid power source / ground plate itself can play the role of a ceramic chip decoupling capacitor at a frequency below the resonance point.

In addition, according to the present invention, there is an effect of lowering the impedance even in the frequency region above the resonance point by the power / ground plate having a low thickness of less than 10㎛.

In addition, according to the present invention, such a hybrid power supply / ground plate replaces a power supply / ground plate made of a general resin of a CPU and a chipset flip-chip package substrate for high speed operation, and thus a lower power supply / ground plate. The fluctuation of the voltage can be implemented to improve the reliability (stability) of the system operating at high speed.

Claims (8)

A plurality of circuit layers for providing a signal input from the outside to the flip chip; A plurality of power layers having a circuit pattern for providing power input from the outside to the flip chip and having an insulating ink filled in the spaces between the patterns; A plurality of ground layers formed with a circuit pattern for providing ground to the power input through the power layer, and filled with insulating ink in a space between the patterns; A first layer laminated between the plurality of circuit layers and the plurality of power supply layers or between the plurality of circuit layers and the plurality of ground layers, the plurality of interlayer via holes made of an insulating material and filled with insulating ink; Insulating layer; And A plurality of interlayers, which are stacked between a plurality of power layers and ground layers in the plurality of power layers and the plurality of ground layers, are made of a high capacity hybrid material composed of a high dielectric constant ceramic powder and a resin, and are filled with insulating ink. Second insulating layer having via holes Hybrid flip chip package substrate comprising a. The method of claim 1, The second insulating layer, A hybrid flip chip package substrate, comprising: a composite obtained by mixing BaTiO ₃ ceramic powder having a high dielectric constant into a resin such as a thermosetting epoxy resin or polyimide. The method of claim 2, The second insulating layer is The size of BaTiO ₃ powder is realized in two forms (Bimodal), and the size is 0.5 ~ 1.0㎛ diameter powder and 20-50nm diameter micro powder is mixed in a volume ratio of 3: 1-5: 1 A hybrid flip chip package substrate characterized in that it is dispersed in the form of a polymer ceramic composite having a high dielectric constant of about 20 to 60. The method of claim 1, The thickness of the second insulating layer is a hybrid flip chip package substrate, characterized in that less than 10um. Forming a power supply layer on both sides of the core layer and forming a through hole for interlayer conduction; A second step of filling the through hole with ink and polishing the cured ink; Stacking a high capacity hybrid material composed of a high dielectric constant ceramic powder and a resin; And And a fourth step of forming a blind via hole after the ground layer is formed on the insulating layer of the third step. The method of claim 5, The second step, A step 2-1 of filling the through hole formed in the core layer with photocurable ink; Step 2-2 of curing the ink filled in the through hole of the step 2-1; And And a second step of exposing the power layer by polishing using a ceramic buffer after the ink is cured in step 2-2. The method of claim 5, The third step is a method of manufacturing a hybrid flip chip package substrate, characterized in that for stacking a high capacity hybrid film consisting of a high dielectric constant ceramic powder and a resin. The method of claim 5, The third step is a method for manufacturing a hybrid flip chip package substrate, characterized in that by printing and stacking a high capacity hybrid paste consisting of a high dielectric constant ceramic powder and a resin.

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