KR100578845B1 - Power supply and display device using the same - Google Patents

Abstract

The present invention relates to a power supply device and a display device using the same. The power supply apparatus according to the present invention includes an oscillator for outputting a first clock signal, a first inverter for inverting a first clock signal and outputting a second clock signal, and a latch for latching and outputting a first clock signal and a second clock signal. And a charge pump circuit for inputting an output signal of the latch circuit and outputting a first voltage, and a comparator for controlling the operation of the oscillator by comparing the first voltage and the second voltage.

Power Supplies, Latches, Oscillators, Comparators, Charge Pump Circuits

Description

Power supply and display device using the same {POWER SUPPLY AND DISPLAY DEVICE USING THE SAME}

1 is a conceptual diagram of an organic electroluminescent device.

2 illustrates a display device according to an exemplary embodiment of the present invention.

3 illustrates a power supply apparatus according to an embodiment of the present invention.

FIG. 4 shows the internal circuit of the oscillator shown in FIG. 3.

Figure 5 illustrates in more detail the latch according to an embodiment of the present invention.

6 is a circuit diagram illustrating a charge pump circuit according to an embodiment of the present invention.

7 exemplarily illustrates a clock signal applied to a charge pump circuit.

The present invention relates to a power supply, and more particularly, to a power supply of an organic electroluminescent (EL) display device.

In general, an organic EL display device is a display device for electrically exciting a fluorescent organic compound to emit light, and is capable of representing an image by voltage or current writing N × M organic light emitting cells. The organic light emitting cell has a structure of an anode, an organic thin film, and a cathode layer as shown in FIG. 1. The organic thin film has a multilayer structure including an emitting layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) to improve the emission efficiency by improving the balance between electrons and holes. It also includes a separate electron injecting layer (EIL) and a hole injecting layer (HIL).

The organic light emitting cell may be driven using a simple matrix method and an active matrix method using a thin film transistor (TFT) or a MOSFET. In the simple matrix method, the anode and the cathode are orthogonal and the line is selected and driven, whereas the active driving method connects the thin film transistor and the capacitor to each indium tin oxide (ITO) pixel electrode to maintain the voltage by the capacitor capacitance. It is a driving method. In this case, the active driving method is divided into a voltage programming method and a current programming method according to the type of signal applied to maintain the voltage on the capacitor.

The organic EL display device is composed of a display panel, various drivers for driving the display panel, and a power supply device, and the power supply device mainly comprises an oscillator and a charge pump circuit for generating a clock signal. The clock signal of the oscillator and the clock signal inverting the signal are input to the charge pump circuit, and the charge pump circuit outputs a desired voltage using the two clock signals input.

However, the conventional power supply has a problem in that the synchronization of the two clock signals are misaligned or the clock signals are distorted due to an internal delay of the inverter for inverting the clock signal of the oscillator. Therefore, a section in which both clock signals input to the charge pump circuit are high level or low level occurs. In this case, the capacitor of the charge pump circuit is not normally charged or discharged so that the desired voltage is not output.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a power supply device and a display device using the same to provide a desired voltage by matching synchronization of a plurality of clock signals input to a charge pump circuit and preventing distortion of the clock signal.

In order to achieve the above object, a power supply according to an aspect of the present invention includes an oscillator for outputting a first clock signal; A first inverter for inverting the first clock signal and outputting a second clock signal; A latch circuit for latching and outputting the first clock signal and the second clock signal; A charge pump circuit for outputting a first voltage by inputting an output signal of the latch circuit; And a comparator for controlling the operation of the oscillator by comparing the first voltage and the second voltage.

In a power supply according to an aspect of the present invention, the comparator causes the oscillator to output the first clock signal when the first voltage is lower than the second voltage, and wherein the first voltage is the first voltage. If the voltage is equal to or higher than 2, the oscillator is deactivated.

In a power supply according to an aspect of the present invention, the latch includes a second inverter for inverting the first clock signal and the second clock signal, and a third inverter for inverting an output signal of the second inverter. Include.

A power supply according to one aspect of the invention, further comprising a buffer circuit coupled between the latch and the charge pump circuit.

A power supply according to one aspect of the invention, further comprising a divider for distributing the first voltage, wherein the comparator compares the output voltage of the divider with the second voltage.

According to one or more exemplary embodiments, a display device includes: a display panel including a plurality of pixel circuits; A data driver for applying a data signal to the display panel; A scan driver for applying a selection signal to the display panel; A panel controller for controlling the data driver and the scan driver; And a power supply for supplying a first voltage to at least one of the display panel, the data driver, the scan driver, and the panel controller, wherein the power supply includes: an oscillator for outputting a first clock signal; A first inverter for inverting an output signal of the oscillator and outputting a second clock signal, a latch circuit for latching and outputting the first and second clock signals, and an output signal of the latch circuit, and outputting the first voltage And a comparator for comparing the first voltage and the second voltage to control the operation of the oscillator.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the following description, when a part is connected to another part, it includes not only the case where it is directly connected but also the case where it is electrically connected with another element between them. In the drawings, parts irrelevant to the present invention are omitted for clarity, and like reference numerals designate like parts throughout the specification.

2 illustrates a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the display device according to the exemplary embodiment of the present invention includes a display panel 100, a data driver 200, a scan driver 300, a panel controller 400, and a power supply device 500. It includes.

The display panel 100 is provided with a plurality of pixel circuits, a plurality of data lines for transmitting data signals to the pixel circuits, and a plurality of scanning lines for transmitting selection signals to the pixel circuits (not shown).

The data driver 200 applies a data signal to the display panel 100, and the scan driver 300 applies a selection signal.

The panel controller 400 controls the data driver 200 and the scan driver 300, and the data driver 200 displays the image data R, G, and B data in synchronization with the vertical synchronization signal V_sync. 100, and the scan driver 300 applies a selection signal to the display panel 100 in synchronization with the horizontal synchronization signal H_sync.

The power supply device 500 outputs a desired voltage by using a DC-DC converter, and supplies an appropriate power voltage to the display panel 100, the respective driving units 200 and 300, and the panel controller 400.

The data driver 200, the scan driver 300, and / or the panel controller 400 may be electrically connected to the display panel 100 or may be bonded to the display panel 100 and electrically connected to the tape carrier package. tape carrier package, TCP) or the like in the form of a chip. Alternatively, a flexible printed circuit (FPC) or a film may be mounted on the display panel 100 in the form of a chip or the like, and may be mounted on a chip on flexible board, chip on film). Alternatively, the data driver 200, the scan driver 300, and / or the panel controller 400 may be directly mounted on the glass substrate of the display panel 100, or the scan line, the data line, and the thin film transistor may be disposed on the glass substrate. It may be replaced or directly mounted with a driving circuit formed of the same layers.

3 illustrates a power supply apparatus according to an embodiment of the present invention.

As shown in FIG. 3, a power supply according to an embodiment of the present invention includes an oscillator 510, an inverter IN1, a latch 520, a charge pump circuit 530, and a comparator 540. .

The oscillator 510 generates a clock signal clk1 in response to the output signal of the comparator 540, and the inverter IN1 inverts the clock signal clk1 of the oscillator 510 to output the clock signal clk2. .

The latch 520 matches the synchronization of the clock signals clk1 and clk2 and compensates for the distortion generated in the clock signals clk1 and clk2.

The charge pump circuit 530 outputs a voltage Vout at a desired level using the clock signals clk1 and clk2.

The comparator 540 controls the operation of the oscillator 510 by comparing the output voltage Vout and the reference voltage Vref of the charge pump circuit 530. Specifically, the output voltage Vout of the charge pump circuit 530 is compared with the reference voltage Vref, and the absolute value of the output voltage Vout is smaller than the absolute value of the reference voltage Vref (that is, the output When the voltage Vout is lower than the reference voltage Vref), the oscillator 510 generates the clock signal clk1. When the output voltage Vout is higher than or equal to the reference voltage Vref, the oscillator 510 is generated. ) Outputs a fixed voltage rather than the clock signal clk1.

In addition, according to an exemplary embodiment of the present invention, as shown in FIG. 3, resistors R1 and R2 for distributing the output voltage Vout of the charge pump circuit 530 may be further included, and in this case, the reference voltage Vref. Is set as in Equation 1.

Here, Vref represents a reference voltage, and V1 represents an output voltage Vout of the desired charge pump circuit 530.

4 exemplarily illustrates an internal circuit of the oscillator 510 illustrated in FIG. 3.

As shown in FIG. 4, the oscillator 510 may be formed as a ring oscillator. According to an embodiment of the present invention, the oscillator 510 inputs the output signal of the comparator 540 as an enable signal (Enable), and outputs a clock signal clk1 or a fixed voltage signal.

Specifically, the oscillator 510 includes a NAND gate 511, a plurality of inverters 512, and a plurality of capacitors 513. The NAND gate 511 inputs an output signal of the oscillator 510 and an enable signal (Enable) to perform a NAND operation, and an output signal of the NAND gate 511 is input to the inverter 511 and inverted.

The capacitor 513 is charged when the inverted signal of the inverter 511 is a high level voltage, and is connected between the output terminals of several inverters 512 and ground to increase the delay of the oscillator 510 and lower the frequency. do.

Hereinafter, the operation of the oscillator 510 will be described in more detail.

When the output voltage Vout of the charge pump circuit 530 is lower than the reference voltage Vref, the comparator 540 outputs a high level voltage, and the enable signal Enable of the oscillator 510 becomes a high level. . Accordingly, the output signal of the NAND gate 511 becomes an inverted signal of the output voltage Out of the oscillator 510, and the high level and the low level when the even number of inverters 512 included in the oscillator 510 are connected. The clock signal clk1 that repeats is outputted.

On the other hand, when the output voltage Vout of the charge pump circuit 530 is higher than or equal to the reference voltage Vref, the comparator 540 outputs a low level voltage and the enable signal of the oscillator 510 is enabled. Goes to the low level. Accordingly, the output signal of the NAND gate 511 outputs a high level voltage regardless of the output signal Out of the oscillator 510, and the oscillator 510 outputs a fixed voltage.

Thus, the output signal of the oscillator 510 may be controlled according to the output voltage Vout of the charge pump circuit 530. When the output voltage Vout increases to a desired level, the oscillator 510 is deactivated. The output voltage Vout of the charge pump circuit 530 may be maintained.

Figure 5 illustrates in more detail the latch 520 according to an embodiment of the present invention.

According to an embodiment of the present invention, the latch 520 includes two inverters, and the two inverters IN2 and IN3 are connected to each other by engaging an input terminal and an output terminal.

As such, by engaging and connecting the two inverters IN2 and IN3, the oscillation signal clk1 of the oscillator 510 is primarily inverted through the inverter IN2 and secondly inverted through the inverter IN3. It is input to the buffer Buf1. In addition, the oscillation signal clk2 inverted through the inverter IN1 is primarily inverted through the inverter IN3, and secondly inverted through the inverter IN2 and input to the buffer Buf2. Accordingly, the synchronization of the clock signal clk1 and the clock signal clk2 is synchronized with each other through the two inverters IN2 and IN3, and distortion of the clock signals clk1 and clk2 can be prevented.

Hereinafter, the charge pump circuit 530 according to an embodiment of the present invention will be described with reference to FIGS. 6 and 7.

FIG. 6 is a circuit diagram illustrating a charge pump circuit according to an embodiment of the present invention, and FIG. 7 exemplarily illustrates clock signals clk1 and clk2 applied to the charge pump circuit 530. In the following description, it is assumed that the high level voltage of the clock signals clk1 and clk2 is VDD and the low level voltage is the ground voltage.

As shown in FIG. 6, the charge pump circuit 530 includes transistors M1-M4, diodes D1, and capacitors C1-C4.

The transistors M1-M4 are all diode-connected transistors, and FIG. 6 illustrates a case in which the transistors M1-M4 are all formed of transistors having a P-type channel. However, according to the embodiment, the transistors M1-M4 may be formed as transistors having N-type channels, and may be formed by other switching elements capable of performing a switching function.

The voltage VSS is applied to the drain of the transistor M1, and the transistors M2-M4 are connected in series between the source of the transistor M1 and the diode D1. Capacitors C1 and C3 are respectively connected between the source of transistors M1 and M3 and the signal line carrying the clock signal clk1, and capacitors C2 and C4 are respectively the source and clock signals of transistors M2 and M4. It is connected between signal lines carrying (clk2).

The diode D1 is connected between the output terminal of the charge pump circuit 530 and the source of the transistor M4 to prevent current from flowing from the transistor M4 to the output terminal.

Hereinafter, an operation of the charge pump circuit according to an embodiment of the present invention will be described with reference to FIG. 7.

When the high level clock signal clk1 is applied to the other electrode B1 of the capacitor C1 in the period T1, the transistor M1 is biased in the forward direction to charge the capacitor C1. At this time, since the transistor M1 is diode-connected, the voltage applied to the one electrode A1 of the capacitor C1 becomes as shown in Equation (2).

Here, V _A1 denotes a voltage applied to one electrode _A1 of the capacitor C1, and Vth1 denotes a threshold voltage of the transistor M1.

When a low level voltage is applied to the other electrode B1 of the capacitor C1 in the period T2, the transistor M1 is biased in the reverse direction and turned off. Therefore, since a current path through the capacitor C1 is not formed, one electrode A1 of the capacitor C1 is in a floating state. Since the voltage of the other electrode B1 of the capacitor C1 is changed from the high level voltage VDD to the low level voltage (ground voltage), the voltage of the one electrode A1 of the capacitor C1 is changed to the other electrode. It is changed by the voltage change amount (-VDD) of (B1). Equation 3 shows the voltage applied to the one electrode A1 of the capacitor C1 in the period T2.

The high voltage VDD is applied to the capacitor C2 to conduct the transistors M2 and M1, and the capacitor C2 is charged with a voltage corresponding to the voltage difference between the two electrodes A2 and B2.

Like the transistor M1, the transistor M2 is diode-connected, so that the voltage of one electrode A2 of the capacitor C2 is the voltage of the one electrode A1 of the capacitor C1 at the voltage V _A1 of the transistor M2. The sum is equal to the absolute value of the threshold voltage Vth2.

In this manner, when the clock signals clk1 and clk2 are applied to the other electrodes B1 and B3 of the capacitors C1 and C3 and the other electrodes B2 and B4 of the capacitors C2 and C4, the capacitors C1- Assuming that the voltages of the one electrodes A1-A4 of C4 are sequentially increased, and the threshold voltages of the transistors M1-M4 are all the same, the output voltage Vout is (VSS + 4 | Vth |-). 4VDD).

Therefore, if the high level voltage VDD values of the power supply VSS and the clock signals clk1 and clk2 are appropriately selected and the clock signals clk1 and clk2 are controlled, the desired output voltage Vout can be obtained.

According to an embodiment of the present invention, the clock signals clk1 and clk2 input to the charge pump circuit 530 are synchronized by the latch 520, and the distortion present in the clock signals clk1 and clk2 is latched. As compensated by 520, the voltage of the other electrodes B1-B4 of the capacitors C1-C4 can be accurately controlled.

Therefore, the phenomenon in which the clock signals clk1 and clk2 generated due to the delay of the inverter IN1 are shifted from each other can be improved, and the output voltage of the charge pump circuit 530 can be stabilized.

In the above embodiment, the case in which the charge pump circuit 530 outputs a negative voltage has been described, but according to the embodiment, the voltage VSS is set to a positive voltage and the transistors M1-M4 have an N type channel. The transistor may be formed of a transistor such that the charge pump circuit 520 outputs a positive voltage. In this case, the connection direction of the diode D1 should be opposite to that of FIG.

6 illustrates a charge pump circuit 530 including four transistors M1-M4 and four capacitors C1-C4, according to an embodiment. It is possible to form a charge pump circuit 530 of the type. Where N is a natural number

In the above, the light emitting display device according to the embodiment of the present invention has been described. The above-described embodiment is an embodiment to which the concept of the present invention is applied, and the scope of the present invention is not limited to the above embodiment, and various modifications may be made by using the concept of the present invention as it is.

According to the present invention, a power supply device capable of outputting a desired voltage by synchronizing synchronization of a clock signal input to a charge pump and a display device using the same can be provided.

Claims (7)

An oscillator for outputting a first clock signal; A first inverter for inverting the first clock signal and outputting a second clock signal; A latch circuit for latching and outputting the first clock signal and the second clock signal; A charge pump circuit for outputting a first voltage by inputting an output signal of the latch circuit; And A comparator for controlling the operation of the oscillator by comparing the first voltage and a second voltage Power supply comprising a. The method of claim 1, The comparator allows the oscillator to output the first clock signal when the first voltage is lower than the second voltage, and deactivates the oscillator when the first voltage is equal to or higher than the second voltage. Feeding device. The method of claim 1, The latch includes a second inverter for inverting the first clock signal and the second clock signal, and a third inverter for inverting the output signal of the second inverter. The method of claim 1, And a buffer circuit coupled between the latch and the charge pump circuit. The method of claim 1, And a divider for distributing the first voltage, wherein the comparator compares the output voltage of the divider and the second voltage. A display panel including a plurality of pixel circuits; A data driver for applying a data signal to the display panel; A scan driver for applying a selection signal to the display panel; A panel controller for controlling the data driver and the scan driver; And A power supply device for supplying a first voltage to at least one of the display panel, the data driver, the scan driver, and the panel controller Including; The power supply device includes an oscillator for outputting a first clock signal, a first inverter for inverting an output signal of the oscillator and outputting a second clock signal, a latch circuit for latching and outputting the first and second clock signals; And a charge pump circuit for inputting the output signal of the latch circuit to output the first voltage, and a comparator for controlling the operation of the oscillator by comparing the first voltage and the second voltage. The method of claim 6, The latch includes a second inverter for inverting the first clock signal and the second clock signal, and a third inverter for inverting an output signal of the second inverter.

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