KR100542947B1 - Flash memory cell - Google Patents

Flash memory cell Download PDF

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Publication number
KR100542947B1
KR100542947B1 KR1019980045189A KR19980045189A KR100542947B1 KR 100542947 B1 KR100542947 B1 KR 100542947B1 KR 1019980045189 A KR1019980045189 A KR 1019980045189A KR 19980045189 A KR19980045189 A KR 19980045189A KR 100542947 B1 KR100542947 B1 KR 100542947B1
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KR
South Korea
Prior art keywords
region
channel impurity
flash memory
memory cell
impurity region
Prior art date
Application number
KR1019980045189A
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Korean (ko)
Other versions
KR20000027286A (en
Inventor
심성보
이민규
신성훈
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019980045189A priority Critical patent/KR100542947B1/en
Publication of KR20000027286A publication Critical patent/KR20000027286A/en
Application granted granted Critical
Publication of KR100542947B1 publication Critical patent/KR100542947B1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11521Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324Gate electrodes for transistors with a floating gate

Abstract

The present invention relates to a flash memory cell, wherein in forming a channel impurity region between a source region and a drain region, the channel impurity region near the source region is lower than a conventional cell threshold voltage implant dose. In addition, since the channel impurity region near the drain region is higher than the conventional threshold voltage ion implantation dose, the impurity concentration of the channel impurity region is formed different from each other near the source and the drain, thereby minimizing the change of the threshold voltage of the cell. Improve the program speed of memory cells.

Description

Flash memory cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory cell. In particular, a flash memory cell capable of improving the program speed of a memory cell while minimizing a change in the threshold voltage of the cell by forming different impurity concentrations in a channel impurity region near source and drain. It is about.

In general, in order to improve the speed while uniformizing a program in a flash memory cell array, it is necessary to bring a high cell threshold voltage implant dose, and to provide a proper amount of current during a read operation. In order to improve the read speed, the cell threshold voltage ion implantation dose should be kept low. Due to these conflicting characteristics, it is difficult to improve the program speed of a flash memory cell. Conventionally, after performing an isolation mask process to define an active region and a field region, all cell regions are opened, and the cell threshold voltage ion implantation aid is performed. The process is being conducted to optimize the various types of experiments. Even if the cell threshold voltage ion implantation is optimized by this process, there is a limit in satisfying the program and read operation characteristics of the flash memory cell having the opposite characteristics.

1A and 1B are diagrams for describing a conventional stack gate type flash memory cell.

Referring to FIG. 1A, a conventional stacked gate type flash memory cell opens both cell regions after performing a device isolation mask process to define a field region and an active region, and performs active with an optimized cell threshold voltage ion implantation dose. The channel impurity region 12 is formed in the semiconductor substrate 11 in the region, and the floating gate 13 and the control gate 14 are stacked on a portion of the semiconductor substrate 11 on which the channel impurity region 12 is formed. And the source region 15 and the drain region 16 are formed by a source / drain impurity ion implantation process.

In the conventional stacked gate type flash memory cell, as shown in FIG. 1A, a channel impurity region 12 is formed to be constant. The program operation of the flash memory cell having the channel impurity region 12 is, as shown in FIG. 1B, in which electrons move from the source region 15 to the drain region 16 due to the positive voltage applied to the drain region 16. The pinch-off region P1 is applied to a high voltage near the drain region 16 by the drain voltage of the positive voltage applied to the channel impurity region 12. Many electrons passing through this pinch-off region P1 generate electrons and hole pairs due to ion collisions, most of which move toward the drain region 16 but some of them float due to the applied high gate voltage. The cell 13 is moved to the gate 13 to complete the program of the cell. The reference numeral 120 of FIG. 1B is a channel region formed by applying a voltage for a program.

Accordingly, an object of the present invention is to provide a flash memory cell capable of improving the reliability of the flash memory cell by satisfying all of the opposite characteristics of the program operation and the read operation of the flash memory cell.

A flash memory cell of the present invention for achieving the above object is a gate formed on a semiconductor substrate, a source region and a drain region formed on the semiconductor substrate on both sides of the gate, and a semiconductor between the source region and the drain region below the gate And a dual channel impurity region formed on the substrate and including a first channel impurity region near the source region and a second channel impurity region near the drain region having a higher concentration than the first channel impurity region.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

2A and 2B illustrate a stack gate type flash memory cell according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, in the stack gate type flash memory cell of the present invention, after the device isolation mask process for defining the field region and the active region is performed, the cell threshold voltage ion implantation dose is changed so that the first impurity concentration is low. The channel impurity region 22a and the second channel impurity region 22b having a high impurity concentration are respectively formed to form the dual channel impurity region 22 having different impurity concentrations in the semiconductor substrate 21 of the active region, and the dual channel impurity is formed. The floating gate 23 and the control gate 24 are formed in a stacked structure on a portion of the semiconductor substrate 21 on which the regions 22 are formed, and the source region 25 and the drain region are formed by a source / drain impurity ion implantation process. 26) is formed.

The stack gate type flash memory cell of the present invention has a double channel impurity region 22 composed of first and second channel impurity regions 22a and 22b, as shown in FIG. 2A. Assuming that a parameter such as a current or a cell threshold voltage is the same in the conventional stack gate type flash memory cell shown in FIG. 1A and the stack gate type flash memory cell of the present invention shown in FIG. 2A, a first channel The impurity region 22a is formed near the source region 25 by making the cell threshold voltage ion implantation dose lower than the conventional dose, and the second channel impurity region 22b is the cell threshold voltage ion implantation dose. Is formed near the drain region 26 so as to be higher than the existing dose amount. The first and second channel impurity regions 22a and 22b are formed by two mask processes, and the order of the processes may be any one. In order to prevent the overall cell threshold voltage from changing, the length of the second channel impurity region 22b is shorter than that of the first channel impurity region 22a. After forming a mask to shorten the length of the second channel impurity region 22b, a tilt implantation method may be applied.

The program operation of the flash memory cell having the dual channel impurity region 22 is characterized in that electrons move from the source region 25 to the drain region 26 due to the positive voltage applied to the drain region 26, as shown in FIG. 2B. The pinch-off region P2 to which a high voltage is applied in the vicinity of the drain region 26 is generated by the drain voltage of the positive voltage or more applied to the channel impurity region 22. Many electrons passing through this pinch-off region P2 generate electrons and hole pairs due to ion collisions, and most of them move toward the drain region 26, but some of them move due to the applied high gate voltage. The cell is moved to the floating gate 23 to complete the program of the cell. The reference numeral 220 of FIG. 2B is a channel region formed by voltage application for a program.

In the conventional stack gate type flash memory cell shown in FIG. 1A and the stack gate type flash memory cell of the present invention shown in FIG. 2A, it is assumed that a parameter such as a current or a cell threshold voltage is the same. The channel region (indicated by reference numeral 220 of FIG. 2B) of the present invention is formed at a greater distance from the drain region 26 than the conventional channel region (indicated by reference numeral 120 of FIG. 1B) when voltage is applied. This results in the length of the pinch-off region P2 of the present invention being longer than that of the conventional pinch-off region P2. Generally, programming is performed by electron and hole pairs generated by ion collision of electrons passing through the pinch-off region, and the more the electron and hole pairs are generated, the faster the programming speed is. Therefore, the longer the length of the pinch-off region P2 of the present invention, the more the ion collision of electrons, the more electrons and hole pairs are generated, thereby improving the program speed.

On the other hand, the read operation speed is improved when the cell threshold voltage ion implantation dose is low, but in the present invention, the impurity of the first channel impurity region 22a is increased due to the increase in the impurity concentration of the second channel impurity region 22b. By lowering the density, it is possible to prevent the slowing down of the read operation.

Incidentally, by lowering the channel impurity concentration toward the source region 25, it is possible to reduce the band-to-band tunneling current generated during erasure in the source region 25. As a result, the source current during erasing can be reduced to suppress the voltage drop of the source line due to the increase in current.

As described above, the present invention forms different impurity concentrations in the channel impurity region in the vicinity of the source and the drain, so that the program speed of the memory cell is increased to make a high speed device, and the test in actual memory production as the speed is increased. It can reduce the time, bringing economic effect, and reduce the band-to-band tunneling current when erasing with the low channel concentration of the source part, and also improve the program characteristics without changing the existing parameters such as current or cell threshold voltage. You can.

1A and 1B are diagrams for explaining a conventional stacked gate type flash memory cell.

2A and 2B illustrate a stack gate type flash memory cell according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11 and 21: semiconductor substrate 12 and 22: channel impurity region

22a and 22b: first and second channel impurity regions

13 and 23: floating gate 14 and 24: control gate

15 and 25 source regions 16 and 26 drain regions

120 and 220: channel regions P1 and P2: pinch-off regions

Claims (2)

  1. A gate formed on the semiconductor substrate,
    A source region and a drain region formed on both of the gate semiconductor substrates;
    A second channel impurity region formed in the semiconductor substrate between the source region and the drain region below the gate and having a concentration higher than that of the first channel impurity region and the first channel impurity region near the source region; A flash memory cell comprising a dual channel impurity region.
  2. The method of claim 1,
    The length of the second channel impurity region is shorter than the length of the first channel impurity region.
KR1019980045189A 1998-10-27 1998-10-27 Flash memory cell KR100542947B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019980045189A KR100542947B1 (en) 1998-10-27 1998-10-27 Flash memory cell

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Application Number Priority Date Filing Date Title
KR1019980045189A KR100542947B1 (en) 1998-10-27 1998-10-27 Flash memory cell

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Publication Number Publication Date
KR20000027286A KR20000027286A (en) 2000-05-15
KR100542947B1 true KR100542947B1 (en) 2006-03-28

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Publication number Priority date Publication date Assignee Title
KR100663344B1 (en) 2004-06-17 2007-01-02 삼성전자주식회사 non-volatile flash memory device having at least two different channel concentrations and fabrication method thereof
KR101503875B1 (en) 2008-03-17 2015-03-25 삼성전자주식회사 Semiconductor Device Capable Of Suppressing Short Channel Effect And Method Of Fabricating The Same

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