KR100464390B1 - Gate node manufacturing method for semiconductor device - Google Patents

Gate node manufacturing method for semiconductor device Download PDF

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KR100464390B1
KR100464390B1 KR1019970034569A KR19970034569A KR100464390B1 KR 100464390 B1 KR100464390 B1 KR 100464390B1 KR 1019970034569 A KR1019970034569 A KR 1019970034569A KR 19970034569 A KR19970034569 A KR 19970034569A KR 100464390 B1 KR100464390 B1 KR 100464390B1
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gate electrode
gate
forming
oxide film
gate oxide
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KR19990011465A (en
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배경성
신지철
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A method for forming a gate electrode of a semiconductor device is provided to decrease an angle of the corner of a gate electrode by forming the gate electrode by a dry etch process while forming a groove at the corner of the gate electrode in contact with a gate oxide layer. CONSTITUTION: A gate oxide layer(200) is formed on a semiconductor substrate(100). A conductive layer including a polysilicon layer is formed on the gate oxide layer. The conductive layer is patterned by a dry etch process using the gas including hydrogen bromide gas as etch gas to form a gate electrode(350) wherein the gate electrode and the gate oxide layer form a groove at the lower corner of the gate electrode in contact with the gate oxide layer. The gate electrode is covered with an insulation layer(500), including an oxide layer formed by a CVD(chemical vapor deposition) process.

Description

반도체 장치의 게이트 전극 형성 방법{Gate node manufacturing method for semiconductor device}Gate node manufacturing method for semiconductor device

본 발명은 반도체 장치 제조 방법에 관한 것으로, 특히 게이트 전극 형성 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate electrode.

반도체 장치를 구성하는 소자들 중에서 트랜지스터(transistor)는 그 작동에 있어서, 여러 가지의 요소에 의해서 영향을 받는다. 이러한 요소들 중에서 상기 트랜지스터를 형성하는 게이트 전극(gate node)과 그 하부의 게이트 산화막(gate oxide)의 계면부에서의 상기 게이트 전극의 모서리부의 형상은 트랜지스터의 작동에 중요한 영향을 미친다.Among the elements constituting a semiconductor device, a transistor is influenced by various factors in its operation. Among these elements, the shape of the edge portion of the gate electrode at the interface portion of the gate node forming the transistor and the gate oxide below it has an important influence on the operation of the transistor.

도 1 및 도 2는 종래의 게이트 전극 형성 방법을 설명하기 위해서 도시한 단면도이다.1 and 2 are cross-sectional views for explaining a conventional method of forming a gate electrode.

도 1은 게이트 전극(30)을 형성하는 단계를 나타낸다.1 illustrates a step of forming the gate electrode 30.

구체적으로, 반도체 기판(10) 상에 게이트 산화막(20)을 형성한다. 이후에 상기 게이트 산화막(20) 상에 도전막, 예컨대 불순물을 포함하는 폴리 실리콘막(polysilicon layer)을 형성하고, 상기 도전막 상에 식각 저지막 패턴(40)을 형성한다. 이후에, 상기 식각 저지막 패턴(40)을 마스크로 상기 도전막을 패터닝하여 게이트 전극(30)을 형성한다. 이때, 상기 게이트 전극(30)의 모서리부는 첨예한 각도, 예컨대, 대략 90°이하의 첨예한 각도를 가지는 형상이다. 즉, 상기 모서리부와 상기 게이트 산화막의 계면에는 첨예점(A)이 발생된다. 이러한 첨예점(A)이 발생되면, 상기 계면에서의 게이트 전극(30)의 모서리부가 핫 캐리어 전자(hot carrier electron)에 취약한 특성을 나타낸다. 따라서, 이러한 첨예점(A)의 발생은 상기 트랜지스터의 특성을 열화시킨다. Specifically, the gate oxide film 20 is formed on the semiconductor substrate 10. Thereafter, a conductive layer, for example, a polysilicon layer including an impurity is formed on the gate oxide layer 20, and an etch stop layer pattern 40 is formed on the conductive layer. Thereafter, the conductive layer is patterned using the etch stop layer pattern 40 as a mask to form a gate electrode 30. In this case, the corner portion of the gate electrode 30 has a sharp angle, for example, a sharp angle of about 90 ° or less. That is, a sharp point A is generated at the interface between the edge portion and the gate oxide film. When such a sharp point A is generated, the edge portion of the gate electrode 30 at the interface exhibits a property that is vulnerable to hot carrier electrons. Therefore, the occurrence of such a sharp point A deteriorates the characteristics of the transistor.

도 2는 열산화막(50)을 형성하는 단계를 나타낸다.2 shows a step of forming the thermal oxide film 50.

구체적으로, 게이트 전극(30)의 표면을 열산화시켜 상기 게이트 전극(30)을 뒤덮는 열산화막(50)을 형성한다. 이때, 게이트 전극(30)의 표면뿐만 아니라, 게이트 전극(30)과 게이트 산화막(20)의 계면부에서 열산화가 진행되어, 상기 게이트 전극(30)의 모서리부의 첨예한 각이 완화되어 둔각의 모서리 형태를 이룬다. 이와 같이 상기 게이트 전극(30)의 모서리부가 완화되므로 상기 첨예점(A)이 제거된다. Specifically, the surface of the gate electrode 30 is thermally oxidized to form a thermal oxide film 50 covering the gate electrode 30. At this time, not only the surface of the gate electrode 30, but also the thermal oxidation proceeds at the interface between the gate electrode 30 and the gate oxide film 20, the sharp angle of the corner portion of the gate electrode 30 is relaxed to obtuse angle It forms a corner. As such, the corner portion of the gate electrode 30 is relaxed, so that the sharp point A is removed.

그러나, 이러한 방법은 상기 게이트 전극(30)의 모서리부 하부에 국부적인 게이트 산화막(20) 두께의 증가를 가져온다. 이러한 게이트 산화막(20)의 국부적인 두께 증가는 트랜지스터의 전류 구동을 저해한다. 또한, 상기 열산화막(50)은 상기 첨예점을 제거할 정도로 그 두께가 두꺼워야하므로, 트랜지스터의 선폭 감소에 제한이 된다. 따라서, 반도체 장치가 고집적화됨에 따라 상기 열산화막(50)의 두께의 감소가 요구되고 있다.However, this method results in an increase in the thickness of the gate oxide film 20 that is localized below the edge of the gate electrode 30. This increase in the local thickness of the gate oxide film 20 inhibits the current driving of the transistor. In addition, the thermal oxide film 50 should be thick enough to remove the sharp point, thereby limiting the line width of the transistor. Therefore, as the semiconductor device is highly integrated, the thickness of the thermal oxide film 50 is required to be reduced.

본 발명이 이루고자 하는 기술적 과제는 게이트 산화막의 국부적인 두께의 증가없이 첨예점을 제거할 수 있는 반도체 장치 게이트 전극 형성 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for forming a gate electrode of a semiconductor device capable of removing a sharp point without increasing a local thickness of a gate oxide film.

상기의 기술적 과제를 달성하기 위하여 본 발명은, 반도체 기판 상에 게이트 산화막을 형성한다. 이후에 상기 게이트 산화막 상에 도전막을 형성한다. 이때, 상기 도전막은 폴리 실리콘막을 포함하여 이루어진다. 다음에, 상기 도전막을 패터닝하여 상기 게이트 산화막과 접촉하는 모서리부에 홈을 가지는 게이트 전극을 형성한다. 이때, 상기 게이트 전극을 형성하는 단계는 건식 식각 방법을 이용하여 수행된다. 또한, 상기 건식 식각 방법은 브롬화 수소 가스를 포함하는 가스를 식각 가스로 이용한다. 이후에, 상기 게이트 전극을 뒤덮는 절연막을 형성한다. 이때, 상기 절연막은 화학 기상 증착 방법을 이용하여 형성되는 산화막으로 이루어진다.In order to achieve the above technical problem, the present invention forms a gate oxide film on a semiconductor substrate. Thereafter, a conductive film is formed on the gate oxide film. In this case, the conductive film includes a polysilicon film. Next, the conductive film is patterned to form a gate electrode having a groove at a corner portion in contact with the gate oxide film. In this case, the forming of the gate electrode is performed using a dry etching method. In addition, the dry etching method uses a gas containing hydrogen bromide gas as an etching gas. Thereafter, an insulating film covering the gate electrode is formed. In this case, the insulating film is formed of an oxide film formed using a chemical vapor deposition method.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3 내지 도 5는 본 발명의 실시예에 의한 게이트 전극 형성 방법을 설명하기 위하여 도시한 단면도들이다.3 to 5 are cross-sectional views illustrating a method of forming a gate electrode according to an exemplary embodiment of the present invention.

도 3은 반도체 기판(100) 상에 게이트 산화막(200) 및 도전막(300)을 형성하는 단계를 나타낸다.3 illustrates a step of forming the gate oxide film 200 and the conductive film 300 on the semiconductor substrate 100.

구체적으로, 반도체 기판(100) 상에 게이트 산화막(200)을 형성한다. 이후에, 상기 게이트 산화막(200) 상에 도전막(300), 예컨대, 불순물을 포함하는 폴리 실리콘막을 형성한다.Specifically, the gate oxide film 200 is formed on the semiconductor substrate 100. Thereafter, a conductive film 300, for example, a polysilicon film including impurities is formed on the gate oxide film 200.

도 4는 게이트 전극(350)을 형성하는 단계를 나타낸다.4 illustrates a step of forming the gate electrode 350.

구체적으로, 도전막(300) 상에 식각 저지막 패턴(400)을 형성한다. 예컨대, 포토레지스트막을 형성하고 노광 및 현상하여 포토레지스트 패턴을 형성하여 상기 식각 저지막 패턴(400)으로 이용한다. 이어서, 상기 식각 저지막 패턴(400)을 마스크로 건식 식각 방법을 이용하여 상기 도전막(300)을 패터닝하여 게이트 전극(350)을 형성한다. 이때, 상기 건식 식각 방법은 게이트 산화막(200)과의 식각 선택비가 높은 가스, 예컨대 브롬화 수소(HBr) 가스를 포함하는 가스를 식각 가스로 이용하여 수행된다. Specifically, the etch stop layer pattern 400 is formed on the conductive layer 300. For example, a photoresist film is formed, exposed and developed to form a photoresist pattern, and used as the etch stop layer pattern 400. Subsequently, the gate layer 350 is formed by patterning the conductive layer 300 using a dry etching method using the etch stop layer pattern 400 as a mask. In this case, the dry etching method is performed using a gas having a high etching selectivity with respect to the gate oxide film 200, for example, a gas including hydrogen bromide (HBr) gas as an etching gas.

이와 같은 건식 식각 방법으로 상기 도전막(300)을 식각하면, 형성되는 게이트 전극(350)과 게이트 산화막(200)의 계면 부위가 상기 식각 가스에 의해서 식각되어 홈(B)이 형성된다. 즉, 게이트 산화막(200)과의 계면부에 인접하는 상기 게이트 전극(300)의 모서리부가 다른 표면부보다 더 식각되어 움푹한 홈(B)이 형성된다. 이와 같은 홈(B)이 형성됨에 따라 상기 모서리부의 첨예한 각도가 완화된다. 이에 따라 첨예점이 형성되지 않는다. When the conductive layer 300 is etched by the dry etching method, the interface portion between the gate electrode 350 and the gate oxide layer 200 to be formed is etched by the etching gas to form the groove B. That is, the edge portion of the gate electrode 300 adjacent to the interface portion with the gate oxide film 200 is etched more than other surface portions to form a recessed groove B. As the groove B is formed, the sharp angle of the corner portion is alleviated. As a result, no sharp point is formed.

또한, 종래의 열산화막(50) 형성에 의한 상기 모서리부의 각도의 완화는 상기 모서리부의 열산화에 의해 이루어지므로, 그 완화되는 부분이 차지하는 선폭(ΔX)이 상당히 길다. 이에 비해 본 실시예에서의 모서리부의 각도의 완화는 식각에 의해 형성되는 홈(B)에 의해서 이루어진다. 따라서 완화되는 부분이 차지하는 선폭(ΔX´)이 종래의 열산화막(50)에 의해서 완화되는 부분이 차지하는 선폭(ΔX)에 비해 작은 선폭을 가진다. 이에 따라, 유효 채널 길이(effective channel length)를 보다 더 확보할 수 있다. 따라서 트랜지스터의 전류 구동에 보다 더 유리하다.In addition, since the angle of the corner portion is relaxed by the conventional thermal oxide film 50 formation, the line width ΔX occupied by the thermal portion of the edge portion is considerably long. On the contrary, the angle of the corner portion in the present embodiment is relaxed by the groove B formed by etching. Therefore, the line width ΔX ′ occupied by the relaxed portion has a smaller line width than the line width ΔX occupied by the portion relaxed by the conventional thermal oxide film 50. Accordingly, an effective channel length can be further secured. Therefore, it is more advantageous for driving the current of the transistor.

도 5는 게이트 전극(350)을 뒤덮는 절연막(500)을 형성하는 단계를 나타낸다. 5 illustrates a step of forming an insulating film 500 covering the gate electrode 350.

구체적으로, 화학 기상 증착(CVD;Chemical Vapour Deposition) 방법을 이용하여 게이트 전극(350)을 뒤덮는 절연막, 예컨대, CVD 산화막을 형성한다. 이때, 상기 절연막(500)은 종래의 열산화막(50)과는 달리 첨예점(A)을 제거하는 목적을 가지지 않으므로 보다 얇게 형성할 수 있다. 예컨대, 종래의 열산화막(50)은 일반적으로 대략 100Å 정도의 두께로 형성됨에 비해, 상기 절연막(500)은 대략 50Å 정도의 두께로 형성될 수 있다. 따라서, 형성되는 트랜지스터의 선폭을 보다 더 감소시킬 수 있다. 또한, 상기 절연막(500)은 일정한 두께로 형성되므로, 게이트 산화막(200)의 국부적인 두께 증가를 일으키지 않는다. 따라서, 종래의 게이트 산화막(20)의 국부적인 두께 증가에 의한 트랜지스터의 특성 열화를 방지할 수 있다.Specifically, an insulating film, for example, a CVD oxide film, covering the gate electrode 350 is formed by using a chemical vapor deposition (CVD) method. At this time, unlike the conventional thermal oxide film 50, the insulating film 500 does not have the purpose of removing the sharp point (A) can be formed thinner. For example, the conventional thermal oxide film 50 is generally formed to a thickness of about 100 GPa, whereas the insulating film 500 may be formed to a thickness of about 50 GPa. Therefore, the line width of the transistor to be formed can be further reduced. In addition, since the insulating film 500 is formed to have a constant thickness, the local thickness of the gate oxide film 200 does not occur. Therefore, it is possible to prevent the deterioration of the characteristics of the transistor due to the local increase in thickness of the conventional gate oxide film 20.

이상, 본 발명을 구체적인 실시예를 통해서 상세히 설명하였으나, 본 발명은 이에 한정되지 않고, 본 발명의 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 그 변형이나 개량이 가능함이 명백하다.As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

상술한 본 발명에 따르면, 건식 식각 방법을 이용하여 게이트 전극을 형성함과 동시에, 게이트 산화막과 접촉하는 게이트 전극의 모서리에 홈을 형성함으로써 게이트 전극의 모서리의 각도를 완화시킬 수 있다. 따라서, 첨예점이 형성되지 않으므로, 종래의 열산화막을 CVD 산화막과 같은 절연막으로 대체할 수 있다. 이에 따라서, 게이트 산화막의 국부적인 두께 증가는 발생되지 않는다. 따라서, 트랜지스터의 구동 특성의 저하를 방지할 수 있다. 또한, 상기 절연막은 종래의 열산화막보다 더 얇게 형성될 수 있어, 형성되는 트랜지스터의 선폭을 보다 감소시킬 수 있다. According to the present invention described above, the gate electrode may be formed by using a dry etching method, and a groove may be formed in the corner of the gate electrode in contact with the gate oxide layer to reduce the angle of the corner of the gate electrode. Therefore, since no sharp point is formed, the conventional thermal oxide film can be replaced with an insulating film such as a CVD oxide film. Accordingly, no local increase in thickness of the gate oxide film occurs. Therefore, the fall of the drive characteristic of a transistor can be prevented. In addition, the insulating film may be formed thinner than the conventional thermal oxide film, thereby further reducing the line width of the formed transistor.

도 1 및 도 2는 종래의 게이트 전극 형성 방법을 설명하기 위해서 도시한 단면도들이다.1 and 2 are cross-sectional views illustrating a conventional method of forming a gate electrode.

도 3 내지 도 5는 본 발명의 게이트 전극 형성 방법을 설명하기 위해서 도시한 단면도들이다. 3 to 5 are cross-sectional views illustrating a method of forming a gate electrode of the present invention.

Claims (1)

반도체 기판 상에 게이트 산화막을 형성하는 단계;Forming a gate oxide film on the semiconductor substrate; 상기 게이트 산화막 상에 폴리 실리콘막을 포함하는 도전막을 형성하는 단계;Forming a conductive film including a polysilicon film on the gate oxide film; 상기 도전막을 브롬화 수소 가스를 포함하는 가스를 식각 가스로 이용하는 건식 식각으로 패터닝하여 상기 게이트 산화막과 접촉하는 하부 모서리부에 상기 게이트 산화막과 홈을 이루는 게이트 전극을 형성하는 단계; 및Patterning the conductive layer by dry etching using a gas containing hydrogen bromide gas as an etching gas to form a gate electrode forming a groove with the gate oxide layer at a lower edge portion in contact with the gate oxide layer; And 상기 게이트 전극을 뒤덮는 절연막을 화학 기상 증착 방법에 의해 형성된 산화막을 포함하여 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 장치의 게이트 전극 형성 방법.And forming an insulating film covering the gate electrode, including an oxide film formed by a chemical vapor deposition method.
KR1019970034569A 1997-07-23 1997-07-23 Gate node manufacturing method for semiconductor device KR100464390B1 (en)

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KR920005300A (en) * 1990-08-20 1992-03-28 정몽헌 Method of forming multi-faceted metal wiring

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920005300A (en) * 1990-08-20 1992-03-28 정몽헌 Method of forming multi-faceted metal wiring

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