KR100458288B1 - Double-Gate FinFET - Google Patents

Double-Gate FinFET Download PDF

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Publication number
KR100458288B1
KR100458288B1 KR20020005325A KR20020005325A KR100458288B1 KR 100458288 B1 KR100458288 B1 KR 100458288B1 KR 20020005325 A KR20020005325 A KR 20020005325A KR 20020005325 A KR20020005325 A KR 20020005325A KR 100458288 B1 KR100458288 B1 KR 100458288B1
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gate
oxide film
active region
fin active
nm
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KR20020005325A
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KR20030065631A (en
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이종호
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한국과학기술원
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double-gate FNT device and a method of fabricating the same, and more particularly, to a bulk active substrate using a bulk silicon substrate, wherein the fin active region of the silicon to be a body in which the channel is formed is nano-sized. The present invention relates to an electrically stable double-gate FFT device and a method of manufacturing the same, which are connected to a substrate and formed to form a fence in a longitudinal direction in which current flows.
Conventional double-gate devices are typically fabricated using SOI silicon substrates, which are expensive in wafers and result in floating body effects, breakdown voltage drop between drain / source, and increased off-current, which are possible in SOI MOS devices. There is a problem in that the thermal conductivity of the substrate is not good.
In the present invention, the bulk silicon substrate is used instead of the SOI silicon substrate, and the fin active region, which is the body in which the channel is formed, has a nano-sized width and is formed like a fence in the longitudinal direction in which current flows and is connected to the bulk silicon substrate.

Description

Double-gate FFF device and its manufacturing method {Double-Gate FinFET}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double-gate FNT device and a method of fabricating the same, and more particularly, to a bulk active substrate using a bulk silicon substrate, wherein the fin active region of the silicon to be a body in which the channel is formed is nano-sized. The present invention relates to an electrically stable double-gate FFT device and a method of manufacturing the same, which are connected to a substrate and formed to form a fence in a longitudinal direction in which current flows.

Nano CMOS device technology has been applied to logic circuits and memory technologies such as CPUs, which can generate tremendous added value.

The size of the system using silicon semiconductor technology must be smaller and require lower power consumption, while the device size must be smaller accordingly.

The most competitive device technology that can respond to this is CMOS device technology.

The gate size of these devices is currently being scaled down, and problems continue to arise.

The biggest problem is the so-called short channel effect.

Conventional CMOS technology has been fabricated primarily on bulk silicon substrates.

MOS devices made from bulk silicon are scaled down to gate lengths of 50 nm or less, so the process conditions are very sensitive to the characteristics of the device, and at channel lengths near 30 nm, the device's performance is not yet applicable to actual circuits. Not full yet.

The 30 nm CMOS device developed by Intel has a gate length of 30 nm, and the I-V characteristics are not superior to the conventional one.

In addition, since the area occupied by one device has not been reduced since the spacer region formed next to the gate which is not scaled down, there is little room for improvement in the degree of integration.

As the MOS device technology based on these bulk silicon substrates has been limited, researches on devices based on silicon on insulator (SOI) silicon substrates have been actively conducted to realize devices having a channel length of 30 nm or less. have.

Many studies have been conducted to analyze the characteristics of a device fabricated from a conventional bulk silicon substrate as it is on an SOI silicon substrate. However, the parasitic source / drain resistance is greatly increased due to the thin thickness of the silicon film. Selectively grow epitaxial layers.

In addition, since the body of the device is not connected to the substrate due to the characteristics of the SOI device, there is a problem in that the performance of the device is deteriorated due to poor floating body effect and thermal conductivity.

The implementation of the conventional structure on the SOI substrate does not improve the scaling down characteristics significantly compared to the device implemented in the bulk, and thus is the most suitable device structure for reducing the channel length of the CMOS device to 25 nm or less. Device structures have emerged.

In the dual-gate device, gate electrodes are provided on the upper and lower sides (left and right) or left and right sides (left and right sides) of the channel through which current flows, thereby greatly improving the control characteristics of the channel by the gate electrodes.

When the control characteristics of the channel by the gate are large, the leakage current between the source and the drain can be greatly improved as compared with the conventional single gate device, and thus, the drain induced barrier lowering (DIBL) characteristic can be greatly improved.

In addition, gates are present on both sides of the channel to dynamically change the threshold voltage of the device, thereby significantly improving on-off characteristics of the channel and suppressing short channel effects.

FIG. 1 is a diagram schematically illustrating a direction of a channel through which current flows in a conventional double-gate structure based on 100 wafer surfaces.

The gate 32 is formed on the left and right or top and bottom of the body (channel 34).

FIG. 1A is a kind of three-dimensional (3-D) device in which a source / drain is formed up and down by being formed perpendicular to a wafer in a direction of 100, and current flows up and down.

1B is a standard double-gate MOS device structure in which a channel 34 is formed on the same surface as the wafer and a gate 32 is formed below the channel in the direction 100 wafer, and current flows in the crystal direction 100 plane.

In FIG. 1C, unlike FIG. 1A, although the channel 34 is formed on a surface formed perpendicular to the direction 100 wafer surface, current flows in the same direction as that of the 100 wafer surface without forming the source / drain regions up and down.

2 shows a conventional FinFET structure, in which only a main part is shown without a metal layer for wiring.

2A and 2B are the same structure, and FIG. 2A is translucent and FIG. 2B is hatched.

It has a structure corresponding to FIG. 1C and a current direction.

By placing the gate electrodes 16 on both sides (or up and down) of the channel, the so-called short channel effect can be greatly improved.

Reference numeral 2a denotes an SOI silicon substrate, 6 and 10 are oxide films, and 12 is a gate oxide film.

A method for implementing a double-gate device having the features of FIGS. 1B and 1C will now be described in detail.

First, there are two ways to implement it.

First, as shown in FIG. 1B, the current flows horizontally in the same direction as the surface direction of the wafer.

In this structure, as in the conventional case, the channel 34 is formed in the crystal direction 100 of silicon, so that the Si-SiO 2 interface property is not deteriorated compared with the conventional structure.

The double-gate device of FIG. 1B has a gate 32 below and above the channel 34.

This device structure can be manufactured by controlling the film thickness of the body silicon region thinly and uniformly.

In order to form the gate 32 below and above the channel 34, a wafer bonding and etch-back process using a micro electro-mechanical system (MEMS) technique needs to be performed.

One of the very important requirements in a double-gate MOS device is that the two gates 32 must be self-aligned or the device's characteristics will be greatly degraded.

Much research is underway to configure the gate 32 in self-alignment in the device of FIG. 1B with the gate 32 below and over the channel 34, which introduces complexity in materials and processes.

To improve the scaling down characteristics of the device, the thickness of the channel silicon film must be reduced to 20 nm or less.

As such, when the silicon film having a thickness of 20 nm or less is used as the channel and the source / drain regions, the short channel effect of the device can be improved, but the source / drain parasitic resistance is greatly increased to degrade the device characteristics.

As a result, the complexity of the process is required to achieve self-alignment and reduce source / drain resistance.

Second, another method for implementing a double-gate MOS is to fabricate devices by forming gates 32 on both sides (left and right) of channel 34 as shown in FIG. 1C.

The MOS device of FIG. 1C is called a 'FinFET'.

The double-gate device of FIG. 1C forms both the sidewalls of the etched channel pattern by depositing a gate material by patterning and etching the width of the region 34, which is the channel 34, in SOI device technology to nanometer size (typically 50 nm or less). This is to use the main channel area.

In this structure, a channel through which current flows 34 is formed perpendicular to the wafer surface direction so that current flows.

The process of implementing the structure is characterized in that the process is greatly simplified compared to the structure in which the gate 32 is below / above.

However, since the channel 34 through which current flows is formed on the side surface of the film formed perpendicular to the silicon substrate having the surface of 100, the crystal direction of the channel is usually 110, and the interface characteristics are worse than that of the conventional 100 interface.

In order to solve this problem, if the channel is formed in the 45 degree direction with the primary flat zone of the wafer, the channel may be formed on the 100 silicon plane in the crystal direction.

Since the silicon region of the channel is defined by nano-patterning technology, the variation in the body width in which the channel is formed is relatively large compared to the double-gate device having a gate above and below (FIG. 1B), which causes a large variation in device characteristics. And basically the gate 32 is self-aligning on both sides of the channel 34.

However, since the source / drain has the same nano width as the body region, the parasitic source / drain resistance increases, which degrades the current driving capability of the device.

In order to solve this problem, attempts to reduce parasitic resistance by adding a process of depositing and patterning polycrystalline silicon or SiGe layers in a form other than self-alignment in areas to be source / drain have been announced. However, the addition of the process did not reduce the parasitic resistance between the thin channel and the source / drain regions.

That is, the double-gate MOS device formed on the conventional SOI silicon substrate 2a has a problem that the wafer price is much more expensive than the bulk wafer and the parasitic source / drain resistance increases.

In addition, since the body 34 in which the channel of the device is formed in FIG. 2 is not connected to the SOI silicon substrate 2a due to the characteristics of the SOI device, the body 34 has a floating body problem and the oxide film 10 formed on the SOI silicon substrate 2a In addition, the performance of the device is lowered by preventing heat generated in the device from being conducted to the SOI silicon substrate 2a.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to reduce parasitic resistance by growing an epi layer on a source / drain in a low price and self-aligned with a gate using a bulk wafer. The purpose of the present invention is to provide a double-gate FFT device and a method of manufacturing the same, which is a body in which a channel is formed and is connected to a bulk silicon substrate to solve the floating body problem and improve the device properties due to good thermal conductivity. .

In order to achieve the above object, the present invention provides a bulk silicon substrate, a fence-like Fin active region connected to the bulk silicon substrate and formed of single crystal silicon in the center of the bulk silicon substrate, and a Fin active region on the surface of the bulk silicon substrate. A second oxide film formed to a predetermined height of the first oxide film, a gate oxide film formed on both sidewalls of the Fin active region on the second oxide film, a first oxide film formed on the upper surface of the Fin active region equal to or thicker than the gate oxide film, and the first oxide film; A double-gate FIFNTE including a gate formed on the oxide layer, a source / drain formed on both sides of the Fin active region except for the Fin active region overlapping the gate, and a contact region and a metal layer formed on the contact portions of the source, drain and gate. To provide a device.

In order to achieve the above object, the present invention is a process for forming a fin-shaped active region of the fence-like with a single crystal silicon on a bulk silicon substrate, and forming a second oxide film to a predetermined height of the fin active region on the surface of the bulk silicon substrate And forming a gate oxide film on both sidewalls of the Fin active region formed on the second oxide film, and forming a first oxide film on the upper surface of the Fin active region equal to or thicker than the gate oxide film. Forming a gate over the oxide film, forming a source / drain in both fin active regions except the fin active region overlapping the gate, and forming a contact region and a metal layer in the contact portions of the source, drain, and gate It is to provide a method for manufacturing a double-gate FNT device comprising a.

1A to 1C are perspective views schematically showing the direction of a channel through which current flows in a conventional double-gate structure with respect to a wafer surface.

2A and 2B are perspective views showing the structure of a conventional FinFET device with translucent and hatching.

3A and 3B are perspective views of a FinFET device according to the present invention with translucency and hatching.

4A and 4B are plan views showing a general perspective view and a pattern thereof of FIG. 3A.

5A and 5B are a perspective view showing a FinFET structure and a plan view showing a pattern thereof according to another embodiment of the present invention.

6A through 6D are plan views illustrating respective mask steps for implementing FIG. 4.

FIG. 7 is a cross-sectional view of the perspective view of FIG. 4 cut in the horizontal and vertical directions about a channel. FIG.

FIG. 8 is a cross-sectional view of the perspective view of FIG. 5 cut in horizontal and vertical directions with respect to a channel. FIG.

9A to 9D are exemplary views illustrating a process of implementing a body structure of a FinFET device according to the first embodiment of the present invention.

10A to 10D are exemplary views illustrating a process of implementing a body structure of a FinFET device according to a second embodiment of the present invention.

11A to 11D are exemplary views illustrating a process of implementing a body structure of a FinFET device according to a third embodiment of the present invention.

12A to 12D are exemplary views illustrating a process of implementing a body structure of a FinFET device according to a fourth embodiment of the present invention.

13A to 13D are exemplary views illustrating a process of implementing the body structure of the FinFET device according to the fifth embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

2a: SOI silicon substrate 2b: bulk silicon substrate

4: Fin active region 6: First oxide film

10 second oxide film 12 gate oxide film

14 nitride film 16 gate

18: selective epi layer 20: third oxide film

22: buffer oxide film 24: oxidation resistant nitride film

26 spacer oxide film 28 field oxide film

30 spacer 32 gate

34: body (channel) 46: contact area

48: metal layer

Hereinafter, the present invention will be described with reference to the accompanying drawings.

Looking at the basic configuration of the present invention first,

A bulk silicon substrate 2b,

A fence-like Fin active region 4 connected to the bulk silicon substrate 2b and formed of single crystal silicon in the middle of the bulk silicon substrate;

A second oxide film 10 formed on the surface of the bulk silicon substrate 2b up to a predetermined height of the Fin active region 4;

A gate oxide film 12 formed on both sidewalls of the Fin active region 4 on the second oxide film 10;

A first oxide film 6 formed on the upper surface of the Fin active region 4, the same as or thicker than the gate oxide film 12,

A gate 16 formed on the first and second oxide films 6 and 10,

Source / drain formed on both sides of the Fin active region 4 except the Fin active region 4 overlapping the gate 16;

The contact region 46 and the metal layer 48 formed on the contact portion of the source, drain, and gate 16 are formed.

In the above configuration, the parasitic capacitance component between the gate 16 and the bulk silicon substrate 2b can be reduced by setting the thickness of the second oxide film 10 to 20 nm to 800 nm.

In the above-described configuration, the contact region 46 in contact with the metal layer 48 may be larger than the width of the Fin active region 4 or the length of the gate 16 to improve the integration degree of the device and reduce the contact resistance.

In the above-described configuration, the fin active region 4 is made wider in the second oxide film 10 as it approaches the bulk silicon substrate 2b without making the fin active region 4 constant. Can be reduced.

In the above-described configuration, the Fin active region 4 may have a trapezoidal shape having a narrow upper width and a wider lower width.

In the above-described configuration, the two upper edges of the Fin active region 4 may be rounded through an oxidation process, an etching process, or an annealing in a hydrogen atmosphere of 900 ° C. or more, thereby improving durability of the device.

In the above-described configuration, the material constituting the gate 16 may be polysilicon, poly SiGe, or metal.

Figure 3 shows the structure of the device proposed in the present invention.

Except for the metal layer for wiring, only the main part is shown, the same structure is shown in Figure 3a translucent and Figure 3b is hatched.

The difference from FIG. 2 is that the Fin active region 4 is not floated and connected to the bulk silicon substrate 2b, whereby the characteristics are greatly improved.

That is, the body in which the channel is formed is connected to the bulk silicon substrate 2b so that there is no floating body problem of the device formed in the existing SOI silicon substrate 2a, and the heat generated in the channel of the device is lower than that of the conventional structure. It is much easier to get out into the bulk silicon substrate 2b.

It is also advantageous in terms of cost since it is manufactured using bulk wafers instead of SOI wafers.

FIG. 4A is a structure proposed in the present invention, which is added for comparison in the same structure as FIG. 3A, and FIG. 5A further shows the addition of an optional epi layer 18 to reduce parasitic source / drain resistance in the structure of FIG. 4A. will be.

4A and 5A show only main parts except for a metal layer for wiring, and FIGS. 4B and 5B show plan views of respective drawings.

In FIG. 4B, source / drain regions are formed in the fin active regions 4 where the gates 16 do not overlap.

In the Fin active region 4, since a contact is formed where a source / drain is formed and a metal line is connected to the fin structure, the fin structure has the same width as a channel, thereby greatly increasing the parasitic source / drain resistance. The parasitic resistance component is reduced as shown in FIG. 5B.

Here, the process of growing the selective epitaxial layer 18 only in the source / drain regions of the FinFET device will be described.

First, it is assumed that the device structure is formed up to the gate 16.

When the gate 16 is oxidized within 5 nm to about 20 nm with the gate 16 doped at least 10 20 cm −3 , compared to the doping of the channel (˜10 18 cm −3 ), the gate 16 has 3 The oxide film grows much thicker by about 5 times doping.

When the grown oxide film is etched again based on the thickness of the oxide film formed in the channel, the oxide film formed on the sidewall of the Fin active region disappears and the silicon of the Fin active region 4 is exposed.

At this time, the gate 16 in which the oxide film is relatively thick is still covered by the oxide film.

The selective epitaxial layer 18 is grown with the seeds exposed on the sidewalls of the Fin active region 4 of the source / drain as seeds.

In some cases, silicon may also be exposed on the sidewalls and the top of the Fin active region 4 and the selective epitaxial layer 18 may be grown using the seed as a seed.

The selective epitaxial layer 18 grown at this time may include single crystal silicon, single crystal SiGe, single crystal Ge, polysilicon, and poly SiGe.

In FIG. 4A and FIG. 5A, the dashed dashed line in the Fin active region 4 indicates the source / drain junction depth.

Here, it can be seen that the junction depth is located above the upper surface of the second oxide film 10 surface, and this is to control the short channel effect by adjusting the junction depth.

When the upper surface of the second oxide film 10 is referred to as a reference (0 nm), a short channel effect can be suppressed when the source / drain junction depth is upward, that is, larger than 0 nm and within 50 nm.

Conversely, if the junction depth is downward, i.e., smaller than 0 nm and larger than -50 nm, the current drive capability is increased rather than the short channel effect.

Another example of growing the selective epitaxial layer 18 is illustrated in FIG. 5A.

After the completion of the gate 16 formation in the process sequence, an insulating film is deposited to a thickness between 5 nm and 100 nm, and corresponds to the deposited thickness and the height of the Fin active region 4 protruding over the second oxide film 10. Anisotropic etching as much as the thickness of the insulating film is formed only near the gate 16 and the source / drain Fin active region 4 meets, and the other portion is exposed.

The selective epilayer 18 is grown to a value between 5 nm and 100 nm, with the silicon region of the exposed Fin active region 4 and the polysilicon region of the gate 16 as seeds.

The selective epitaxial layer 18 is then grown in the source / drain regions and also in the exposed polysilicon or SiGe gate 16 to reduce the resistance.

Of course, gate 16 and source / drain are electrically insulated.

FIG. 6 shows a mask sequence for implementing the structure shown in FIG. 4A.

In FIG. 6A, the fin active region 4 is implemented. In FIG. 6B, the gate 16 is implemented.

FIG. 6C shows the contact region 46 for source / drain contacts and the connection of the metal layer 48 for the FIG. 6D wiring.

FIG. 7 is a cross-sectional view of the structure of FIG. 4 proposed in the present invention in a horizontal and vertical direction centered on a channel.

The source / drain regions have the same width as the narrow Fin active regions 4 and have a large resistance.

The contact region 46 shown at the upper center is used to electrically connect the metal layer 48 and the source / drain formed in the Fin active region 4.

FIG. 8 is a cross-sectional view cut in the horizontal and vertical directions about the channel of the structure in which the selective epitaxial layer 18 is grown in the source / drain Fin active region 4 in the structure of FIG. 5 proposed in the present invention.

In addition, the lower left section (B-B 'section) shows that the selective epi layer 18 is formed on both exposed sidewalls of the Fin active region 4.

The selective epitaxial layer 18 can be grown on both sidewalls of the Fin active region 4 as well as on the top surface.

The source / drain region is wider than the Fin active region 4 through the selective epi layer 18 forming process, so that the parasitic source / drain resistance is small.

The contact region 46 displayed at the top of the center is used to electrically connect the metal pattern 48 and the source / drain formed in the Fin active region 4.

In the following description, in order to show the body in which the channel of the proposed structure is formed, the two-dimensional cross section where the main part of the channel and the gate 16 are shown, without using a three-dimensional picture.

FIG. 9 is a two-dimensional cross-sectional view showing a main process step of implementing the Finite Mechanical Device proposed by the present invention by introducing CMP (Chemical Mechanical Polishing).

In FIG. 9A, after forming the first oxide film 6 on the bulk silicon substrate 2b and performing nano patterning, silicon of the first oxide film 6 and the bulk silicon substrate 2b is etched.

The channel Fin, which is later connected to the bulk silicon substrate 2b, is formed like the Fin active region 4.

At this time, the thickness of the first oxide film 6 is between 0.5 nm and 200 nm, the height of the fin active region 4 is between 10 nm and 1000 nm, the width between 4 nm and 100 nm. Use the value of.

In FIG. 9B, the second oxide film 10 is formed in the structure formed in FIG. 9A with a thickness between 20 nm and 1000 nm, preferably between 20 nm and 800 nm, and is etched through CMP.

In FIG. 9C, the second oxide film 10 formed in FIG. 9B is etched to a thickness of between 10 nm and 300 nm.

As a result, the height of the Fin active region 4 protruding above the second oxide film 10 is between 5 nm and 300 nm.

In FIG. 9D, a cross section is shown in which the gate oxide film 12 is grown to a thickness between 0.5 nm and 10 nm in the formed Fin active region 4.

Before the gate oxide layer 12 is formed, the sacrificial oxide layer is grown and removed to clean the sidewalls of the protruding Fin active region 4 and to remove the damage by the previous process, and then anneal in nitrogen or argon atmosphere. It is preferable to carry out.

Subsequent subsequent processes form a layer of polysilicon (p + or n + doping) or SiGe (p + or n + doping) or metal as the gate material and implement the gate 16 through photolithography. do.

An oxide film is formed, an appropriate heat treatment process is performed, and an oxide film is deposited as necessary.

Then, photolithography is performed for the contact area 46.

A metal layer 48 to be electrically connected to the source / drain is deposited and metal wiring is formed by photo transfer.

FIG. 10 illustrates a main process step of implementing the mechanical mechanical polishing (CMP) as an example for implementing a body in which a channel of the FinFET device proposed in the present invention is formed.

In FIG. 10A, the first oxide film 6 and the nitride film 14 are formed in the bulk silicon substrate 2b and the fin active region 4, followed by nano patterning, followed by the first oxide film 6 and the nitride film 14. Silicon is etched.

The nitride film 14 is used as an etch stopper of the CMP, the thickness of which is between 10 nm and 200 nm.

The channel Fin, which is later connected to the bulk silicon substrate 2b, is formed like the Fin active region 4.

In this case, the thickness of the first oxide film 6 is between 0.5 nm and 200 nm, and the height of the Fin active region 4 is between 10 nm and 1000 nm.

In FIG. 10B, the second oxide film 10 is formed in the structure formed in FIG. 10A to a thickness between 20 nm and 1000 nm, preferably between 20 nm and 800 nm, and is etched through CMP.

In FIG. 10C, a cross section of the second oxide film 10 formed in FIG. 10B is etched to a thickness between 10 nm and 300 nm.

As a result, the height of the Fin active region 4 protruding above the second oxide film 10 is between 5 nm and 300 nm.

In FIG. 10D, a cross section is shown in which the gate oxide film 12 is grown to a thickness between 0.5 nm and 10 nm in the formed Fin active region 4.

The gate oxide film 12 may be grown after the nitride film 14 is removed.

Before the gate oxide layer 12 is formed, the sacrificial oxide layer is grown and removed to clean the sidewalls of the protruding Fin active region 4 and to remove the damage by the previous process, and then anneal in nitrogen or argon atmosphere. It is preferable to carry out.

Subsequent subsequent processes form a layer of polysilicon (p + or n + doping) or SiGe (p + or n + doping) or metal as the gate material and implement the gate 16 through photolithography. do.

An oxide film is formed, an appropriate heat treatment process is performed, and an oxide film is deposited as necessary.

Then, photolithography is performed for the contact area 46.

A metal layer 48 to be electrically connected to the source / drain is deposited and metal wiring is formed by photo transfer.

FIG. 11 is an example for implementing a body in which a channel of a FinFET device proposed in the present invention is formed, and illustrates a main process step of forming and implementing a fin channel by a selective epitaxial growth method.

In FIG. 11A, a second oxide film 10 having a thickness of 20 nm to 1000 nm is formed on the bulk silicon substrate 2b, and after the nano patterning is performed, the second oxide film 10 is etched.

The width of the etched second oxide film 10 is between 4 nm and 100 nm and the depth is between 10 nm and 1000 nm.

The fin active region 4 is formed by growing a selective epitaxial layer having a suitable height by using a selective epitaxial growth method as a seed of the silicon region of the bulk silicon substrate 2b exposed at the bottom of the etched oxide trench.

A first oxide film 6 between 0.5 nm and 200 nm is formed on the Fin active region 4, and a nitride film 14 between 10 nm and 200 nm is formed thereon.

When the nitride film 14 and the first oxide film 6 are etched by the thickness deposited through CMP or dry etching, a cross section as shown in FIG. 11B is shown.

In FIG. 11C, the second oxide film 10 is etched with a thickness between 10 nm and 300 nm.

As a result, the height of the Fin active region 4 protruding above the second oxide film 10 is between 5 nm and 300 nm.

FIG. 11D shows a cross section in which the gate oxide film 12 is grown in the formed Fin active region 4.

The gate oxide film 12 may be grown after the nitride film 14 is removed.

Before the gate oxide layer 12 is formed, the sacrificial oxide layer is grown and removed to clean the sidewalls of the protruding Fin active region 4 and to remove the damage by the previous process, and then anneal in nitrogen or argon atmosphere. It is preferable to carry out.

Subsequent subsequent processes are the same as the subsequent processes of FIG. 9D or 10D.

12 is an example for implementing a body in which a channel of a FinFET device proposed in the present invention is formed, and shows a main process step for implementing a desired final structure by growing a field oxide film 28 instead of using CMP. .

Here, the main process steps of the method of forming and implementing the spacer oxide layer 26 and the field oxide layer 28 are shown.

In FIG. 12A, after forming the Fin active region 4 by performing nanophotographic transfer, a first oxide film 6 having a thickness of 0.5 nm to 200 nm is formed and a nitride film having a thickness of 10 nm to 200 nm thereon. (14), and a third oxide film 20 having a thickness of between 5 nm and 500 nm is formed thereon.

When the silicon of the third oxide film 20, the nitride film 14, the first oxide film 6, and the bulk silicon substrate 2b is etched, the cross-sectional structure of FIG. 12A is obtained.

The height of the formed Fin active 4 region is to be a value between 10 nm and 1000 nm.

In this state, a thin buffer oxide film 22 is formed with a thickness between 1 nm and 50 nm, and an antioxidant nitride film 24 is formed thereon with a thickness between 5 nm and 100 nm.

When the spacer oxide film 26 is formed on it again with a thickness between 5 nm and 500 nm and anisotropic dry etching is performed, the oxide film 26 is formed in a space form.

Both surfaces and the top surface of the Fin active region 4 are surrounded by oxide films 6, 20, 22, 26 and nitride films 14, 24, and the other portions of the fin active region 4 are exposed to the silicon of the bulk silicon substrate 2b.

Isoetching the silicon of the bulk silicon substrate 2b to a thickness between 30 nm and 300 nm results in the cross-sectional structure of FIG. 12B.

Here, the oxide films 20, 22, and 26 are selectively etched as shown in FIG. 12C.

In this state, when the field oxide film 28 is grown to a thickness between 30 nm and 500 nm and the nitride films 14 and 24 are removed, the field oxide film 28 has a cross section as shown in FIG. 12D.

As a result, the height of the region Fin active region 4 protruding over the field oxide film 28 is between 5 nm and 300 nm.

FIG. 12D shows a cross section in which the gate oxide film 12 is grown in the formed Fin active region 4.

Before the gate oxide layer 12 is formed, the sacrificial oxide layer is grown and removed to clean the sidewalls of the protruding Fin active region 4 and to remove the damage by the previous process, and then anneal in nitrogen or argon atmosphere. It is preferable to carry out.

Subsequent subsequent processes are the same as the subsequent processes of FIGS. 9D, 10D, and 11D.

FIG. 13 is another example for implementing the body in which the channel of the FinFET device proposed in the present invention is formed. The main process of the method of implementing the spacer 30 and the field oxide film 28 is introduced. Looks steps.

Compared with FIG. 12, only materials constituting the spacer 30 are different.

In FIG. 13A, after forming the Fin active region 4 by performing nanophotographic transfer, a first oxide film 6 having a thickness of 0.5 nm to 200 nm is formed and a nitride film having a thickness of 10 nm to 200 nm thereon ( 14), and a third oxide film 20 having a thickness of between 5 nm and 500 nm is formed thereon.

When the silicon of the third oxide film 20, the nitride film 14, the first oxide film 6, and the bulk silicon substrate 2b is etched, the cross-sectional structure of FIG. 13A is obtained.

The height of the formed Fin active 4 region is to be a value between 10 nm and 1000 nm.

In this state, a thin buffer oxide film 22 is formed with a thickness between 1 nm and 20 nm, and an antioxidant nitride film 24 is formed thereon with a thickness between 5 nm and 50 nm.

The spacer 30 is formed on the thickness of 5 nm to 500 nm with polysilicon or amorphous silicon and then anisotropic dry etching.

This structure is shown in Fig. 13B, and the material of the spacer 30 of Fig. 13B and the spacer oxide film 26 of Fig. 12B is different.

In FIG. 13B, polysilicon or amorphous silicon is used as the spacer 30 material. In FIG. 12B, when the spacer oxide layer 26 is etched in FIG. 12B, the buffer oxide layer 22 under the antioxidant nitride layer 24 is etched. This is because it may adversely affect the growth of the field oxide film 28.

In addition, the polysilicon or amorphous silicon may be doped at a high concentration.

Isoetching silicon to a thickness between 30 nm and 300 nm to etch the spacer 30 and the bulk silicon substrate 2b revealed in FIG. 13B results in the cross-sectional structure of FIG. 13C.

In this state, when the field oxide film 28 is grown to a thickness between 30 nm and 500 nm and the nitride films 14 and 24 are removed, the field oxide film 28 has a cross section as shown in FIG. 13D.

As a result, the height of the region Fin active region 4 protruding over the field oxide film 28 is between 5 nm and 300 nm.

In FIG. 13D, a cross section in which the gate oxide film 12 is grown in the formed Fin active region 4 is shown.

Before the gate oxide layer 12 is formed, the sacrificial oxide layer is grown and removed to clean the sidewalls of the protruding Fin active region 4 and to remove the damage by the previous process, and then anneal in nitrogen or argon atmosphere. It is preferable to carry out.

Subsequent subsequent processes are the same as the subsequent processes of FIGS. 9D, 10D, 11D, and 12D.

As described above, according to the present invention, a parasitic resistance component can be reduced by forming an epitaxial layer on the source / drain by using a bulk wafer at low cost and self-aligning with the gate, and forming a fin active region as a silicon structure. In addition to being able to solve the floating body problem by being connected to the bulk wafer, the thermal conductivity of the device can be improved.

Claims (23)

  1. Bulk silicon substrates,
    A fence-like Fin active region connected to the bulk silicon substrate and formed of single crystal silicon in the center of the bulk silicon substrate;
    A second oxide film formed on the surface of the bulk silicon substrate to a predetermined height of the Fin active region;
    A gate oxide film formed on both sidewalls of the Fin active region on the second oxide film;
    A first oxide film formed on the upper surface of the Fin active region equal to or thicker than a gate oxide film;
    A gate formed on the first and second oxide films,
    Source / drain formed on both sides of the Fin active region except the Fin active region overlapping the gate;
    Contact regions and metal layers formed on the contact portions of the source, drain, and gate;
    A double-gate FNT device comprising a.
  2. The double-gate FFT device according to claim 1, wherein the Fin active region has a width of 4 nm to 100 nm.
  3. The double-gate FFT device according to claim 1 or 2, wherein the height of the Fin active region is 10 nm to 1000 nm from the surface of the bulk silicon substrate.
  4. 4. The double-gate FFT device according to claim 3, wherein the height of the Fin active region is 5 nm to 300 nm from the surface of the second oxide film.
  5. The double-gate FFT device according to claim 1, wherein the gate oxide film has a thickness of 0.5 nm to 10 nm, and the first oxide film has a thickness of 0.5 nm to 200 nm.
  6. The double-gate FFT device according to claim 1, wherein the parasitic capacitance component between the gate and the bulk silicon substrate is reduced by setting the thickness of the second oxide film to 20 nm to 800 nm.
  7. The double-gate FFT device according to claim 1, wherein the contact resistance is reduced by making the contact region in contact with the metal layer larger than the width or gate length of the Fin active region.
  8. The device of claim 1, wherein the source / drain is formed by growing a selective epitaxial layer formed on both sides of the fin active region except the fin active region overlapping the gate to reduce parasitic resistance in a gate and self-aligned form. .
  9. The method according to claim 8, wherein the selective epi layer,
    The oxide is wet oxidized while the gate is doped to 10 20 cm −3 or more, and the oxide oxide of the gate is larger than the Fin active region to partially etch the grown oxide layer, and the silicon exposed on the sidewall of the Fin active region is seeded. A double-gate FFT device, characterized in that the.
  10. The method according to claim 8, wherein the selective epi layer,
    An insulating film is deposited on the gate and anisotropically etched by the thickness of the insulating film and the height of the Fin active region protruding above the second oxide layer to seed the silicon and the gate polysilicon in the fin active region except for the region where the fin active region meets the gate. A double-gate FFT device, characterized in that the.
  11. 11. The double-gate FIFANT device of claim 8 wherein the material of the selective epi layer is at least one of monocrystalline silicon, single crystal SiGe, single crystal Ge, polysilicon, poly SiGe.
  12. The method of claim 1, wherein the junction depth of the doping for the source / drain formed in the Fin active region is 0 nm to 50 nm upwards when the upper surface of the second oxide film is a reference (0 nm). A double-gate FFT device.
  13. The method according to claim 1, characterized in that the junction depth of the doping for the source / drain formed in the Fin active region is 0 nm to -50 nm downward when the upper surface of the second oxide film is a reference (0 nm). A double-gate FFT device.
  14. The double-gate FFT device according to claim 1, wherein the width of the Fin active region becomes wider in the oxide film as it approaches the bulk silicon substrate, thereby reducing the resistance of the Fin active region.
  15. 2. The double-gate FFT device according to claim 1, wherein the Fin active region has a narrow upper width and a lower lower width.
  16. The double-gate FFT device of claim 1, wherein two upper edges of the Fin active region are rounded by an oxidation process, an etching process, or annealing in a hydrogen atmosphere.
  17. Forming a fence-like Fin active region with monocrystalline silicon on a bulk silicon substrate,
    Forming a second oxide film on a surface of the bulk silicon substrate up to a predetermined height of the Fin active region;
    Forming a gate oxide film on both sidewalls of the Fin active region formed over the second oxide film;
    Forming a first oxide film on the upper surface of the Fin active region equal to or thicker than a gate oxide film;
    Forming a gate on the first and second oxide films;
    Forming a source / drain on both fin active regions except the fin active region overlapping the gate;
    Forming a contact region and a metal layer in contact portions of the source, drain, and gate;
    A double-gate FNT device manufacturing method comprising the.
  18. The method of claim 17, wherein the Fin active region and the second oxide film forming step,
    Performing photolithography on a central upper portion of the bulk silicon substrate surface;
    Covering the second oxide film on the remaining surface of the bulk silicon substrate, except for the Fin active region, and planarizing the second oxide layer using CMP (Chemical Mechanical Polishing), and then etching down to the appropriate thickness from the surface of the Fin active region A method of manufacturing a double-gate FFT device, characterized by being a process.
  19. The method of claim 17, wherein the Fin active region and the second oxide film forming step,
    A second oxide film is first formed, and then a narrow trench is formed in the second oxide film through photolithography to reach the bottom of the trench to the bulk silicon substrate, and the silicon of the bulk silicon substrate exposed to the bottom of the trench is used as a seed. Process of growing a selective epi layer,
    And etching the second oxide film by an appropriate thickness.
  20. The method according to claim 17, wherein in the second oxide film forming process to form a field oxide film,
    In the Fin active region forming process, photo transfer is performed on the bulk silicon substrate, and a first oxide film / nitride film / third oxide film is sequentially formed on the bulk silicon substrate to form silicon in the third oxide film / nitride film / first oxide film and the bulk silicon substrate. Etching process,
    In the field oxide film forming process, a buffer oxide film / antioxidation nitride film / spacer is formed on the bulk silicon substrate and the fin active region to perform etching, and the silicon of the bulk silicon substrate is etched at this time, and the bulk is removed while the spacer is removed. A method of fabricating a double-gate FFT device, wherein the silicon substrate is thermally oxidized to grow a field oxide film and then the buffer oxide film and the antioxidant nitride film are removed.
  21. 21. The method of claim 20, wherein the spacer material is polysilicon or amorphous silicon.
  22. The method of claim 17, wherein before the gate oxide film is formed, the sacrificial oxide film is grown and removed to clean the sidewalls of the protruding Fin active regions and to remove damage caused by the previous process, and then, annealing is performed under nitrogen or argon atmosphere. A method of manufacturing a double-gate FFT device, characterized in that to perform.
  23. The method according to claim 17, wherein the gate forming step,
    A process for forming a layer from any one of polysilicon, poly SiGe, and metal and performing photo transfer on the layer.
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