KR100391559B1 - Non-volatile semiconductor memory device and method of manufacturing the same, volatile semiconductor memory device and method of manufacturing the same, and semiconductor memory device incorporating the non-volatile semiconductor memory device with the volatile semiconductor memory device and method of manufacturing thereof - Google Patents

Abstract

The present invention discloses a novel structure of a nonvolatile semiconductor memory device capable of storing a plurality of bits of information. The nonvolatile semiconductor memory device according to the present invention has a charge storage layer 4 for accumulating electrons at the ends of the gate electrodes. The nonvolatile semiconductor memory device according to the present invention stores electrons in the charge storage layer 4, thereby storing a plurality of bits of information.

Description

Nonvolatile semiconductor memory device and manufacturing method thereof, volatile semiconductor memory device and manufacturing method thereof, and nonvolatile semiconductor memory device and volatile semiconductor memory device in combination and manufacturing method thereof {NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME, VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR MEMORY DEVICE INCORPORATING THE NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH THE VOLATILE SEMICONDUCTOR MEMORY DEVOFACT AND METHOD AND METHOD

The present invention provides a nonvolatile semiconductor memory device and a method of manufacturing the same, which can be electrically recorded and erased, a volatile semiconductor memory device and a method of manufacturing the same, and a nonvolatile semiconductor memory device and a volatile semiconductor memory device are mixed on the same chip. A semiconductor memory device and a method of manufacturing the same.

In a nonvolatile memory such as a conventional EEPROM (Electrically Erasable and Programmable Read Only Memory), one bit of information is stored in one cell by realizing two different threshold values in one cell. On the other hand, in order to increase the memory density, a technique of having four or more threshold values in one cell and storing two or more bits of information in one cell has been proposed (M. Bauer et al., ISSCC95, p. 132). . However, in order to realize this technique, accurate control of the threshold voltage, accurate detection of small changes in the threshold voltage, and moreover, charge holding reliability beyond the prior art are required. Therefore, in this technique, it is not always possible to obtain the performance equivalent to the conventional one. This technique also has a problem of low production yield. For this reason, a cell structure for storing a plurality of bits of information by accumulating charge in a plurality of physically different positions has been newly proposed (B. Eitan et al. IEDM 96, p. 169, Fig. 6). In addition, as the cell structure similar thereto, a structure for providing a charge storage layer on the sidewall of the gate electrode has been proposed by the present inventor (US Pat. No. 4,881,108). However, the manufacturing process of these cell structures is very complicated and there is a problem that the controllability of the channel region is not sufficient.

On the other hand, there is a growing need to realize a nonvolatile memory that can be electrically written and erased and a volatile memory that can be read and read at a high speed on the same chip. In particular, there is an increasing demand for a VLSI in which a nonvolatile memory having a floating gate structure such as an EEPROM or a flash memory is mixed with a dynamic RAM capable of high speed operation. However, memory cells of recent dynamic RAMs have a very complicated three-dimensional structure called a trench structure or a static structure. For this reason, when mixed floating gate type nonvolatile memory and dynamic RAM are attempted, the manufacturing process is complicated by the difference in the memory cell structure, and the number of mask processes is also increased. Therefore, the manufacturing cost of the mixed chip is very high.

When the memory cell of the dynamic RAM is realized by using the memory cell structure of the floating gate type nonvolatile memory, the manufacturing process can be simplified by reducing the common cell structure, thereby reducing the manufacturing cost. However, in such a common memory cell, it is difficult to realize high-speed writing, which is a characteristic of the dynamic RAM.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a structure of a nonvolatile semiconductor memory device capable of storing a plurality of bits of information in a simple cell structure.

Another object of the present invention is to provide a method of manufacturing a nonvolatile semiconductor memory device for manufacturing a nonvolatile semiconductor memory device for storing a plurality of bits of information in a simple manufacturing process.

It is still another object of the present invention to provide a semiconductor memory device in which a nonvolatile memory that can be electrically written and erased and a volatile memory that can be read and read at high speed in a simple manufacturing process.

A further object of the present invention is to provide a method of manufacturing a semiconductor memory device in which a nonvolatile memory which can be electrically written and erased by a simple manufacturing process and a volatile memory that can be read and read at high speed.

1 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to a first embodiment of the present invention;

2A to 2C are cross-sectional views illustrating the operation of the nonvolatile semiconductor memory according to the first embodiment of the present invention;

3A to 3E are sectional views showing the manufacturing process of the memory cell of the nonvolatile semiconductor memory according to the first embodiment of the present invention;

4 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to a second embodiment of the present invention;

5A and 5B are cross-sectional views illustrating the operation of the nonvolatile semiconductor memory according to the second embodiment of the present invention;

6A to 6G are cross-sectional views illustrating a process for manufacturing a memory cell of a nonvolatile semiconductor memory according to the second embodiment of the present invention;

7 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to the fourth embodiment of the present invention;

8A and 8B are cross-sectional views illustrating the operation of the nonvolatile semiconductor memory according to the fourth embodiment of the present invention;

9 is a sectional view showing the structure of a MOS transistor constituting a peripheral circuit of a nonvolatile memory according to the fifth embodiment of the present invention;

10A to 10G are cross-sectional views illustrating a process of manufacturing the MOS transistor of FIG. 9;

11A is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory mounted in the semiconductor memory device according to the sixth embodiment of the present invention;

Fig. 11B is a sectional view showing the memory cell structure of a volatile semiconductor memory mounted in the semiconductor memory device according to the sixth embodiment of the present invention;

12A and 12B are cross-sectional views illustrating the operation of the nonvolatile semiconductor memory according to the sixth embodiment of the present invention;

13A to 13I are sectional views showing the manufacturing process of the memory cell of the nonvolatile semiconductor memory according to the sixth embodiment of the present invention;

14A to 14I are sectional views showing the manufacturing process of the memory cell of the volatile semiconductor memory according to the sixth embodiment of the present invention;

FIG. 15A is a cross-sectional view illustrating a memory cell structure of a nonvolatile semiconductor memory mounted in a semiconductor memory device according to the seventh embodiment of the present invention; FIG.

15B is a cross-sectional view showing a memory cell structure of a volatile semiconductor memory mounted in the semiconductor memory device according to the seventh embodiment of the present invention;

16A to 16I are sectional views showing the manufacturing process of the memory cell of the nonvolatile semiconductor memory according to the seventh embodiment of the present invention;

17A to 17I are sectional views showing the manufacturing process of the memory cell of the volatile semiconductor memory according to the seventh embodiment of the present invention;

18 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to the eighth embodiment of the present invention;

19A and 19B are cross-sectional views illustrating the operation of the nonvolatile semiconductor memory according to the eighth embodiment of the present invention;

20A to 20I are sectional views showing the manufacturing process of the memory cell of the nonvolatile semiconductor memory according to the eighth embodiment of the present invention;

21 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to the ninth embodiment of the present invention;

22A to 22F are sectional views showing the manufacturing process of the memory cell of the nonvolatile semiconductor memory according to the ninth embodiment of the present invention;

23 is a sectional view showing the memory cell structure of the nonvolatile semiconductor memory according to the tenth embodiment of the present invention;

24A and 24B are cross-sectional views illustrating the operation of the nonvolatile semiconductor memory according to the tenth embodiment of the present invention;

25A to 25I are sectional views showing the manufacturing process of the memory cell of the nonvolatile semiconductor memory according to the tenth embodiment of the present invention;

Fig. 26 is a sectional view showing the memory cell structure of the nonvolatile semiconductor memory according to the eleventh embodiment of the present invention;

27A to 27F are sectional views showing the manufacturing process of the memory cell of the nonvolatile semiconductor memory according to the eleventh embodiment of the present invention;

28 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to the twelfth embodiment of the present invention;

29A to 29I are sectional views showing the manufacturing process of the memory cell of the nonvolatile semiconductor memory according to the twelfth embodiment of the present invention;

30 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to the thirteenth embodiment of the present invention;

31A and 31B are cross-sectional views illustrating the operation of the nonvolatile semiconductor memory according to the thirteenth embodiment of the present invention constituted of an n-type MOS transistor;

32A and 32B are cross-sectional views illustrating the operation of the nonvolatile semiconductor memory according to the thirteenth embodiment of the present invention constituted of a p-type MOS transistor;

33 is a sectional view showing the structure of a MOS transistor having the same gate structure as that of the memory cell of the nonvolatile semiconductor memory according to the thirteenth embodiment of the present invention;

34 is a cross sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to a fourteenth embodiment of the present invention;

35 is a cross-sectional view showing the structure of a MOS transistor having the same gate structure as that of the memory cell of the nonvolatile semiconductor memory according to the fourteenth embodiment of the present invention.

In order to achieve the above object, a first aspect of the present invention provides a first gate electrode disposed on a main surface of a semiconductor substrate via a gate insulating film, and a charge storage layer and a first gate disposed on side surfaces of the first gate electrode. A nonvolatile semiconductor memory device includes at least a second gate electrode disposed on a side surface of an electrode via a charge storage layer and a conductive layer electrically connecting the first gate electrode and the second gate electrode.

According to a second aspect of the present invention, there is provided a gate insulating film comprising first, second and third insulating films disposed on a main surface of a semiconductor substrate, a charge storage layer disposed at an end of the second insulating film, and a gate insulating film. It is a nonvolatile semiconductor memory device having at least a gate electrode.

A third aspect of the present invention is a semiconductor memory device in which a nonvolatile semiconductor memory device and a volatile semiconductor memory device are mixed. The nonvolatile semiconductor memory device includes a first lower insulating film and a first lower insulating film disposed on a main surface of a semiconductor substrate. A first intermediate insulating film disposed on an upper portion of the center of the substrate, a first charge storage layer disposed on an end of the first lower insulating film, a first upper insulating film disposed on the first intermediate insulating film, and a first charge storage layer; A volatile semiconductor memory device comprising at least a first gate electrode disposed over the first upper insulating film, wherein the volatile semiconductor memory device comprises a second lower insulating film made of the same material as the first intermediate insulating film disposed on the main surface of the semiconductor substrate, and a main surface of the semiconductor substrate. An ultrathin insulating film disposed on both ends of the second lower insulating film and a second charge storage layer, a second lower insulating film, and a second charge made of the same material as the first charge storage layer disposed on the ultrathin insulating film; Accumulation layer The first and the second upper insulating film, a second gate electrode disposed on the second upper insulating film made of a first upper insulating film and arranged in the same material and provided with at least.

A fourth aspect of the present invention is a semiconductor memory device that includes a nonvolatile semiconductor memory device and a volatile semiconductor memory device. The nonvolatile semiconductor memory device includes a first lower insulating film and a first lower insulating film disposed on a main surface of a semiconductor substrate. A first intermediate insulating film disposed on an upper portion of the center of the substrate, a first charge storage layer disposed on an end of the first lower insulating film, a first upper insulating film disposed on the first intermediate insulating film, and a first charge storage layer; And at least a first gate electrode disposed over the first upper insulating film, wherein the volatile semiconductor memory device is made of the same material as the ultrathin insulating film disposed on the main surface of the semiconductor substrate and the first charge storage layer disposed on the ultrathin insulating film. And at least a second upper insulating film disposed on the second charge storage layer, and a second gate electrode disposed on the second upper insulating film.

A fifth aspect of the invention is the first, second and first portions disposed on the main surface of the semiconductor substrate including the iron portion or the recessed portion disposed on the main surface of the semiconductor substrate and the iron portion or the recessed portion. A nonvolatile semiconductor memory device includes at least a gate insulating film made of three insulating films, a charge storage layer disposed at an end of the second insulating film, and a gate electrode disposed on the gate insulating film.

A sixth aspect of the present invention is a gate insulating film comprising first and second insulating films disposed on a main surface of a semiconductor substrate including the iron portions or recesses and first and second insulating films disposed on the main surface of the semiconductor substrate. It is a nonvolatile semiconductor memory device having at least a charge storage layer disposed between two insulating films and a gate electrode disposed on the gate insulating film.

A seventh aspect of the invention includes at least a gate electrode disposed on a main surface of a semiconductor substrate via a gate insulating film, a recess disposed at an end of the gate electrode, and a charge storage layer disposed at an recess through an insulating film. The charge storage layer is a nonvolatile semiconductor memory device disposed above both the channel region and the source / drain region.

Embodiment

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings. In description of the following drawings, the same or similar code | symbol is attached | subjected to the same or similar part. It should be noted, however, that the drawings are schematic and that the relationship between thickness and planar dimension, the ratio of the thickness of each layer, and the like differ from those in reality. Therefore, specific thickness or dimension should be judged in consideration of the following description. Moreover, of course, the part from which the relationship and the ratio of a mutual dimension differ also in between drawings is contained.

First embodiment

1 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to the first embodiment of the present invention. This memory cell is composed of n-type MOS transistors. In the memory cell structure of the nonvolatile semiconductor memory according to the first embodiment of the present invention, the first gate electrode 3 is provided on the surface of the p-type semiconductor substrate 1 via the gate insulating film 2. Charge storage layers 4 (4a, 4b) are provided on both sides of the gate electrode 3. The charge storage layer 4 has a lamination structure, and the first layer is composed of the first oxide film 5, the second layer is formed of the nitride film 6, and the third layer is composed of the second oxide film 7. Further, the second gate electrode 8 is provided on the charge storage layer 4. A side wall spacer 9 is provided on the side of the charge storage layer 4, and a low impurity concentration n ⁻ type in contact with the channel region is provided on the p-type semiconductor substrate 1 below the side wall spacer 9. A diffusion layer 10 and an n ⁺ type diffusion layer 11 having a high impurity concentration located outside the n ⁻ type diffusion layer 10 are provided. A conductive layer 12 is provided on the surface of each of the first gate electrode 3, the charge storage layer 4, the second gate electrode 8, and the n ⁺ type diffusion layer 11. The first gate electrode 3 and the second gate electrode 8 are electrically connected via this conductive layer 12.

In the memory cell of the nonvolatile semiconductor memory according to the first embodiment of the present invention, an LDD comprising a source region and a drain region composed of an n ⁻ type diffusion layer 10 having a low impurity concentration and an n ⁺ type diffusion layer 11 having a high impurity concentration. (Lightly doped drain) structure. The charge accumulation layer 4 is formed on both sides of the first gate electrode 3, and the change in the threshold voltage caused by the presence or absence of electrons held in the nitride film 6 of the two charge accumulation layers 4. To "00", "01", "10", and "11" of the stored information. Furthermore, the second gate electrode 8 is formed on the charge storage layer 4, and the second gate electrode 8 is electrically connected to the first gate electrode 3, thereby controlling the controllability of the channel region. It makes it easy to detect a threshold voltage change.

Next, operations of the nonvolatile memory according to the first embodiment of the present invention will be described with reference to FIGS. 2A to 2C. 2A is a cross-sectional view of the nonvolatile memory for explaining the write operation. 2B is a cross-sectional view of the nonvolatile memory for explaining the read operation. 2C is a cross-sectional view of the nonvolatile memory for explaining the erase operation. As shown in Fig. 2A, at the time of writing the memory cell, a high voltage (˜10 V) is applied to the gate G, and at the same time, a high voltage (˜8 V) is applied to the drain D adjacent to the charge storage layer 4 b that accumulates electrons. ) And ground the non-proximate source (S). When a voltage is applied in this manner, channel hot electrons are generated, and the hot electrons are captured in the nitride film 6 of the charge storage layer 4b. When electrons are trapped in the charge storage layer 4b, the threshold voltage of the cell transistor changes. Reading of the memory cell is performed by detecting a change in the threshold voltage. Specifically, as shown in FIG. 2B, a voltage 5V is applied to the gate G, a voltage 3V is applied to the drain D at the same time, and a difference in the amount of current is detected by the sense amplifier. In the erase of the memory cell, as shown in FIG. 2C, a negative voltage (˜-6 V) is applied to the gate G, and a constant voltage (˜9 V) is applied to the drain D adjacent to the charge storage layer 4 b to be erased. It is applied by emitting electrons trapped in the charge storage layer 4b. On the other hand, as is well known, the source S and the drain D of the MOS transistor can be symmetrical, and in general, the source S and the drain D can be replaced. Therefore, also in the above description, it is possible to replace the source S and the drain D. FIG.

Next, a method of manufacturing a memory cell of a nonvolatile semiconductor memory according to the first embodiment of the present invention will be described with reference to FIGS. 3A to 3E. First, as shown in FIG. 3A, a 25 nm gate insulating film 2 is formed on the p-type semiconductor substrate 1 by thermal oxidation. Subsequently, a 300 nm polycrystalline silicon film doped with n-type or p-type impurities was deposited on the entire surface of the p-type semiconductor substrate 1 by LPCVD (Low Pressure Chemical Vapor Deposition), followed by well-known exposure and etching techniques. The first gate electrode 3 is formed by patterning.

Next, as shown in Fig. 3B, after removing the gate insulating film 2 on the surface of the p-type semiconductor substrate 1 in the region in which the source region and the drain region are formed, the p-type semiconductor substrate 1 is 900 deg. Thermal oxidation in an oxidation atmosphere at 1200 ° C. forms a first oxide film 5 of 10 nm. Then, a 10 nm to 100 nm nitride film 6 is deposited on the first oxide film 5 by LPCVD, and then about 5 nm on the surface of the nitride film 6 by 900 ° C hydrogen combustion oxidation or CVD. A second oxide film 7 is formed.

Next, as shown in FIG. 3C, polysilicon having a thickness of about 25 to 250 nm is deposited on the second oxide film 7, for example, by LPCVD, followed by anisotropic etching by RIE (Reactive Ion Etching). The charge storage layer 4 having the second gate electrode 8 thereon by removing the polysilicon film, the first oxide film 5, the nitride film 6 and the second oxide film 7 by their film thicknesses; 4a and 4b are formed on the side of the first gate electrode.

Next, as shown in FIG. 3D, an n ⁻ type diffusion layer 10 having a low impurity concentration is formed. The n ⁻ type diffusion layer 10 is formed by implanting n type impurities using the first gate electrode 3 and the charge storage layer 4 as a mask by ion implantation techniques, and activating the implanted impurities by subsequent heat treatment. do.

Next, as shown in FIG. 3E, after forming the sidewall spacers 9 on the sidewalls of the charge storage layer 4, the n ⁺ type diffusion layer 11 having a high impurity concentration is formed. The n ⁺ type diffusion layer 11 injects n-type impurities using the first gate electrode 3, the charge storage layer 4, and the sidewall spacers 9 as a mask by ion implantation technology, and then implants them by heat treatment thereafter. It is formed by activating one impurity.

Next, a high melting point metal film such as tungsten, titanium, or cobalt is deposited on the entire surface of the p-type semiconductor substrate 1 by CVD or sputtering, and then the p-type semiconductor substrate 1 is heat-treated in an inert atmosphere. A conductive layer 12 made of high melting point metal silicide is formed on the surface of each of the gate electrode 3, the charge accumulation layer 4, the second gate electrode 8 and the n ⁺ type diffusion layer 11. At this time, the first oxide film 5, the nitride film 6, the second oxide film 7, so that the high melting point metal silicide layers on the first gate electrode 3 and the second gate electrode 8 are bridged. In particular, the film thickness of the nitride film 6 needs to be set. After the formation of the conductive layer 12, the unreacted high melting point metal remaining in the regions other than the above is removed, thereby completing the memory cell structure shown in FIG.

On the other hand, although not shown, after completion of the memory cell structure of FIG. 1, a final CMOS manufacturing process such as an interlayer insulating film forming process, a contact hole forming process, a wiring forming process, and a passivation film forming process is sequentially performed. The nonvolatile memory cell is completed.

According to the first embodiment of the present invention, since the second gate electrode 8 is also provided on the charge storage layer 4, the controllability of the threshold voltage is improved. On the other hand, in the first embodiment of the present invention, the case where the memory cell is composed of the n-type MOS transistor has been described, but the same effect can be obtained even when the memory cell is composed of the P-type MOS transistor. In addition, although the memory cell has an LDD structure, it may be a single drain structure or a double drain structure.

Second embodiment

Next, a second embodiment of the present invention will be described. 4 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to the second embodiment of the present invention. This memory cell is composed of n-type MOS transistors. In the memory cell structure of the nonvolatile memory according to the second embodiment of the present invention, the second gate insulating film 14 is provided on the surface of the p-type semiconductor substrate 1 via the first gate insulating film 13. Charge storage layers 4a and 4b are formed at both ends of the second gate insulating film 14. The gate electrode 3 is provided on the second gate insulating film 14 and the charge storage layers 4a and 4b via the third gate insulating film 15. A sidewall spacer 9 is provided on the side of the gate electrode 3 via an oxide film 16, and a low impurity concentration n in contact with the channel region is provided on the p-type semiconductor substrate 1 below the sidewall spacer 9. ^The diffusion type diffusion layer 10 and the n ⁺ type diffusion layer 11 having a high impurity concentration located outside the n ⁻ type diffusion layer 10 are provided. The conductive layer 12 is provided on the surface of each of the gate electrode 3 and the n ⁺ type diffusion layer 11.

In the memory cell of the nonvolatile semiconductor memory according to the second embodiment of the present invention, an LDD comprising a source region and a drain region of an n ⁻ type diffusion layer 10 having a low impurity concentration and an n ⁺ type diffusion layer 11 having a high impurity concentration. I have a structure. The gate insulating film is composed of a three-layer laminated film including a first gate insulating film 13 (lower layer), a second gate insulating film 14 (intermediate layer), and a third gate insulating film 15 (upper layer), and the second gate insulating film 14 Charge storage layers 4a and 4b are formed at both ends of the " Electrons are accumulated in these two charge storage layers 4a and 4b, and the accumulation state is that (1) the charge storage layers 4a and 4b do not accumulate electrons. (2) The charge storage layers 4a. (4) four states: the state in which only electrons accumulate, (3) the state in which only the charge accumulation layer 4b accumulates electrons, and (4) the state in which the charge accumulation layers 4a and 4b all accumulate electrons. Can be taken. Changes in the threshold voltage caused by the presence or absence of electrons held in these two charge storage layers 4a and 4b correspond to " 00 "," 01 "," 10 " and " 11 " In this memory cell structure, since the charge storage layers 4a and 4b are located above the end of the channel region, the threshold voltage at the center of the channel region is determined only by the impurity concentration of the channel region. It does not depend on the accumulation state of electrons. Therefore, over-erase due to the lack of electrons in the charge storage layers 4a and 4b is prevented, and therefore, leakage failure, program failure, reading failure, etc. due to over-erasure cannot occur. In addition, the leakage current between the source region and the drain region can be suppressed only by the gate voltage, thereby achieving a highly reliable nonvolatile semiconductor memory. The charge accumulation layers 4a and 4b may be composed of silicon nitride films having high charge accumulation capability by the CVD method. This is because by accumulating electrons at the discrete charge trapping level of the silicon nitride film, it is possible to obtain charge holding characteristics that are hardly affected by the film quality of the lower insulating film. Moreover, if it comprises a silicon film and a polycrystalline silicon film, it can manufacture at low cost. Further, when the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon nitride film (Si ₃ N ₄ film) having a dielectric constant about twice that of the silicon oxide film (SiO ₂ film), a silicon oxide film conversion film A very thin gate insulating film having a thickness of about 4 nm to 11 nm can be stably realized. For example, since the actual thickness of the silicon nitride film having a silicon oxide film thickness of about 5 nm is about 10 nm, direct tunnel DT injection is not induced. Therefore, the voltage at the time of electron injection / extraction operation is lowered, so that not only the memory cell can be miniaturized but also the peripheral high voltage operating element can be miniaturized.

In the memory cell of the nonvolatile semiconductor memory according to the second embodiment of the present invention, the n ^- type diffusion layer 10 is provided for the purpose of improving the breakdown voltage of the source region and the drain region. The source region and the drain region may be configured in a double drain structure. The second gate insulating film 14 prevents leakage between the charge storage layers 4a-4b, and may be formed of, for example, a silicon oxide film. In addition, when a metal oxide film having a high dielectric constant is used for the second gate insulating film 14, the current transfer characteristic in the center of the channel region can be improved. Examples of the metal oxide film include TiO ₂ , Ta ₂ O ₅ , Al ₂ O ₅ , PZT, and SBT.

Next, operations of the nonvolatile memory according to the second embodiment of the present invention will be described with reference to FIGS. 5A and 5B. Fig. 5A is a sectional view of the nonvolatile memory for explaining the write operation. 5B is a cross-sectional view of the nonvolatile memory for explaining the erase operation. As shown in Fig. 5A, at the time of writing the memory cells, about 7 to 8V are applied to the gate G and about 5V to the drain D, respectively, and the source S is grounded. In this way, a voltage is applied and electrons are injected into the charge storage layer 4b on the drain region side by the channel thermal electrons CHE. When electrons are injected into the charge storage layer 4a on the source region side, the voltage applied to each of the drains D and S may be replaced with the above case. On the other hand, the memory cell is erased from the charge storage layers 4a and 4b by applying a negative voltage (˜-5V) to the gate G as shown in FIG. 5B and using a Fowler node-type (FN) tunnel current. By emitting electrons. When the gate electrode 3 is shared by a plurality of memory cells, electrons can be emitted from these memory cells at the same time. In this case, the source S and the drain D may be coincident with the p-type semiconductor substrate 1. If a constant voltage different from the potential of the p-type semiconductor substrate 1 is applied to the drain D, and the source S is floating, only the charge storage layer 4b on the drain D side is used. It is also possible to emit electrons. When electrons are emitted from only the charge storage layer 4a on the source S side, a constant voltage may be applied to the source S, and the drain D may be floating potential.

The memory cell can be written using the FN current, similarly to erasing the memory cell. About 10V is applied between the gate G and the p-type semiconductor substrate 1, and electrons are injected into the charge storage layers 4a and 4b with an FN current. In this case, electrons can be injected simultaneously into a plurality of memory cells with which the gate G is common.

Although not shown, reading of the memory cell is performed by detecting a read current flowing between the source S and the drain D. FIG. The current transfer characteristic (channel conductance) in the vicinity of the source region and the drain region is modulated in accordance with the accumulation state of the charge accumulation layers 4a and 4b. Which one of the source S and the drain D is biased may be selected in which the modulation of the current transfer characteristic is remarkable. Four different current transfer characteristics are obtained according to the four accumulation states of the charge accumulation layers 4a and 4b, thereby storing two bits of information in one cell.

Next, a method of manufacturing a memory cell of a nonvolatile semiconductor memory according to the second embodiment of the present invention will be described with reference to FIGS. 6A to 6G. First, as shown in FIG. 6A, a silicon nitride film having a small charge accumulation capability is deposited on the entire surface of the p-type semiconductor substrate 1 to form a first gate insulating film 13 of about 10 nm. The deposition of the silicon nitride film having a small charge accumulation capacity is performed by, for example, the Jet-Vapor-Deposition (JVD) method. Regarding the JVD method, for example, reference "T. P. Ma. IEEE Transactions on Electron Devices, Volume 45 Number 3, March 1998 p.680. After the first gate insulating film 13 is formed, a silicon oxide film is deposited by CVD to form a second gate insulating film 14 of about 5 to 10 nm. Subsequently, a silicon nitride film having a small charge accumulation capability is deposited by the JVD method to form a third gate insulating film 15 of about 10 nm.

Next, as shown in FIG. 6B, a 50-250 nm polysilicon film doped with n-type or p-type impurities by LPCVD is deposited on the entire surface of the p-type semiconductor substrate 1, followed by exposure and etching techniques. Patterned by to form the gate electrode (3). Subsequently, the first gate insulating film 13, the second gate insulating film 14, and the third gate of the surface of the p-type semiconductor substrate 1 in the region where the source and drain regions are formed using the gate electrode 3 as a mask. The insulating film 15 is dry etched by dry matching.

Next, as shown in Fig. 6C, a space 17 for forming a charge storage layer is formed. The space 17 is selectively formed at an end portion of the second gate insulating film 14 by using an etchant having a larger etching rate of the second gate insulating film 14 than the first gate insulating film 13 and the third gate insulating film 15. It is formed by wet etching (wet etching). In the second embodiment of the present invention, since the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon nitride film, and the second gate insulating film 14 is composed of a silicon oxide film, the etching solution is, for example, hydrofluoric acid. It is good to use a system. The space 17 for forming the charge storage layer may be formed by a plasma dry etching method using a gas containing HF gas instead of the wet etching method using an etching solution.

Next, as shown in FIG. 6D, the silicon nitride film 18 having high charge storage capability is deposited on the entire surface of the p-type semiconductor substrate 1 so as to completely fill the space 17 for forming the charge storage layer. . As shown in Fig. 6E, anisotropic etching is performed on the entire surface of the p-type semiconductor substrate 1 by RIE to form charge storage layers 4a and 4b made of silicon nitride films having high charge storage capability.

Next, as shown in FIG. 6F, after the oxide film 16 is formed over the entire surface of the p-type semiconductor substrate 1, the n ⁻ type diffusion layer 10 having a low impurity concentration is formed. The n ⁻ type diffusion layer 10 is formed by implanting n type impurities using the gate electrode 3 as a mask by ion implantation technology, and activating the implanted impurities by subsequent heat treatment.

Next, as shown in Fig. 6G, after forming the sidewall spacers 9 on the sidewalls of the gate electrodes 3, an n ⁺ type diffusion layer 11 having a high impurity concentration is formed. The n ⁺ type diffusion layer 11 is formed by implanting n-type impurities using the gate electrode 3 and the sidewall spacers 9 as a mask by ion implantation techniques, and activating the implanted impurities by subsequent heat treatment.

Next, a high melting point metal film such as tungsten, titanium or cobalt is deposited on the entire surface of the p-type semiconductor substrate 1 by CVD or sputtering, and then the p-type semiconductor substrate 1 is heat-treated in an inert atmosphere to form a gate electrode. A conductive layer 12 made of high melting point metal silicide is formed on the surface of each of (3) and n ⁺ type diffusion layer 11. After the formation of the conductive layer 12, the unreacted high melting point metal remaining in the region other than the above is removed, thereby completing the memory cell structure shown in FIG.

On the other hand, although not shown, after completion of the memory cell structure of FIG. 4, the nonvolatile memory cell is finally processed through a conventional CMOS manufacturing process such as an interlayer insulating film forming process, a contact hole forming process, a wiring forming process, and a passivation film forming process. This is done.

As described above, in the second embodiment of the present invention, the charge storage layers 4a and 4b can be formed in self-alignment under both ends of the gate electrode 3. Therefore, the gate length direction of the cell transistor can be made smaller. Accordingly, a large capacity, high density nonvolatile semiconductor memory can be provided. In addition, the cell area per bit is almost reduced by half compared with the conventional one, and a non-volatile semiconductor memory can be substantially reduced.

The width of the charge storage layers 4a and 4b in the channel length direction is used to control the etching rate difference and the etching time of the first gate insulating film 13, the third gate insulating film 15, and the second gate insulating film 14. It can be controlled easily. Thus, the charge storage layers 4a and 4b can be arranged symmetrically. Since the charge storage layers 4a and 4b are electrically separated completely by the second gate insulating film 14, the interaction between the charge storage layers 4a and 4b does not occur. Furthermore, the charge storage layers 4a and 4b are completely insulated from the source region, the drain region, the gate electrode 3 and the channel region by the first insulating film 13, the third insulating film 15 and the oxide film 16. In addition, it is possible to provide a nonvolatile semiconductor memory having excellent charge holding characteristics. The charge accumulation layers 4a and 4b extend from the end of the gate electrode 3 in the direction of the channel region, and the current of the memory cell depends on the charge accumulation state of the portion of the channel region side in the charge accumulation layers 4a and 4b. The transmission characteristics are almost determined. Therefore, when the length of the gate length direction of this portion is reduced to the limit, a finer nonvolatile semiconductor memory can be provided.

Moreover, since the cell structure can be easily realized by a conventional CMOS process, a nonvolatile semiconductor memory can be manufactured at low cost by using an existing manufacturing line.

Third embodiment

Next, a third embodiment of the present invention will be described. According to the third embodiment of the present invention, in the second embodiment shown in Fig. 4, the first gate insulating film 13 is made of silicon oxide film, the second gate insulating film 14 is made of silicon nitride film and the third gate insulating film 15. It is replaced with the silicon oxide film. Hereinafter, a method of manufacturing a memory cell of a nonvolatile semiconductor memory according to the third embodiment of the present invention will be described with reference to FIGS. 6A to 6C.

In the memory cell of the nonvolatile semiconductor memory according to the third embodiment of the present invention, first, the p-type semiconductor substrate 1 is thermally oxidized to form a first gate insulating film 13 of about 10 nm. After the formation of the first gate insulating film 13, a silicon nitride film having low charge storage capability by the JVD method is deposited to form a second gate insulating film 14 of about 5 to 10 nm. Subsequently, a silicon oxide film is deposited by CVD to form a third gate insulating film 15 of about 10 nm (see Fig. 6A).

Next, a polysilicon film of about 50 to 250 nm doped with n-type or p-type impurities is deposited on the entire surface of the p-type semiconductor substrate 1, and then patterned by exposure and etching techniques to form a gate electrode ( 3) form. Subsequently, the first gate insulating film 13, the second gate insulating film 14, and the third gate of the surface of the p-type semiconductor substrate 1 in the region where the source and drain regions are formed using the gate electrode 3 as a mask. The insulating film 15 is dry etched self-aligning (see FIG. 6B).

Next, the p-type semiconductor substrate 1 is thermally oxidized to form a thin silicon oxide film on the entire surface of the p-type semiconductor substrate 1. Thereafter, a space 17 for forming a charge storage layer is formed. The space 17 for forming a charge storage layer is formed by a second gate insulating film (ie, a first gate insulating film 13 and a third gate insulating film 15). It is formed by selectively wet etching the end portion of the second gate insulating film 14 using an etchant having a large etching rate. In the third embodiment of the present invention, since the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon oxide film, and the second gate insulating film 14 is composed of a silicon nitride film, the etching solution is, for example, phosphoric acid. It is good to use a system. Since the silicon nitride film 14 is hardly oxidized by the thermal oxidation process, an oxide film is not formed on the side surface of the second gate insulating film, so that the selectivity of etching is improved (see FIG. 6C). The space 17 for forming the charge storage layer may be formed by a plasma dry etching method using a gas containing CF ₄ gas instead of the wet etching method using an etching solution. The subsequent steps are the same as in the second embodiment.

Fourth Embodiment

Next, a fourth embodiment of the present invention will be described. 7 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to the fourth embodiment of the present invention. The fourth embodiment of the present invention is an example in which a memory cell is composed of a p-type MOS transistor. As shown in Fig. 7, in the memory cell structure of the nonvolatile memory according to the fourth embodiment of the present invention, the second gate insulating film 13 is formed on the surface of the n-type semiconductor substrate 19 via the first gate insulating film 13. 14) is installed. Charge storage layers 4a and 4b are formed at both ends of the second gate insulating film 14. The gate electrode 3 is provided on the second gate insulating film 14 and the charge storage layers 4a and 4b via the third gate insulating film 15. The sidewalls of the gate electrode 3 are provided with sidewall spacers 9 via an oxide film 16. The n-type semiconductor substrate 19 below the sidewall spacers 9 has a low impurity concentration in contact with the channel region. ^The diffusion type diffusion layer 20 and the p ⁺ type diffusion layer 21 having a high impurity concentration located outside the p ⁻ type diffusion layer 20 are provided. The conductive layer 12 is provided on the surface of each of the gate electrode 3 and the p ⁺ type diffusion layer 21.

Next, operations of the nonvolatile memory according to the fourth embodiment of the present invention will be described with reference to FIGS. 8A and 8B. 8A is a cross-sectional view of the nonvolatile memory for explaining the write operation. 8B is a cross-sectional view of the nonvolatile memory for explaining the erase operation. As shown in Fig. 8A, at the time of writing the memory cell, about 5V is applied to the gate G and about -5V to the drain D, respectively, and the source S is made a floating potential. In this way, a voltage is applied to supply electrons to the charge accumulation layer 4b on the drain region side by supplying energy to an electron near the drain region to electrons caused by the interband tunnel phenomenon. When electrons are injected into the charge storage layer 4a on the source region side, the voltage applied to each of the drains D and S may be changed from the above. On the other hand, the erasing of the memory cell is performed by applying a negative voltage (˜-5 V) to the gate G as shown in FIG. 8B and emitting electrons from the charge storage layers 4a and 4b using the FN current. When the gate G is shared by a plurality of memory cells, electrons can be emitted from these memory cells at the same time. In this case, the source S and the drain D are the n-type semiconductor substrate 19 and the coin or floating potential.

The memory cell can be written using channel column electrons as in the second embodiment of the present invention. In this case, about -2.5V is applied to the gate G and about -5V is applied to the drain D, respectively, and the source S is grounded. In this way, a voltage is applied, and electrons are injected into the charge storage layer 4b on the drain region side with channel thermal electrons. On the other hand, when electrons are injected into the charge storage layer 4a on the source region side, the voltages applied to each of the drains D and S may be replaced.

Although not shown, reading of the memory cell is performed by detecting a read current flowing between the source S and the drain D. FIG. The current transfer characteristic (channel conductance) in the vicinity of the source region and the drain region is modulated in accordance with the accumulation state of the charge accumulation layers 4a and 4b. Which one of the source S and the drain D is biased may be selected in which the modulation of the current transfer characteristic is remarkable. Four different current transfer characteristics are obtained according to the four accumulation states of the charge accumulation layers 4a and 4b, thereby storing two bits of information in one cell.

Fifth Embodiment

Next, a fifth embodiment of the present invention will be described. In general, in a semiconductor memory, peripheral circuits are arranged around a memory cell array. For example, the peripheral circuits include decoders, write / erase circuits, read circuits, analog circuits, various I / O circuits, and various capacitor circuits. In the fifth embodiment of the present invention, an example in which the MOS transistors constituting these peripheral circuits are simultaneously manufactured using the manufacturing steps of the memory cell transistors of the second to fourth embodiments is shown. 9 is a cross-sectional view showing the structure of a MOS transistor constituting a peripheral circuit of the nonvolatile semiconductor memory according to the fifth embodiment of the present invention. As shown in Fig. 9, according to the fifth embodiment of the present invention, seven kinds of MOS transistors Tr1 to Tr7 having different gate insulating films in addition to the memory cell transistors (memory cell Tr) can be realized. 9 is a memory cell transistor shown in FIG. In addition, the MOS transistors Tr1 to Tr7 all represent n-type MOS transistors. The n ⁻ type diffusion layer 10, the n ⁺ type diffusion layer 11, and the conductive layer 12 of the memory cell transistor are omitted for ease of view. The same applies to the MOS transistors Tr1 to Tr7.

Next, a method of manufacturing the MOS transistor shown in FIG. 9 will be described with reference to FIGS. 10A to 10G. First, as shown in FIG. 10A, a silicon nitride film having a small charge accumulation capability is deposited on the entire surface of the p-type semiconductor substrate 1 by the JVD method to form a first gate insulating film 13 of about 10 nm. After the first gate insulating film 13 is formed, the first gate insulating film 13 in a part of the region on the p-type semiconductor substrate 1 is removed by a known exposure technique and a dry etching technique. As shown in Fig. 10B, a silicon oxide film is deposited by CVD to form a second gate insulating film 14 of about 5 to 10 nm. After the second gate insulating film 14 is formed, the second gate insulating film 14 in a part of the region is removed by an exposure technique and a dry etching technique. Next, as shown in Fig. 10C, a silicon nitride film having a small charge accumulation capability is deposited by the JVD method to form a third gate insulating film 15 of about 10 nm. After the third gate insulating film 15 is formed, the third gate insulating film 15 in a part of the region is removed by an exposure technique and a dry etching technique. In this manner, seven types of gate insulating films including at least one of the first gate insulating film 13, the second gate insulating film 14, and the third gate insulating film 15 are realized.

Next, as shown in FIG. 10D, after depositing a polysilicon film of about 50 to 250 nm doped with n-type or p-type impurities by LPCVD on the entire surface of the p-type semiconductor substrate 1, an exposure technique and an etching technique Patterning is performed to form a plurality of gate electrodes 3. Further, the first gate insulating film 13 on the surface of the p-type semiconductor substrate 1 in the region where the source region and the drain region of each of the memory cell transistor and the MOS transistor are formed by dry etching using the gate electrode 3 as a mask. The second gate insulating film 14 and the third gate insulating film 15 are removed.

Next, as shown in Fig. 10E, the regions for forming the MOS transistors Tr1 to Tr7 are covered with photoresist, and the regions for forming the memory cell transistors are wet etched. As the etching solution, the etching rate of the second gate insulating film 14 is higher than that of the first gate insulating film 13 and the third gate insulating film 15. By wet etching, the end portion of the second gate insulating film 14 in the region where the memory cell transistor is formed is selectively etched to form a space 17 for forming a charge storage layer. In the fifth embodiment of the present invention, since the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon nitride film, and the second gate insulating film 14 is composed of a silicon oxide film, the etching solution is, for example, hydrofluoric acid. It is good to use a system. As shown in Fig. 10F, a silicon nitride film 18 having high charge storage capability is deposited on the entire surface of the p-type semiconductor substrate 1 so as to completely fill the space 17 for forming the charge storage layer. Next, as shown in FIG. 10G, charge storage layers 4a and 4b composed of silicon nitride films having high charge storage capability in regions where memory cell transistors are formed by performing anisotropic etching by RIE on the entire surface of the p-type semiconductor substrate 1. ). The subsequent steps are the same as in the second embodiment of the present invention.

According to the fifth embodiment of the present invention, seven kinds of MOS transistors Tr1 to Tr7 having gate insulating films having different film thicknesses can be manufactured simultaneously with the memory cell transistors. Accordingly, it is possible to provide a MOS transistor corresponding to various operating voltages, from a high voltage transistor having a high voltage operation to an ultra low voltage operating transistor. Furthermore, both n-type MOS transistors and p-type MOS transistors can be realized. In addition, the gate electrodes 3 of the memory cell transistors and the MOS transistors Tr1 to Tr7 are made of the same material and are formed by the same exposure process and dry etching process. Therefore, a fine transistor with little misalignment of the photomask can be provided.

Sixth embodiment

Next, a sixth embodiment of the present invention will be described. This sixth embodiment shows an example in which a nonvolatile memory that can be electrically written and erased and a volatile memory that can be written and read at high speed are realized on the same chip. FIG. 11A is a cross-sectional view illustrating a memory cell structure of a nonvolatile memory mounted in a semiconductor memory device according to a sixth embodiment of the present invention, and FIG. 11B is a cross-sectional view of a volatile memory mounted into a semiconductor memory device according to a sixth embodiment of the present invention. A cross-sectional view showing a memory cell structure. The nonvolatile memory of FIG. 11A and the volatile memory of FIG. 11B are mixed on the same chip.

(A) nonvolatile memory

As shown in Fig. 11A, the memory cell of the nonvolatile memory according to the sixth embodiment is composed of n-type MOS transistors. In the memory cell structure of the nonvolatile memory, the second gate insulating film 14 is provided on the surface of the p-type semiconductor substrate 1 via the first gate insulating film 13. Charge storage layers 4 (4a, 4b) are formed at both ends of the second gate insulating film 14. The gate electrode 3 is provided on the second gate insulating film 14 and the charge storage layer 4 via the third gate insulating film 15. Sidewall spacers 9 are provided on the side of the gate electrode 3 via an oxide film 16, and a low impurity concentration in contact with the channel region on the main surface of the p-type semiconductor substrate 1 below the sidewall spacers 9. The n ⁻ type diffusion layer 10 and the n ⁺ type diffusion layer 11 having a high impurity concentration located outside the n ⁻ type diffusion layer 10 are provided. The conductive layer 12 is provided on the surface of each of the gate electrode 3 and the n ⁺ type diffusion layer 11.

The memory cell of the nonvolatile memory according to the sixth embodiment of the present invention has an LDD structure in which a source region and a drain region are composed of an n ⁻ type diffusion layer 10 having a low impurity concentration and an n ⁺ type diffusion layer 11 having a high impurity concentration. Equipped with. The gate insulating film is composed of a three-layer laminated film including a first gate insulating film 13 (lower layer), a second gate insulating film 14 (intermediate layer), and a third gate insulating film 15 (upper layer), and the second gate insulating film 14 At both ends, the charge storage layers 4 (4a, 4b) are formed. Electrons are accumulated in these two charge storage layers 4a and 4b, and the accumulation state is that (1) the charge storage layers 4a and 4b do not accumulate electrons. (2) The charge storage layers 4a. (4) four states: the state in which only electrons accumulate, (3) the state in which only the charge accumulation layer 4b accumulates electrons, and (4) the state in which the charge accumulation layers 4a and 4b all accumulate electrons. Can be taken. Changes in the threshold voltage caused by the presence or absence of electrons held in these two charge storage layers 4a and 4b correspond to " 00 "," 01 "," 10 " and " 11 " In this memory cell structure, since the charge storage layer 4 is located above the end of the channel region, the threshold voltage at the center of the channel region is determined only by the impurity concentration of the channel region, and the accumulation state of electrons in the charge storage layer 4 is achieved. Does not depend on Therefore, over-erase due to the lack of electrons in the charge storage layer 4 is prevented, and therefore, leakage failure, program failure, reading failure, etc. due to over-erasure cannot occur. In addition, the leakage current between the source region and the drain region can be suppressed only by the gate voltage, thereby achieving a highly reliable nonvolatile memory. The charge accumulation layer 4 may be made of a silicon nitride film having a high charge accumulation capability by the CVD method. This is because by accumulating electrons at the discrete charge trapping level of the silicon nitride film, it is possible to obtain charge holding characteristics that are hardly affected by the film quality of the lower insulating film. Moreover, if it comprises a silicon film and a polycrystalline silicon film, it can manufacture at low cost. Further, when the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon nitride film (Si ₃ N ₄ film) having a dielectric constant about twice that of the silicon oxide film (SiO ₂ film), a silicon oxide film conversion film A very thin gate insulating film having a thickness of about 4 nm to 11 nm can be stably realized. For example, since the actual thickness of the silicon nitride film having a silicon oxide film thickness of about 5 nm is about 10 nm, direct tunnel DT injection is not induced. Therefore, the voltage at the time of electron injection / extraction operation is lowered, so that not only the memory cell can be miniaturized but also the peripheral high voltage operating element can be miniaturized.

In the memory cell of the nonvolatile memory according to the sixth embodiment of the present invention, although the n ⁻ type diffusion layer 10 is provided for the purpose of improving the breakdown voltage of the source region and the drain region, the LDD structure is formed. The drain region may be composed of a source region and a drain region. The second gate insulating film 14 prevents leakage between the charge storage layers 4a-4b, and may be formed of, for example, a silicon oxide film. In addition, when a metal oxide film having a high dielectric constant is used for the second gate insulating film 14, the current transfer characteristic in the center of the channel region can be improved. Examples of the metal oxide film include TiO ₂ , Ta ₂ O ₅ , Al ₂ O ₅ , PZT, and SBT.

Next, operations of the nonvolatile semiconductor memory according to the sixth embodiment of the present invention will be described with reference to FIGS. 12A and 12B. 12A is a sectional view of a nonvolatile memory for explaining a write operation. 12B is a sectional view of the nonvolatile memory for explaining the erase operation. As shown in Fig. 12A, at the time of writing the memory cell, about 7 to 8V is applied to the gate G and about 5V to the drain D, respectively, and the source S is grounded. In this way, a voltage is applied and electrons are injected into the charge storage layer 4b on the drain region side by the channel thermal electrons CHE. When electrons are injected into the charge storage layer 4a on the source region side, the voltage applied to each of the drains D and S may be changed from the above. On the other hand, the memory cell is erased from the charge storage layers 4a and 4b by applying a negative voltage (˜-5V) to the gate G as shown in FIG. 12B and using a Fowler node-type (FN) tunnel current. By emitting electrons. When the gate G is shared by a plurality of memory cells, electrons can be emitted from these memory cells at the same time. In this case, the source S and the drain D may be coincident with the p-type semiconductor substrate 1. When a constant voltage different from the potential of the p-type semiconductor substrate 1 is applied to the drain D, and the source S is a floating potential, electrons are emitted from only the charge storage layer 4b on the drain electrode side. It is also possible. When electrons are emitted from only the charge storage layer 4a on the source electrode side, it is sufficient to apply a constant voltage to the source electrode and set the drain electrode to the floating potential.

The memory cell can be written using the FN current, similarly to erasing the memory cell. About 10V is applied between the gate G and the p-type semiconductor substrate 1, and electrons are injected into the charge storage layers 4a and 4b with an FN current. In this case, electrons can be injected simultaneously into a plurality of memory cells with which the gate G is common.

Although not shown, reading of the memory cell is performed by detecting a read current flowing between the source S and the drain D. FIG. The current transfer characteristic (channel conductance) in the vicinity of the source region and the drain region is modulated in accordance with the accumulation state of the charge accumulation layers 4a and 4b. Which one of the source S and the drain D is biased may be selected in which the modulation of the current transfer characteristic is remarkable. Four different current transfer characteristics are obtained according to the four accumulation states of the charge accumulation layers 4a and 4b, thereby storing two bits of information in one cell.

(B) volatile memory

As shown in Fig. 11B, the memory cell of the volatile memory according to the sixth embodiment of the present invention is composed of n-type MOS transistors. In the memory cell structure of this nonvolatile memory, the second gate insulating film 14 of FIG. 11A is directly disposed on the main surface of the p-type semiconductor substrate 1. On both ends of the second gate insulating film 14, as in the nonvolatile memory of FIG. 11A, charge storage layers 4; 4c and 4d are formed, but these charge storage layers 4c and 4d are formed in the tunnel insulating film 23. The point of being disposed on the main surface of the p-type semiconductor substrate 1 by means of) is different from that of the nonvolatile memory of FIG. 11A. The gate electrode 3 is provided on the second gate insulating film 14 and the charge storage layer 4 via the third gate insulating film 15. Sidewall spacers 9 are provided on the side of the gate electrode 3 via an oxide film 16, and a low impurity concentration in contact with the channel region on the main surface of the p-type semiconductor substrate 1 below the sidewall spacers 9. The n ⁻ type diffusion layer 10 and the n ⁺ type diffusion layer 11 having a high impurity concentration located outside the n ⁻ type diffusion layer 10 are provided. The conductive layer 12 is provided on the surface of each of the gate electrode 3 and the n ⁺ type diffusion layer 11.

The memory cell of the volatile memory according to the sixth embodiment of the present invention has an LDD structure in which a source region and a drain region are composed of an n ⁻ type diffusion layer 10 having a low impurity concentration and an n ⁺ type diffusion layer 11 having a high impurity concentration. Equipped. The gate insulating film 14 includes the second gate insulating film 14, the tunnel insulating film 23, and the third gate insulating film 15, and charge storage layers 4c and 4d are formed at both ends of the second gate insulating film 14. do. Electrons are accumulated in these two charge storage layers 4c and 4d, and the accumulation state thereof is (1) the state in which the charge storage layers 4c and 4d do not both store electrons, and (2) the charge storage layer 4c. (4) four states: only the electrons accumulate, (3) only the charge accumulation layer 4d accumulates electrons, and (4) all the charge accumulation layers 4c and 4d accumulate electrons. Can be taken. The change in the threshold voltage caused by the presence or absence of electrons held in these two charge storage layers 4c and 4d corresponds to "00", "01", "10", and "11" of the stored information. In this memory cell structure, since the charge storage layer 4 is located above the end of the channel region, the threshold voltage at the center of the channel region is determined only by the impurity concentration of the channel region, and the accumulation state of electrons in the charge storage layer 4 is achieved. Does not depend on Therefore, over-erase due to the lack of electrons in the charge storage layer 4 is prevented, and therefore, leakage failure, program failure, reading failure, etc. due to over-erasure cannot occur. In addition, the leakage current between the source region and the drain region can be suppressed only by the gate voltage, thereby achieving a highly reliable nonvolatile memory. The charge accumulation layer 4 may be made of a silicon nitride film having a high charge accumulation capability by the CVD method. This is because by accumulating electrons at the discrete charge trapping level of the silicon nitride film, it is possible to obtain charge holding characteristics that are hardly affected by the film quality of the lower insulating film. Moreover, if it comprises a silicon film and a polycrystalline silicon film, it can manufacture at low cost. Further, when the third gate insulating film 15 is composed of a silicon nitride film (Si ₃ N ₄ film) having a dielectric constant about twice that of the silicon oxide film (SiO ₂ film), the silicon oxide film conversion film thickness is about 4 nm to 11 nm. The ultra-thin gate insulating film can be stably realized. For example, since the actual thickness of the silicon nitride film having a silicon oxide film thickness of about 5 nm is about 10 nm, direct tunnel DT injection is not induced. Therefore, the voltage at the time of electron injection / extraction operation is lowered, so that not only the memory cell can be miniaturized but also the peripheral high voltage operating element can be miniaturized.

In the memory cell of the volatile memory according to the sixth embodiment of the present invention, although the n ⁻ type diffusion layer 10 is provided for the purpose of improving the breakdown voltage of the source region and the drain region, the LDD structure is formed. The structure may include a source region and a drain region. The second gate insulating film 14 prevents leakage between the charge storage layers 4c-4d, and may be formed of, for example, a silicon oxide film. In addition, when a metal oxide film having a high dielectric constant is used for the second gate insulating film 14, the current transfer characteristic in the center of the channel region can be improved. Examples of the metal oxide film include TiO ₂ , Ta ₂ O ₅ , Al ₂ O ₅ , PZT, and SBT.

In the volatile memory according to the sixth embodiment of the present invention, the tunnel insulating film 23 is disposed under the charge storage layers 4c and 4d. The tunnel insulating film 23 is composed of a thin silicon oxide film having a directly tunnelable film thickness, and enables high speed recording and reading at 100 ns or less required for the dynamic RAM. When the tunnel insulating film 23 is made of a silicon oxide film, the film thickness may be 3 nm or less. When the silicon nitride film has a thickness of 3 nm or less, an extremely thin gate insulating film having a silicon oxide film conversion film thickness of about 1.5 nm can be stably realized. Since the electrons accumulated in the charge storage layer 4 gradually decrease due to the leakage current through the tunnel insulating film 23, it is difficult to actually maintain data for a long time. However, it is considered that there is no problem in operation as a normal dynamic RAM. This is C. H-J. Wann et al., 1995 IEDM digest p.867.

The reading of the memory cell is performed by detecting a read current flowing between the source electrode and the drain electrode. The current transfer characteristic (channel conductance) in the vicinity of the source region and the drain region is modulated in accordance with the accumulation state of the charge storage layers 4c and 4d. Which one of the source electrode and the drain electrode is biased may be selected in which the modulation of the current transfer characteristic is remarkable. Four different current transfer characteristics are obtained according to the four accumulation states of the charge storage layers 4c and 4d, thereby storing two bits of information in one cell.

Furthermore, the volatile memory according to the sixth embodiment of the present invention can be operated as a normal MOS transistor unless charge is injected into the charge storage layers 4c and 4d.

(C) Method of manufacturing nonvolatile and volatile memory

Next, a method of manufacturing a nonvolatile memory and a memory cell of a volatile memory according to the sixth embodiment of the present invention will be described with reference to FIGS. 13A to 13I and 14A to 14I. 13A to 13I are sectional views showing the manufacturing method of the nonvolatile memory according to the sixth embodiment of the present invention, and FIGS. 14A to 14I are sectional views showing the manufacturing method of the volatile memory according to the sixth embodiment of the present invention.

First, as shown in FIGS. 13A and 14A, a silicon nitride film having a small charge accumulation capability is deposited on the entire surface of the p-type semiconductor substrate 1 to form a first gate insulating film 13 of about 10 nm. After the formation of the first gate insulating film 13, the non-volatile memory formation region of FIG. 13A is covered with a photoresist, for example, and only the first gate insulation layer 13 of the volatile memory formation region of FIG. 14A is wet-etched using, for example, a heating phosphoric acid solution. Remove by Therefore, the first gate insulating film 13 is formed only in the nonvolatile memory formation region of FIG. 13A. The silicon nitride film with a small charge accumulation capacity is deposited by, for example, the JVD method.

13B and 14B, a silicon oxide film is deposited on the entire surface of the p-type semiconductor substrate 1 by CVD to form a second gate insulating film 14 of about 5 to 10 nm. Subsequently, a silicon nitride film having a small charge accumulation capability is deposited by the JVD method to form a third gate insulating film 15 of about 10 nm. As a result, the first, second, and third gate insulating layers 13, 14, and 15 are formed in the nonvolatile memory formation region of FIG. 13B, and the second and third gate insulation layers 14 are formed in the volatile memory formation region of FIG. 14B. 15) is formed.

Next, as shown in FIGS. 13C and 14C, a 50-250 nm polycrystalline silicon film doped with n-type or p-type impurities by LPCVD is deposited on the entire surface of the p-type semiconductor substrate 1, followed by exposure technique. And the gate electrode 3 is patterned by an etching technique. Subsequently, in the nonvolatile memory formation region of Fig. 13C, the first gate insulating film 13 and the first gate insulating film 13 on the surface of the p-type semiconductor substrate 1 are formed in the nonvolatile memory formation region of Fig. 13C. The two-gate insulating film 14 and the third gate insulating film 15 are dry etched in a self-aligned manner. On the other hand, in the volatile memory formation region of Fig. 14C, the second gate insulating film 14 and the third gate insulating film 15 are dry-etched in a self-aligned manner.

Next, as shown in FIGS. 13D and 14D, a space 17 for forming a charge storage layer is formed. The space 17 selectively selects an end portion of the second gate insulating film 14 by using an etchant having a higher etching rate of the second gate insulating film 14 than the first gate insulating film 13 and the third gate insulating film 15. It is formed by wet etching. A space 17 for forming a charge accumulation layer of the nonvolatile memory formation region of FIG. 13D and a space 17 for forming a charge accumulation layer of the volatile memory formation region of FIG. 14D are simultaneously formed. In the sixth embodiment of the present invention, since the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon nitride film, and the second gate insulating film 14 is composed of a silicon oxide film, the etching solution is, for example, hydrofluoric acid. It is good to use a system. The space 17 may be formed by a plasma dry etching method using a gas containing HF gas instead of the wet etching method using an etching solution.

Next, as shown in FIGS. 13E and 14E, the entire surface of the p-type semiconductor substrate 1 is oxidized by, for example, an RTO method to form a tunnel insulating film 23 made of a silicon oxide film that can be directly tunneled.

Next, as shown in FIGS. 13F and 14F, the space 17 for filling the silicon nitride film 18 having high charge storage capability by the LPCVD method on the entire surface of the p-type semiconductor substrate 1 is formed. Deposit as much as possible. 13G and 14G, anisotropic etching is performed on the entire surface of the p-type semiconductor substrate 1 by RIE to form charge storage layers 4 (4; 4a, 4b, 4c) composed of silicon nitride films having high charge storage capability. Simultaneously form 4d).

Next, as shown in FIGS. 13H and 14H, after the oxide film 16 is formed over the entire surface of the p-type semiconductor substrate 1, the n ⁻ type diffusion layer 10 having a low impurity concentration is formed. The n ⁻ type diffusion layer 10 is formed by implanting n type impurities using the gate electrode 3 as a mask by ion implantation technology, and activating the implanted impurities by subsequent heat treatment.

Next, as shown in Figs. 13I and 14I, after forming the sidewall spacers 9 on the sidewalls of the gate electrodes 3, an n ⁺ type diffusion layer 11 having a high impurity concentration is formed. The n ⁺ type diffusion layer 11 is formed by implanting n-type impurities using the gate electrode 3 and the sidewall spacers 9 as a mask by ion implantation techniques, and activating the implanted impurities by subsequent heat treatment.

Then, a high melting point metal film such as tungsten, titanium, cobalt, etc. is deposited on the entire surface of the p-type semiconductor substrate 1 by CVD or sputtering, and then the p-type semiconductor substrate 1 is heat-treated in an inert atmosphere. 3) and a conductive layer 12 composed of a high melting point metal silicide is formed on the surface of each of the n ⁺ type diffusion layer 11. After the formation of the conductive layer 12, the unreacted high melting point metal remaining in the regions other than the above is removed, thereby completing the memory cell structures of the nonvolatile memory shown in FIG. 11A and the volatile memory shown in FIG. 11B.

Although not shown, after completion of the memory cell structures shown in FIGS. 11A and 11B, the final process is performed after the normal CMOS manufacturing process such as the interlayer insulating film forming process, the contact hole forming process, the wiring forming process, and the passivation film forming process. A volatile memory and a semiconductor device having a volatile memory are completed.

As described above, in the sixth embodiment of the present invention, the charge storage layers 4 (4a, 4b, 4c, 4d) can be formed in self-alignment under the ends of the gate electrodes 3. Therefore, the gate length direction of the memory cell transistors of FIGS. 11A and 11B can be miniaturized. Accordingly, a large capacity, high density nonvolatile memory and volatile memory can be provided. In addition, the cell area per bit is almost reduced by half compared with the conventional one, and a non-volatile semiconductor memory can be substantially reduced.

The width of the charge storage layer 4 in the channel length direction is determined by the etching rate difference between the p-type semiconductor substrate 1, the first gate insulating film 13, the third gate insulating film 15, and the second gate insulating film 14. It can be controlled easily by adjusting the etching time. Thus, the charge storage layer 4 can be arranged symmetrically. Since the charge storage layers 4 are electrically separated completely by the second gate insulating film 14, the interaction between the charge storage layers 4 does not occur. In addition, the charge storage layer 4 includes the first insulating film 13, the tunnel insulating film 23, the third insulating film 15, and the oxide film 16 from the source region, the drain region, the gate electrode 3, and the channel region. Since it is completely insulated by, a nonvolatile memory and a volatile memory having excellent charge holding characteristics can be provided. The charge accumulation layer 4 is formed extending from the end of the gate electrode 3 toward the channel region, and substantially improves the current transfer characteristics of the memory cell in accordance with the charge accumulation state of the portion of the channel region side in the charge accumulation layer 4. Decide Therefore, when the length of the gate length direction of this portion is reduced to the limit, a finer nonvolatile memory and a volatile memory can be provided.

Since the cell structure can be easily realized by a conventional CMOS process, a nonvolatile memory and a volatile memory can be manufactured at low cost by using an existing manufacturing line.

In addition, since most of the manufacturing processes of the nonvolatile memory and the volatile memory are common, it is possible to manufacture a semiconductor device in which the nonvolatile memory and the volatile memory are mixed with low cost and short manufacturing air.

In the sixth embodiment of the present invention, the first gate insulating film 13 is formed of a silicon nitride film, the second gate insulating film 14 is formed of a silicon oxide film, and the third gate insulating film 15 is formed of a silicon nitride film. The gate insulating film 13 may be formed of a silicon oxide film, the second gate insulating film 14 may be formed of a silicon nitride film, and the third gate insulating film 15 may be formed of a silicon oxide film. In this case, for example, the first gate insulating film 13 is composed of a silicon oxide film of about 10 nm obtained by thermally oxidizing the p-type semiconductor substrate 1. The second gate insulating film 14 is composed of a silicon nitride film having a low charge accumulation capability of about 5 to 10 nm deposited by the JVD method. The third gate insulating film 15 may be made of a silicon oxide film of about 10 nm deposited by CVD. In the formation of the space 17 for forming the charge storage layer, the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon oxide film, and the second gate insulating film 14 is composed of a silicon nitride film. As the etching solution, for example, a phosphoric acid system may be used.

Seventh embodiment

Next, a seventh embodiment of the present invention will be described. This seventh embodiment shows an example of realizing, on the same chip, a nonvolatile memory that can be electrically written and erased and a volatile memory that can be written and read at high speed, similarly to the sixth embodiment. FIG. 15A is a cross-sectional view illustrating a memory cell structure of a nonvolatile memory mounted in a semiconductor memory device according to a seventh embodiment of the present invention. FIG. 15B illustrates a volatile memory mounted in a semiconductor memory device according to a seventh embodiment of the present invention. A cross-sectional view showing a memory cell structure. The nonvolatile memory of FIG. 15A and the volatile memory of FIG. 15B are mixed on the same chip. Since the nonvolatile memory shown in FIG. 15A is the same as in the sixth embodiment, the description thereof is omitted here.

As shown in Fig. 15B, the memory cell of the volatile memory according to the seventh embodiment is composed of n-type MOS transistors. In the memory cell structure of this volatile memory, the charge storage layer 4e is disposed on the main surface of the p-type semiconductor substrate 1 via the tunnel insulating film 23. The gate electrode 3 is provided on the charge storage layer 4e via the fourth gate insulating film 24. Sidewall spacers 9 are provided on the side of the gate electrode 3 via an oxide film 16, and a low impurity concentration in contact with the channel region on the main surface of the p-type semiconductor substrate 1 below the sidewall spacers 9. The n ⁻ type diffusion layer 10 and the n ⁺ type diffusion layer 11 having a high impurity concentration located outside the n ⁻ type diffusion layer 10 are provided. The conductive layer 12 is provided on the surface of each of the gate electrode 3 and the n ⁺ type diffusion layer 11.

The memory cell of the volatile memory according to the seventh embodiment of the present invention has an LDD structure in which a source region and a drain region are composed of an n ⁻ type diffusion layer 10 having a low impurity concentration and an n ⁺ type diffusion layer 11 having a high impurity concentration. Equipped. The gate insulating film has a laminated structure including the tunnel insulating film 23 and the fourth gate insulating film 24, and a charge storage layer 4e is disposed between the tunnel insulating film 23 and the fourth gate insulating film 24. . Electrons are accumulated in the charge accumulation layer 4e, and changes in the threshold voltage caused by the presence or absence of electrons held in the charge accumulation layer 4e correspond to "0" and "1" of the storage information. The charge accumulation layer 4e may be composed of a silicon nitride film having a high charge accumulation capability by the CVD method. This is because by accumulating electrons at the discrete charge trapping level of the silicon nitride film, it is possible to obtain charge holding characteristics that are hardly affected by the film quality of the lower insulating film. Moreover, if it comprises a silicon film and a polycrystalline silicon film, it can manufacture at low cost. Further, when the fourth gate insulating film 24 is composed of a silicon nitride film (Si ₃ N ₄ film) having a dielectric constant about twice that of the silicon oxide film (SiO ₂ film), the silicon oxide film conversion film thickness is about 4 nm to 11 nm. The ultra-thin gate insulating film can be stably realized. For example, since the actual thickness of the silicon nitride film having a silicon oxide film thickness of about 5 nm is about 10 nm, direct tunnel DT injection is not induced. Therefore, the voltage at the time of electron injection / extraction operation is lowered, so that not only the memory cell can be miniaturized but also the peripheral high voltage operating element can be miniaturized.

In the memory cell of the volatile memory according to the seventh embodiment of the present invention, although the n ⁻ type diffusion layer 10 is provided for the purpose of improving the breakdown voltage of the source region and the drain region, the LDD structure is formed. The structure may include a source region and a drain region.

In the volatile memory according to the seventh embodiment of the present invention, the tunnel insulating film 23 is disposed under the charge storage layer 4e. The tunnel insulating film 23 is composed of a thin silicon oxide film having a directly tunnelable film thickness, and enables recording and reading at a high speed of 100 ns or less required for the dynamic RAM. When the tunnel insulating film 23 is made of a silicon oxide film, the film thickness may be 3 nm or less. When the silicon nitride film has a thickness of 3 nm or less, an extremely thin tunnel insulating film 23 having a silicon oxide film conversion film thickness of about 1.5 nm can be stably realized.

Furthermore, the volatile memory according to the seventh embodiment of the present invention can also be operated as a normal MOS transistor unless charge is injected into the charge storage layer 4e.

Next, a method of manufacturing a nonvolatile memory and a memory cell of a volatile memory according to the seventh embodiment of the present invention will be described with reference to FIGS. 16A to 16H and 17A to 17H. 16A to 16H are cross-sectional views showing the manufacturing method of the nonvolatile memory according to the seventh embodiment of the present invention, and FIGS. 17A to 17H are cross-sectional views showing the manufacturing method of the volatile memory according to the seventh embodiment of the present invention.

First, as shown in FIGS. 16A and 17A, a silicon nitride film having a small charge accumulation capability is deposited on the entire surface of the p-type semiconductor substrate 1 to form a first gate insulating film 13 of about 10 nm. The deposition of the silicon nitride film having a small charge accumulation capacity is performed by, for example, the JVD method. After the first gate insulating film 13 is formed, a silicon oxide film is deposited by CVD to form a second gate insulating film 14 of about 5 to 10 nm. Subsequently, a silicon nitride film having a small charge accumulation capability is deposited by the JVD method to form a third gate insulating film 15 of about 10 nm.

Next, as shown in Figs. 16B and 17B, after depositing a polysilicon film of about 50 to 250 nm doped with n-type or p-type impurities by LPCVD on the entire surface of the p-type semiconductor substrate 1, Fig. 16B. In the nonvolatile memory formation region of the gate electrode 3, the gate electrode 3 is formed by patterning by exposure technique and etching technique. Subsequently, the first gate insulating film 13, the second gate insulating film 14, and the third gate of the surface of the p-type semiconductor substrate 1 in the region where the source and drain regions are formed using the gate electrode 3 as a mask. The insulating film 15 is dry-etched in self-alignment. In the volatile memory formation region of FIG. 17B, the polysilicon film, the first gate insulating film 13, the second gate insulating film 14, and the third gate insulating film 15 are all removed, and the surface of the p-type semiconductor substrate 1 is removed. Exposed.

Next, as shown in FIG. 16C, a space 17 for forming a charge storage layer is formed in the nonvolatile memory formation region. The space 17 for forming the charge storage layer is formed by using the etching solution having a larger etching rate of the second gate insulating film 14 than the first gate insulating film 13 and the third gate insulating film 15. The end of 14) is formed by selectively wet etching. In the seventh embodiment of the present invention, since the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon nitride film, and the second gate insulating film 14 is composed of a silicon oxide film, the etching solution is, for example, hydrofluoric acid. It is good to use a system. The space 17 for forming the charge storage layer may be formed by a plasma dry etching method using a gas containing HF gas instead of the wet etching method using an etching solution. 17C, the surface of the p-type semiconductor substrate 1 remains exposed in the volatile memory formation region.

Next, as shown in Figs. 16D and 17D, the entire surface of the p-type semiconductor substrate 1 is oxidized by, for example, the RTO method to form a tunnel insulating film 23 made of a silicon oxide film that can be directly tunneled. After the tunnel insulating film 23 is formed, a silicon nitride film 18 having high charge storage capability is deposited on the entire surface of the p-type semiconductor substrate 1 by the LPCVD method. At this time, the space 17 for forming the charge storage layer is completely filled by the silicon nitride film 18. As shown in FIG. 16E, in the nonvolatile memory formation region, anisotropic etching is performed on the entire surface of the p-type semiconductor substrate 1 by RIE to form a charge storage layer 4 composed of a silicon nitride film 18 having a high charge storage capability; 4a, 4b). At that time, the volatile memory formation region in Fig. 17E is covered with photoresist so that the silicon nitride film 18 is not etched.

After the etching of the silicon nitride film 18 is finished, a silicon oxide film is deposited on the entire surface of the p-type semiconductor substrate 1 to form a fourth gate insulating film 24. Here, the fourth gate insulating film 24 of the nonvolatile memory formation region of FIG. 16E is removed. The removal is performed by covering the volatile memory formation region of FIG. 17E with photoresist and etching the fourth gate insulating film 24 deposited in the nonvolatile memory formation region of FIG. 16E.

Next, as shown in FIG. 17F, a polysilicon film of about 50 to 250 nm doped with n-type or p-type impurities is deposited on the entire surface of the p-type semiconductor substrate 1 by the LPCVD method. Then, the polysilicon film is patterned by an exposure technique and an etching technique to form the gate electrode 3a. Subsequently, the tunnel insulating film 23, the charge storage layer 4e and the fourth gate insulating film on the surface of the p-type semiconductor substrate 1 in the region where the gate electrode 3a is used as an etching mask to form the source region and the drain region. 24) dry-etch self-aligned. On the other hand, in the nonvolatile memory formation region, as shown in Fig. 16F, all of the polysilicon films may be removed or may be patterned in accordance with the gate electrode 3 to form new gate electrodes.

Next, as shown in Figs. 16G and 17G, after the oxide film 16 is formed on the entire surface of the p-type semiconductor substrate 1, an n ⁻ type diffusion layer 10 having a low impurity concentration is formed. The n ⁻ type diffusion layer 10 is formed by implanting n type impurities using the gate electrode 3 as a mask by ion implantation technology, and activating the implanted impurities by subsequent heat treatment.

Next, as shown in Figs. 16H and 17H, after forming the sidewall spacers 9 on the sidewalls of the gate electrode 3, an n ⁺ type diffusion layer 11 having a high impurity concentration is formed. The n ⁺ type diffusion layer 11 is formed by implanting n-type impurities using the gate electrode 3 and the sidewall spacers 9 as a mask by ion implantation techniques, and activating the implanted impurities by subsequent heat treatment.

Next, a high melting point metal film such as tungsten, titanium or cobalt is deposited on the entire surface of the p-type semiconductor substrate 1 by CVD or sputtering, and then the p-type semiconductor substrate 1 is heat-treated in an inert atmosphere to form a gate electrode. A conductive layer 12 made of high melting point metal silicide is formed on the surface of each of (3) and n ⁺ type diffusion layer 11. After the conductive layer 12 is formed, the unreacted high melting point metal remaining in the regions other than the above is removed to complete the memory cell structures of the nonvolatile memory shown in FIG. 15A and the volatile memory shown in FIG. 15B.

Although not shown, after completion of the memory cell structures shown in FIGS. 15A and 15B, the final nonvolatile memory is sequentially processed through ordinary CMOS manufacturing processes such as an interlayer insulating film forming process, a contact hole forming process, a wiring forming process, and a passivation film forming process. And a volatile memory is completed.

In the seventh embodiment of the present invention, the first gate insulating film 13 is formed of a silicon nitride film, the second gate insulating film 14 is formed of a silicon oxide film, and the third gate insulating film 15 is formed of a silicon nitride film. (13) may be composed of a silicon oxide film, a second gate insulating film 14 of a silicon nitride film, and a third gate insulating film 15 of a silicon oxide film. In this case, for example, the first gate insulating film 13 is composed of a silicon oxide film of about 10 nm obtained by thermally oxidizing the p-type semiconductor substrate 1. The second gate insulating film 14 is composed of a silicon nitride film having a low charge accumulation capability of about 5 to 10 nm deposited by the JVD method. The third gate insulating film 15 may be made of a silicon oxide film of about 10 nm deposited by CVD. In the formation of the space 17 for forming the charge storage layer, the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon oxide film, and the second gate insulating film 14 is composed of a silicon nitride film. As the etching solution, for example, a phosphoric acid system may be used.

In the sixth and seventh embodiments of the present invention, an example in which the memory cells of the nonvolatile memory and the volatile memory are all composed of n-type MOS transistors has been described. However, the memory cells of the anti-conductive type p-type MOS transistors may be used. Of course. In this case, in the above description, the conductivity type of the substrate and the diffusion layer may be changed to the opposite one as appropriate.

8th Embodiment

Next, an eighth embodiment of the present invention will be described. In the above first to seventh embodiments, the structure of the charge accumulation layer does not directly contribute to the improvement of the electron injection efficiency. In a nonvolatile semiconductor memory having a floating gate structure, attempts have been made to improve electron injection efficiency by providing a step in a channel portion (S. Ogura, 1988 IDEM p.987, US Patent No. 5,780,341). . However, this proposal employs a floating gate structure, which is weak against defects and leakage sites in the oxide film. Moreover, also about the defect which may arise at the time of forming a stepped structure, there exists a possibility that sufficient reliability may not be obtained. In the eighth embodiment of the present invention, the electron injection efficiency can be improved by a simple process.

18 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to the eighth embodiment of the present invention. In the eighth embodiment, the step of providing a step and an inclination in the channel region of the memory cell improves the electron injection efficiency during recording. As shown in Fig. 18, this memory cell is composed of n-type MOS transistors. In the memory cell structure of the nonvolatile memory according to the eighth embodiment of the present invention, the second gate insulating film 14 is provided on the surface of the p-type semiconductor substrate 1 via the first gate insulating film 13. . Charge storage layers 4a and 4b are formed at both ends of the second gate insulating film 14. The gate electrode 3 is provided on the second gate insulating film 14 and the charge storage layers 4a and 4b via the third gate insulating film 15. A sidewall spacer 9 is provided on the side of the gate electrode 3 via an oxide film 16, and a low impurity concentration n in contact with the channel region is provided on the p-type semiconductor substrate 1 below the sidewall spacer 9. ^The diffusion type diffusion layer 10 and the n ⁺ type diffusion layer 11 having a high impurity concentration located outside the n ⁻ type diffusion layer 10 are provided. The conductive layer 12 is provided on the surface of each of the gate electrode 3 and the n ⁺ type diffusion layer 11.

Further, in the memory cell structure of the nonvolatile memory according to the eighth embodiment of the present invention, a step 26 is provided in the channel region 25. The step 26 causes the charge storage layer 4 to be positioned in the scattering direction of electrons in the p-type semiconductor substrate 1. Therefore, the electron injection efficiency at the time of recording is improved.

In the memory cell of the nonvolatile semiconductor memory according to the eighth embodiment of the present invention, an LDD comprising a source region and a drain region composed of an n ⁻ type diffusion layer 10 having a low impurity concentration and an n ⁺ type diffusion layer 11 having a high impurity concentration. I have a structure. The gate insulating film is composed of a three-layer laminated film including a first gate insulating film 13 (lower layer), a second gate insulating film 14 (intermediate layer), and a third gate insulating film 15 (upper layer), and the second gate insulating film 14 Charge storage layers 4a and 4b are formed at both ends of the " Electrons are accumulated in these two charge storage layers 4a and 4b, and the accumulation state is that (1) the charge storage layers 4a and 4b do not accumulate electrons. (2) The charge storage layers 4a. (4) four states: the state in which only electrons accumulate, (3) the state in which only the charge accumulation layer 4b accumulates electrons, and (4) the state in which the charge accumulation layers 4a and 4b all accumulate electrons. Can be taken. Changes in the threshold voltage caused by the presence or absence of electrons held in these two charge storage layers 4a and 4b correspond to " 00 "," 01 "," 10 " and " 11 " In this memory cell structure, since the charge storage layers 4a and 4b are located above the end of the channel region, the threshold voltage at the center of the channel region is determined only by the impurity concentration of the channel region. It does not depend on the accumulation state of electrons. Therefore, over-erasing due to the lack of electrons in the charge storage layers 4a and 4b is prevented, and accordingly, leakage failure, program failure, reading failure, etc. due to over-exposure cannot occur. In addition, the leakage current between the source region and the drain region can be suppressed only by the gate voltage, thereby achieving a highly reliable nonvolatile semiconductor memory. The charge accumulation layers 4a and 4b may be composed of silicon nitride films having high charge accumulation capability by the CVD method. This is because by accumulating electrons at the discrete charge trapping level of the silicon nitride film, it is possible to obtain charge holding characteristics that are hardly affected by the film quality of the lower insulating film. Moreover, if it comprises a silicon film and a polycrystalline silicon film, it can manufacture at low cost. Further, when the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon nitride film (Si ₃ N ₄ film) having a dielectric constant about twice that of the silicon oxide film (SiO ₂ film), a silicon oxide film conversion film A very thin gate insulating film having a thickness of about 4 nm to 11 nm can be stably realized. For example, since the actual thickness of the silicon nitride film having a silicon oxide film thickness of about 5 nm is about 10 nm, direct tunnel DT injection is not induced. Therefore, the voltage at the time of electron injection / extraction operation is lowered, so that not only the memory cell can be miniaturized but also the peripheral high voltage operating element can be miniaturized.

In the memory cell of the nonvolatile semiconductor memory according to the eighth embodiment of the present invention, the n ^- type diffusion layer 10 is provided for the purpose of improving the breakdown voltage of the source region and the drain region. The source region and the drain region may be configured in a double drain structure. The second gate insulating film 14 prevents leakage between the charge storage layers 4a-4b, and may be formed of, for example, a silicon oxide film. In addition, when a metal oxide film having a high dielectric constant is used for the second gate insulating film 14, the current transfer characteristic in the center of the channel region can be improved. Examples of the metal oxide film include TiO ₂ , Ta ₂ O ₅ , Al ₂ O ₅ , PZT, and SBT.

In the eighth embodiment of the present invention, the step 26 is provided on both the source side and the drain side, but either may be provided only on one side. In particular, only one side is sufficient in a memory that stores one bit of information.

Next, operations of the nonvolatile memory according to the eighth embodiment of the present invention will be described with reference to FIGS. 19A and 19B. 19A is a sectional view of a nonvolatile memory for explaining a write operation. 19B is a sectional view of the nonvolatile memory for explaining the erase operation. As shown in Fig. 19A, at the time of writing a memory cell, about 6 to 8 V is applied to the gate G and about 4 to 5 V to the drain D, respectively, and the source S is grounded. In this way, a voltage is applied and electrons are injected into the charge storage layer 4b on the drain region side by the channel thermal electrons CHE. By providing the step 26 in the channel region 25, the charge storage layer 4b is positioned in the scattering direction of the electrons. For this reason, the injection efficiency of the electron to the charge storage layer 4b is improved, and the injection speed can be increased and the applied voltage can be reduced. When electrons are injected into the charge storage layer 4a on the source region side, the voltage applied to each of the drains D and S may be replaced with the above case. On the other hand, erasing the memory cell is performed by applying a negative voltage (˜-5 V) to the gate G as shown in FIG. By emitting electrons. When the gate electrode 3 is shared by a plurality of memory cells, electrons can be emitted from these memory cells at the same time. In this case, the source S and the drain D may be coincident with the p-type semiconductor substrate 1. When a constant voltage different from the potential of the p-type semiconductor substrate 1 is applied to the drain D, and the source S is made a floating potential, electrons are drawn from only the charge accumulation layer 4b on the drain D side. It is also possible to emit. When electrons are emitted from only the charge storage layer 4a on the source S side, a constant voltage may be applied to the source S, and the drain D may be floating potential.

Although not shown, reading of the memory cell is performed by detecting a read current flowing between the source S and the drain D. FIG. The current transfer characteristic (channel conductance) in the vicinity of the source region and the drain region is modulated in accordance with the accumulation state of the charge accumulation layers 4a and 4b. Which one of the source S and the drain D is biased may be selected in which the modulation of the current transfer characteristic is remarkable. Four different current transfer characteristics are obtained according to the four accumulation states of the charge accumulation layers 4a and 4b, thereby storing two bits of information in one cell.

Next, a method of manufacturing a memory cell of a nonvolatile semiconductor memory according to an eighth embodiment of the present invention will be described with reference to FIGS. 20A to 20I. First, as shown in FIG. 20A, a photoresist pattern 27 covering the region where the channel region 25 is formed is formed on the p-type semiconductor substrate 1. As shown in FIG. 20B, the step 26 is formed by etching the p-type semiconductor substrate 1 by, for example, the RIE method.

Next, as shown in FIG. 20C, a silicon nitride film having a small charge accumulation capability is deposited on the entire surface of the p-type semiconductor substrate 1 to form a first gate insulating film 13 of about 10 nm. The deposition of the silicon nitride film having a small charge accumulation capacity is performed by, for example, the JVD method. After the first gate insulating film 13 is formed, a silicon oxide film is deposited by CVD to form a second gate insulating film 14 of about 5 to 10 nm. Subsequently, a silicon nitride film having a small charge accumulation capability is deposited by the JVD method to form a third gate insulating film 15 of about 10 nm.

Next, as shown in FIG. 20D, a 50-250 nm polycrystalline silicon film doped with n-type or p-type impurities by LPCVD is deposited on the entire surface of the p-type semiconductor substrate 1, followed by exposure and etching techniques. Patterned by to form the gate electrode (3). Subsequently, the first gate insulating film 13, the second gate insulating film 14, and the third gate of the surface of the p-type semiconductor substrate 1 in the region where the source and drain regions are formed using the gate electrode 3 as a mask. The insulating film 15 is dry-etched in self-alignment.

Next, as shown in Fig. 20E, a space 17 for forming a charge storage layer is formed. The space 17 is selectively formed at an end portion of the second gate insulating film 14 by using an etchant having a larger etching rate of the second gate insulating film 14 than the first gate insulating film 13 and the third gate insulating film 15. It forms by wet etching. In the eighth embodiment of the present invention, since the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon nitride film, and the second gate insulating film 14 is composed of a silicon oxide film, the etching solution is, for example, hydrofluoric acid. It is good to use a system. The space 17 for forming the charge storage layer may be formed by a plasma dry etching method using a gas containing HF gas instead of the wet etching method using an etching solution.

Next, as shown in FIG. 20F, a silicon nitride film 18 having high charge storage capability is deposited on the entire surface of the p-type semiconductor substrate 1 so as to completely fill the space 17 for forming the charge storage layer. . As shown in Fig. 20G, anisotropic etching is performed on the entire surface of the p-type semiconductor substrate 1 by RIE to form charge storage layers 4a and 4b made of silicon nitride film having high charge storage capability.

Next, as shown in FIG. 20H, after the oxide film 16 is formed over the entire surface of the p-type semiconductor substrate 1, the n ⁻ type diffusion layer 10 having a low impurity concentration is formed. The n ⁻ type diffusion layer 10 is formed by implanting n type impurities using the gate electrode 3 as a mask by ion implantation technology, and activating the implanted impurities by subsequent heat treatment.

Next, as shown in FIG. 20I, after forming the sidewall spacers 9 on the sidewalls of the gate electrodes 3, an n ⁺ type diffusion layer 11 having a high impurity concentration is formed. The n ⁺ type diffusion layer 11 is formed by implanting n-type impurities using the gate electrode 3 and the sidewall spacers 9 as a mask by ion implantation techniques, and activating the implanted impurities by subsequent heat treatment.

Next, a high melting point metal film such as tungsten, titanium or cobalt is deposited on the entire surface of the p-type semiconductor substrate 1 by CVD or sputtering, and then the p-type semiconductor substrate 1 is heat-treated in an inert atmosphere to form a gate electrode. A conductive layer 12 made of high melting point metal silicide is formed on the surface of each of (3) and n ⁺ type diffusion layer 11. After the formation of the conductive layer 12, when the unreacted high melting point metal remaining in the region other than the above is removed, the memory cell structure shown in Fig. 18 is completed.

On the other hand, although not shown, after completion of the memory cell structure shown in FIG. This is done.

As described above, in the eighth embodiment of the present invention, the charge storage layers 4a and 4b can be formed in self-alignment under both ends of the gate electrode 3. Therefore, the gate length direction of the cell transistor can be made smaller. Accordingly, a large capacity, high density nonvolatile semiconductor memory can be provided. In addition, the cell area per bit is almost reduced by half compared with the conventional one, and a non-volatile semiconductor memory can be substantially reduced.

The width of the charge storage layers 4a and 4b in the channel length direction is used to control the etching rate difference and the etching time of the first gate insulating film 13, the third gate insulating film 15, and the second gate insulating film 14. It can be controlled easily. Thus, the charge storage layers 4a and 4b can be arranged symmetrically. Since the charge storage layers 4a and 4b are completely electrically separated by the second gate insulating film 14, the interaction between the charge storage layers 4a and 4b does not occur. Further, the charge storage layers 4a and 4b are completely insulated from the source region, the drain region, the gate electrode 3 and the channel region by the first insulating film 13, the third insulating film 15 and the oxide film 16. Therefore, it is possible to provide a nonvolatile semiconductor memory having excellent charge holding characteristics. The charge accumulation layers 4a and 4b extend from the end of the gate electrode 3 in the direction of the channel region, and the current of the memory cell depends on the charge accumulation state of the portion of the channel region side in the charge accumulation layers 4a and 4b. The transmission characteristics are almost determined. Therefore, when the length of the gate length direction of this portion is reduced to the limit, a finer nonvolatile semiconductor memory can be provided.

Moreover, since the cell structure can be easily realized by a conventional CMOS process, a nonvolatile semiconductor memory can be manufactured at low cost by using an existing manufacturing line.

In the eighth embodiment of the present invention, the electron injection efficiency at the time of recording can be improved. For this reason, the recording speed can be increased and the applied voltage at the time of recording can be reduced.

9th Embodiment

Next, a ninth embodiment of the present invention will be described. In the ninth embodiment of the present invention, in the eighth embodiment, the second insulating film 14 disposed between the charge storage layer 4a and the charge storage layer 4b in FIG. The structure which integrated the two charge storage layers 4a and 4b is employ | adopted. 21 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to the ninth embodiment of the present invention. As shown in Fig. 21, the memory cell structure is such that the charge storage layer 4f is disposed in place of the charge storage layers 4a and 4b and the second insulating film 14 of the eighth embodiment.

Next, a method of manufacturing a memory cell of a nonvolatile memory according to the ninth embodiment of the present invention will be described with reference to FIGS. 22A to 22F. As in the eighth embodiment, first, as shown in FIG. 22A, a photoresist pattern 27 covering the region where the channel region 25 is formed is formed on the p-type semiconductor substrate 1. As shown in Fig. 22B, the step 26 is formed by etching the p-type semiconductor substrate 1 by, for example, the RIE method.

Next, as shown in FIG. 22C, a silicon nitride film having a small charge accumulation capability is deposited on the entire surface of the p-type semiconductor substrate 1 to form a first gate insulating film 13 of about 10 nm. The deposition of the silicon nitride film having a small charge accumulation capacity is performed by, for example, the JVD method. After the first gate insulating film 13 is formed, a silicon nitride film 18 having a high charge storage capability is formed by about 5 to 10 nm by the LPCVD method. Subsequently, a silicon nitride film having a small charge accumulation capability is deposited by the JVD method to form a third gate insulating film 15 of about 10 nm.

Next, as shown in FIG. 22D, after depositing a polysilicon film of about 50 to 250 nm doped with n-type or p-type impurities by LPCVD on the entire surface of the p-type semiconductor substrate 1, an exposure technique and an etching technique Patterned by to form the gate electrode (3). Subsequently, the first gate insulating film 13, the silicon nitride film 18, and the third gate insulating film of the surface of the p-type semiconductor substrate 1 in the region where the source electrode and the drain region are formed using the gate electrode 3 as a mask are formed. Dry-etch 15) self-aligned. Here, the charge storage layer 4f is formed.

Next, as shown in FIG. 22E, after the oxide film 16 is formed over the entire surface of the p-type semiconductor substrate 1, the n ⁻ type diffusion layer 10 having a low impurity concentration is formed. The n ⁻ type diffusion layer 10 is formed by implanting n type impurities using the gate electrode 3 as a mask by ion implantation technology, and activating the implanted impurities by subsequent heat treatment.

Next, as shown in Fig. 22F, after forming the sidewall spacers 9 on the sidewalls of the gate electrodes 3, an n ⁺ type diffusion layer 11 having a high impurity concentration is formed. The n ⁺ type diffusion layer 11 is formed by implanting n-type impurities using the gate electrode 3 and the sidewall spacers 9 as a mask by ion implantation techniques, and activating the implanted impurities by subsequent heat treatment.

Next, a high melting point metal film such as tungsten, titanium or cobalt is deposited on the entire surface of the p-type semiconductor substrate 1 by CVD or sputtering, and then the p-type semiconductor substrate 1 is heat-treated in an inert atmosphere to form a gate electrode. A conductive layer 12 made of high melting point metal silicide is formed on the surface of each of (3) and n ⁺ type diffusion layer 11. After the formation of the conductive layer 12, the unreacted high melting point metal remaining in the regions other than the above is removed, thereby completing the memory cell structure shown in FIG.

On the other hand, although not shown in the drawing, after completion of the memory cell structure shown in FIG. This is done.

Tenth Embodiment

Next, a tenth embodiment of the present invention will be described. Fig. 23 is a sectional view showing the memory cell structure of the nonvolatile semiconductor memory according to the tenth embodiment of the present invention. In the eighth and ninth embodiments, steps are provided at both ends of the channel region by making the channel region iron with respect to the semiconductor substrate. In this tenth embodiment, however, the channel region is formed relative to the semiconductor substrate. In this state, steps are provided in the channel region. This tenth embodiment also aims to improve the electron injection efficiency at the time of writing by providing a step or a slope in the channel region of the memory cell.

As shown in Fig. 23, this memory cell is composed of a p-type MOS transistor. In the structure of the memory cell according to the tenth embodiment, the second gate insulating film 14 is provided on the surface of the n-type semiconductor substrate 19 via the first gate insulating film 13. Charge storage layers 4a and 4b are formed at both ends of the second gate insulating film 14. The gate electrode 3 is provided on the second gate insulating film 14 and the charge storage layers 4a and 4b via the third gate insulating film 15. The sidewalls of the gate electrode 3 are provided with sidewall spacers 9 via an oxide film 16. The n-type semiconductor substrate 19 below the sidewall spacers 9 has a low impurity concentration in contact with the channel region. ^The diffusion type diffusion layer 20 and the p ⁺ type diffusion layer 21 having a high impurity concentration located outside the p ⁻ type diffusion layer 20 are provided. The conductive layer 12 is provided on the surface of each of the gate electrode 3 and the p ⁺ type diffusion layer 21.

Further, in the memory cell structure of the nonvolatile semiconductor memory according to the tenth embodiment of the present invention, a step 26 is provided in the channel region 25. The step 26 causes the charge storage layer 4 to be positioned in the scattering direction of electrons in the p-type semiconductor substrate 1. Therefore, the electron injection efficiency at the time of recording is improved.

In the memory cell of the nonvolatile semiconductor memory according to the tenth embodiment of the present invention, an LDD including a source region and a drain region as a p ⁻ type diffusion layer 20 having a low impurity concentration and a p ⁺ type diffusion layer 21 having a high impurity concentration. I have a structure. The gate insulating film is composed of a three-layer laminated film including a first gate insulating film 13 (lower layer), a second gate insulating film 14 (intermediate layer), and a third gate insulating film 15 (upper layer), and the second gate insulating film 14 Charge accumulation layers 4a and 4b are formed at both ends of the " Electrons are accumulated in these two charge storage layers 4a and 4b, and the accumulation state is that (1) the charge storage layers 4a and 4b do not accumulate electrons. (2) The charge storage layers 4a. (4) four states: the state in which only electrons accumulate, (3) the state in which only the charge accumulation layer 4b accumulates electrons, and (4) the state in which the charge accumulation layers 4a and 4b all accumulate electrons. Can be taken. Changes in the threshold voltage caused by the presence or absence of electrons held in these two charge storage layers 4a and 4b correspond to " 00 "," 01 "," 10 " and " 11 " In this memory cell structure, since the charge storage layers 4a and 4b are located above the end of the channel region, the threshold voltage at the center of the channel region is determined only by the impurity concentration of the channel region. It does not depend on the accumulation state of electrons. Therefore, overexposure due to the lack of electrons in the charge storage layers 4a and 4b is prevented, and therefore, leakage failure, program failure, reading failure, and the like due to overerasure cannot occur. In addition, the leakage current between the source region and the drain region can be suppressed only by the gate voltage, thereby achieving a highly reliable nonvolatile semiconductor memory. The charge accumulation layers 4a and 4b may be composed of silicon nitride films having high charge accumulation capability by the CVD method. This is because by accumulating electrons at the discrete charge trapping level of the silicon nitride film, it is possible to obtain charge holding characteristics that are hardly affected by the film quality of the lower insulating film. Moreover, if it comprises a silicon film and a polycrystalline silicon film, it can manufacture at low cost. Further, when the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon nitride film (Si ₃ N ₄ film) having a dielectric constant about twice that of the silicon oxide film (SiO ₂ film), a silicon oxide film conversion film A very thin gate insulating film having a thickness of about 4 nm to 11 nm can be stably realized. For example, since the actual thickness of the silicon nitride film having a silicon oxide film thickness of about 5 nm is about 10 nm, direct tunnel DT injection is not induced. Therefore, the voltage at the time of electron injection / extraction operation is lowered, so that not only the memory cell can be miniaturized but also the peripheral high voltage operating element can be miniaturized.

In the memory cell of the nonvolatile semiconductor memory according to the tenth embodiment of the present invention, the p ^- type diffusion layer 20 is provided for the purpose of improving the breakdown voltage of the source region and the drain region. The source region and the drain region may be configured in a double drain structure. The second gate insulating film 14 prevents leakage between the charge storage layers 4a-4b, and may be formed of, for example, a silicon oxide film. In addition, when a metal oxide film having a high dielectric constant is used for the second gate insulating film 14, the current transfer characteristic in the center of the channel region can be improved. Examples of the metal oxide film include TiO ₂ , Ta ₂ O ₅ , Al ₂ O ₅ , PZT, and SBT.

In the tenth embodiment of the present invention, the step 26 is provided on both the source side and the drain side, but either may be provided only on one side. In particular, only one side is sufficient in a memory that stores one bit of information.

Next, operations of the nonvolatile memory according to the tenth embodiment of the present invention will be described with reference to FIGS. 24A and 24B. 24A is a sectional view of a nonvolatile memory for explaining a write operation. 24B is a cross-sectional view of the nonvolatile memory for explaining the erase operation. As shown in FIG. 24A, at the time of writing the memory cell, about 5V is applied to the gate G and about -5V to the drain D, respectively, and the source S is made a floating potential. In this way, a voltage is applied, and energy is supplied to the electrons caused by the interband tunnel phenomenon by an electric field near the drain and injected into the charge storage layer 4b on the drain region side. By providing the step 26 in the channel region 25, the charge storage layer 4b is positioned in the electron injection direction. For this reason, the injection efficiency of the electron to the charge storage layer 4b is improved, and the injection speed can be increased and the applied voltage can be reduced. When electrons are injected into the charge storage layer 4a on the source region side, the voltage applied to each of the drains D and S may be replaced with the above case. On the other hand, erasing of the memory cells is performed by applying a negative voltage (˜-5 V) to the gate G as shown in FIG. By emitting electrons. When the gate electrode 3 is shared by a plurality of memory cells, electrons can be emitted from these memory cells at the same time. In this case, the source S and the drain D may be coincident with the p-type semiconductor substrate 1. When a constant voltage different from the potential of the p-type semiconductor substrate 1 is applied to the drain D, and the source S is made a floating potential, electrons are drawn from only the charge accumulation layer 4b on the drain D side. It is also possible to emit. When electrons are emitted from only the charge storage layer 4a on the source S side, a constant voltage may be applied to the source S, and the drain D may be floating potential.

Although not shown, reading of the memory cell is performed by detecting a read current flowing between the source S and the drain D. FIG. The current transfer characteristic (channel conductance) in the vicinity of the source region and the drain region is modulated in accordance with the accumulation state of the charge accumulation layers 4a and 4b. Which one of the source S and the drain D is biased may be selected in which the modulation of the current transfer characteristic is remarkable. Four different current transfer characteristics are obtained according to the four accumulation states of the charge accumulation layers 4a and 4b, thereby storing two bits of information in one cell.

Next, a method of manufacturing a memory cell of a nonvolatile semiconductor memory according to the tenth embodiment of the present invention will be described with reference to FIGS. 25A to 25I. First, as shown in FIG. 25A, a photoresist pattern 27 is formed on the n-type semiconductor substrate 19 to cover other than the region where the channel region 25 is formed. As shown in Fig. 25B, the step 26 is formed by etching the n-type semiconductor substrate 19 by, for example, the RIE method.

Next, as shown in FIG. 25C, a silicon nitride film having a small charge storage capability is deposited on the entire surface of the n-type semiconductor substrate 19 to form a first gate insulating film 13 of about 10 nm. The deposition of the silicon nitride film having a small charge accumulation capacity is performed by, for example, the JVD method. After the first gate insulating film 13 is formed, a silicon oxide film is deposited by CVD to form a second gate insulating film 14 of about 5 to 10 nm. Subsequently, a silicon nitride film having a small charge accumulation capability is deposited by the JVD method to form a third gate insulating film 15 of about 10 nm.

Next, as shown in FIG. 25D, a 50-250 nm polycrystalline silicon film doped with n-type or p-type impurities by LPCVD is deposited on the entire surface of the n-type semiconductor substrate 19, followed by an exposure technique and an etching technique. Patterned by to form the gate electrode (3). Next, the first gate insulating film 13, the second gate insulating film 14, and the third gate of the surface of the n-type semiconductor substrate 19 in the region where the source electrode and the drain region are formed using the gate electrode 3 as a mask. The insulating film 15 is dry-etched in self-alignment.

Next, as shown in Fig. 25E, a space 17 for forming a charge storage layer is formed. The space 17 is selectively formed at an end portion of the second gate insulating film 14 by using an etchant having a larger etching rate of the second gate insulating film 14 than the first gate insulating film 13 and the third gate insulating film 15. It forms by wet etching. In the tenth embodiment of the present invention, since the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon nitride film, and the second gate insulating film 14 is composed of a silicon oxide film, the etching solution is, for example, hydrofluoric acid. It is good to use a system. The space 17 for forming the charge storage layer may be formed by a plasma dry etching method using a gas containing HF gas instead of the wet etching method using an etching solution.

Next, as shown in FIG. 25F, a silicon nitride film 18 having high charge storage capability is deposited on the entire surface of the n-type semiconductor substrate 19 so as to completely fill the space 17 for forming the charge storage layer. . As shown in Fig. 25G, anisotropic etching is performed on the entire surface of the n-type semiconductor substrate 19 by RIE to form charge storage layers 4a and 4b made of silicon nitride films having high charge storage capability.

Next, as shown in FIG. 25H, after the oxide film 16 is formed over the entire surface of the n-type semiconductor substrate 19, a p ⁻ type diffusion layer 20 having a low impurity concentration is formed. The p ⁻ type diffusion layer 20 is formed by implanting p type impurities using the gate electrode 3 as a mask by ion implantation technology and activating the implanted impurities by subsequent heat treatment.

Next, as shown in FIG. 25I, after forming the sidewall spacer 9 on the sidewall of the gate electrode 3, the p ⁺ type diffusion layer 21 having a high impurity concentration is formed. The p ⁺ type diffusion layer 21 is formed by implanting p-type impurities using the gate electrode 3 and the sidewall spacers 9 as a mask by ion implantation techniques, and activating the implanted impurities by subsequent heat treatment.

Next, a high melting point metal film such as tungsten, titanium or cobalt is deposited on the entire surface of the n-type semiconductor substrate 19 by CVD or sputtering, and then the n-type semiconductor substrate 19 is heat-treated in an inert atmosphere to form a gate electrode. A conductive layer 12 made of high melting point metal silicide is formed on the surface of each of (3) and p ⁺ type diffusion layer 21. After the formation of the conductive layer 12, when the unreacted high melting point metal remaining in the region other than the above is removed, the memory cell structure shown in Fig. 23 is completed.

On the other hand, although not shown, after completion of the memory cell structure shown in FIG. This is done.

As described above, in the tenth embodiment of the present invention, the charge storage layers 4a and 4b can be formed in self-alignment under both ends of the gate electrode 3. Therefore, the gate length direction of the cell transistor can be made smaller. Accordingly, a large capacity, high density nonvolatile semiconductor memory can be provided. In addition, the cell area per bit is almost reduced by half compared with the conventional one, and a non-volatile semiconductor memory can be substantially reduced.

The width of the charge storage layers 4a and 4b in the channel length direction is used to control the etching rate difference and the etching time of the first gate insulating film 13, the third gate insulating film 15, and the second gate insulating film 14. It can be controlled easily. Thus, the charge storage layers 4a and 4b can be arranged symmetrically. Since the charge storage layers 4a and 4b are completely electrically separated by the second gate insulating film 14, the interaction between the charge storage layers 4a and 4b does not occur. Further, the charge storage layers 4a and 4b are completely insulated from the source region, the drain region, the gate electrode 3 and the channel region by the first insulating film 13, the third insulating film 15 and the oxide film 16. Therefore, it is possible to provide a nonvolatile semiconductor memory having excellent charge holding characteristics. The charge accumulation layers 4a and 4b extend from the end of the gate electrode 3 in the direction of the channel region, and the current of the memory cell depends on the charge accumulation state of the portion of the channel region side in the charge accumulation layers 4a and 4b. The transmission characteristics are almost determined. Therefore, when the length of the gate length direction of this portion is reduced to the limit, a finer nonvolatile semiconductor memory can be provided.

Moreover, since the cell structure can be easily realized by a conventional CMOS process, a nonvolatile semiconductor memory can be manufactured at low cost by using an existing manufacturing line.

In the tenth embodiment of the present invention, the electron injection efficiency at the time of recording can be improved. For this reason, the recording speed can be increased and the applied voltage at the time of recording can be reduced.

Eleventh Embodiment

Next, an eleventh embodiment of the present invention will be described. In the eleventh embodiment of the present invention, in the tenth embodiment, the second insulating film 14 disposed between the charge storage layer 4a and the charge storage layer 4b of FIG. The structure which integrated the two charge storage layers 4a and 4b is employ | adopted. Fig. 26 is a sectional view showing the memory cell structure of the nonvolatile semiconductor memory according to the eleventh embodiment of the present invention. As shown in Fig. 26, the memory cell structure has a charge storage layer 4f instead of the charge storage layers 4a and 4b and the second insulating film 14 of the tenth embodiment.

Next, a method of manufacturing a memory cell of a nonvolatile memory according to the eleventh embodiment of the present invention will be described with reference to FIGS. 27A to 27F. As in the tenth embodiment, first, as shown in Fig. 27A, a photoresist pattern 27 is formed on the n-type semiconductor substrate 19 to cover other than the region where the channel region 25 is formed. 27B, the step 26 is formed by etching the n-type semiconductor substrate 19 by, for example, the RIE method.

Next, as shown in FIG. 27C, a silicon nitride film having a small charge accumulation capability is deposited on the entire surface of the n-type semiconductor substrate 19 to form a first gate insulating film 13 of about 10 nm. The deposition of the silicon nitride film having a small charge accumulation capacity is performed by, for example, the JVD method. After the first gate insulating film 13 is formed, a silicon nitride film 18 having a high charge storage capability is formed by about 5 to 10 nm by the LPCVD method. Subsequently, a silicon nitride film having a small charge accumulation capability is deposited by the JVD method to form a third gate insulating film 15 of about 10 nm.

Next, as shown in FIG. 27D, a 50-250 nm polycrystalline silicon film doped with n-type or p-type impurities is deposited on the entire surface of the n-type semiconductor substrate 19 by LPCVD, followed by an exposure technique and an etching technique. Patterned by to form the gate electrode (3). Subsequently, the first gate insulating film 13, the silicon nitride film 18, and the third gate insulating film on the surface of the n-type semiconductor substrate 19 in the region where the source electrode and the drain region are formed using the gate electrode 3 as a mask are formed. Dry-etch 15) self-aligned. Here, the charge storage layer 4f is formed.

Next, as shown in FIG. 27E, after the oxide film 16 is formed over the entire surface of the n-type semiconductor substrate 19, a p ⁻ type diffusion layer 20 having a low impurity concentration is formed. The p ⁻ type diffusion layer 20 is formed by implanting p type impurities using the gate electrode 3 as a mask by ion implantation technology and activating the implanted impurities by subsequent heat treatment.

Next, as shown in FIG. 27F, the sidewall spacers 9 are formed on the sidewalls of the gate electrode 3, and then a p ⁺ type diffusion layer 21 having a high impurity concentration is formed. The p ⁺ type diffusion layer 21 is formed by implanting p-type impurities using the gate electrode 3 and the sidewall spacers 9 as a mask by ion implantation techniques, and activating the implanted impurities by subsequent heat treatment.

Next, a high melting point metal film such as tungsten, titanium or cobalt is deposited on the entire surface of the n-type semiconductor substrate 19 by CVD or sputtering, and then the n-type semiconductor substrate 19 is heat-treated in an inert atmosphere to form a gate electrode. A conductive layer 12 made of high melting point metal silicide is formed on the surface of each of (3) and p ⁺ type diffusion layer 21. After the formation of the conductive layer 12, the unreacted high melting point metal remaining in the regions other than the above is removed, thereby completing the memory cell structure shown in FIG.

On the other hand, although not shown, after completion of the memory cell structure shown in FIG. This is done.

12th Embodiment

Next, a twelfth embodiment of the present invention will be described. Fig. 28 is a sectional view showing the memory cell structure of the nonvolatile semiconductor memory according to the twelfth embodiment of the present invention. In the tenth embodiment, an exposure technique and an etching technique are used for patterning the gate electrode 3, but in the twelfth embodiment, a chemical mechanical polishing method is used for the patterning of the gate electrode 3.

Next, a method of manufacturing a memory cell of a nonvolatile memory according to the twelfth embodiment of the present invention will be described with reference to FIGS. 29A to 29I. First, as shown in FIG. 29A, a photoresist pattern 27 is formed on the n-type semiconductor substrate 19 to cover other than the region where the channel region 25 is formed. As shown in Fig. 29B, the step 26 is formed by etching the n-type semiconductor substrate 19 by, for example, the RIE method.

Next, as shown in FIG. 29C, a silicon nitride film having a small charge storage capability is deposited on the entire surface of the n-type semiconductor substrate 19 to form a first gate insulating film 13 of about 10 nm. The deposition of the silicon nitride film having a small charge accumulation capacity is performed by, for example, the JVD method. After the first gate insulating film 13 is formed, a silicon oxide film is deposited by CVD to form a second gate insulating film 14 of about 5 to 10 nm. Subsequently, a silicon nitride film having a small charge accumulation capability is deposited by the JVD method to form a third gate insulating film 15 of about 10 nm. Further, a polysilicon film 28 of about 50 to 500 nm doped with n-type or p-type impurities is deposited on the entire surface of the n-type semiconductor substrate 19 by LPCVD.

Next, as shown in FIG. 29D, the gate electrode 3 is formed by embedding the polysilicon film 28 by chemical mechanical polishing. At this time, the first gate insulating film 13, the second gate insulating film 14, and the third gate insulating film 15 remaining on the n-type semiconductor substrate 19 are normally removed by wet etching.

Next, as shown in FIG. 29E, a space 17 for forming a charge storage layer is formed. The space 17 is selectively formed at an end portion of the second gate insulating film 14 by using an etchant having a larger etching rate of the second gate insulating film 14 than the first gate insulating film 13 and the third gate insulating film 15. It forms by wet etching. In the twelfth embodiment of the present invention, since the first gate insulating film 13 and the third gate insulating film 15 are composed of a silicon nitride film, and the second gate insulating film 14 is composed of a silicon oxide film, the etching solution is, for example, hydrofluoric acid. It is good to use a system. The space 17 for forming the charge storage layer may be formed by a plasma dry etching method using a gas containing HF gas instead of the wet etching method using an etching solution.

Next, as shown in FIG. 29F, the silicon nitride film 18 having high charge storage capability is deposited on the entire surface of the n-type semiconductor substrate 19 so as to completely fill the space 17 for forming the charge storage layer. . As shown in FIG. 29G, anisotropic etching is performed on the entire surface of the n-type semiconductor substrate 19 by RIE to form charge storage layers 4a and 4b made of silicon nitride film having high charge storage capability.

Next, as shown in FIG. 29H, after the oxide film 16 is formed over the entire surface of the n-type semiconductor substrate 19, a p ⁻ type diffusion layer 20 having a low impurity concentration is formed. The p ⁻ type diffusion layer 20 is formed by implanting p type impurities using the gate electrode 3 as a mask by ion implantation technology and activating the implanted impurities by subsequent heat treatment.

Next, as shown in FIG. 29I, the sidewall spacers 9 are formed on the sidewalls of the gate electrode 3, and then a p ⁺ type diffusion layer 21 having a high impurity concentration is formed. The p ⁺ type diffusion layer 21 is formed by implanting p-type impurities using the gate electrode 3 and the sidewall spacers 9 as a mask by ion implantation techniques, and activating the implanted impurities by subsequent heat treatment.

Next, a high melting point metal film such as tungsten, titanium or cobalt is deposited on the entire surface of the n-type semiconductor substrate 19 by CVD or sputtering, and then the n-type semiconductor substrate 19 is heat-treated in an inert atmosphere to form a gate electrode. A conductive layer 12 made of high melting point metal silicide is formed on the surface of each of (3) and p ⁺ type diffusion layer 21. After the formation of the conductive layer 12, the unreacted high melting point metal remaining in the regions other than the above is removed, thereby completing the memory cell structure shown in FIG.

On the other hand, although not shown, after completion of the memory cell structure shown in FIG. This is done.

Thirteenth embodiment

Next, a thirteenth embodiment of the present invention will be described. In the above first to twelfth embodiments, sufficient consideration has not been given to speeding up transistors other than memory cells. On the other hand, as a structure of a high-speed CMOS transistor, attempts have been made to speed up the logic gate by reducing the capacitance between the gate electrode and the diffusion layer by forming a notch in the recessed state between the gate electrode and the source / drain diffusion layer (T). Ghani et al., IDEM99, p. 415). In this thirteenth embodiment, by using this structure for a nonvolatile semiconductor memory, it is possible to significantly speed up a conventional transistor having no memory function and a semiconductor device in which a nonvolatile semiconductor memory is mixed.

30 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to the thirteenth embodiment of the present invention. This memory cell is composed of n-type MOS transistors. In the memory cell structure of the nonvolatile semiconductor memory according to the thirteenth embodiment of the present invention, the gate electrode 3 is provided on the surface of the p-type semiconductor substrate 1 via the first gate insulating film 13. Recesses are provided at both ends of the gate electrode 3, and charge storage layers 4 (4a, 4b) are formed in each recess. An oxide film 30 is formed between the charge storage layer 4 and the gate electrode 3. Sidewall spacers 9 are provided on the side of the gate electrode 3 via an oxide film 16, and a low impurity concentration in contact with the channel region on the main surface of the p-type semiconductor substrate 1 below the sidewall spacers 9. The n ⁻ type diffusion layer 10 and the n ⁺ type diffusion layer 11 having a high impurity concentration located outside the n ⁻ type diffusion layer 10 are provided. The conductive layer 12 is provided on the surface of each of the first gate electrode 3 and the n ⁺ type diffusion layer 11.

The memory cell of the nonvolatile memory according to the thirteenth embodiment of the present invention has an LDD structure in which a source region and a drain region are composed of an n ⁻ type diffusion layer 10 having a low impurity concentration and an n ⁺ type diffusion layer 11 having a high impurity concentration. Equipped with. Charge accumulation layers 4 (4a, 4b) are formed on both end surfaces of the gate electrode (3). Electrons are accumulated in these two charge storage layers 4a and 4b, and the accumulation state is that (1) the charge storage layers 4a and 4b do not accumulate electrons. (2) The charge storage layers 4a. (4) four states: the state in which only electrons accumulate, (3) the state in which only the charge accumulation layer 4b accumulates electrons, and (4) the state in which the charge accumulation layers 4a and 4b all accumulate electrons. Can be taken. Changes in the threshold voltage caused by the presence or absence of electrons held in these two charge storage layers 4a and 4b correspond to " 00 "," 01 "," 10 " and " 11 " In this memory cell structure, since the charge storage layer 4 is located above the end of the channel region, the threshold voltage at the center of the channel region is determined only by the impurity concentration of the channel region, and the accumulation state of electrons in the charge storage layer 4 is achieved. Does not depend on Therefore, over-erasing due to the excessive shortage of the electrons in the charge storage layer 4 is prevented, and accordingly, leakage failure, program failure, reading failure, etc. due to over-erasure cannot occur. In addition, the leakage current between the source region and the drain region can be suppressed only by the gate voltage, thereby achieving a highly reliable nonvolatile memory. The charge accumulation layer 4 may be made of a silicon nitride film having a high charge accumulation capability by the CVD method. This is because by accumulating electrons at the discrete charge trapping level of the silicon nitride film, it is possible to obtain charge holding characteristics that are hardly affected by the film quality of the lower insulating film. Moreover, if it comprises a silicon film and a polycrystalline silicon film, it can manufacture at low cost. Further, when the first gate insulating film 13 is composed of a silicon nitride film (Si ₃ N ₄ film) having a dielectric constant about twice that of the silicon oxide film (SiO ₂ film), the silicon oxide film conversion film thickness is about 4 nm to 11 nm. The ultra-thin gate insulating film can be stably realized. For example, since the actual thickness of the silicon nitride film having a silicon oxide film thickness of about 5 nm is about 10 nm, direct tunnel DT injection is not induced. Therefore, the voltage at the time of electron injection / extraction operation is lowered, so that not only the memory cell can be miniaturized but also the peripheral high voltage operating element can be miniaturized.

In the memory cell of the nonvolatile memory according to the thirteenth embodiment of the present invention, although the n ⁻ type diffusion layer 10 is provided for the purpose of improving the breakdown voltage of the source region and the drain region, the LDD structure is formed. The drain region may be composed of a source region and a drain region.

Next, operations of the nonvolatile memory according to the thirteenth embodiment of the present invention will be described with reference to FIGS. 31A and 31B. Fig. 31A is a sectional view of the nonvolatile memory for explaining the write operation. Fig. 31B is a sectional view of the nonvolatile memory for explaining the erase operation. The memory cells of FIGS. 31A and 31B are composed of n-type MOS transistors. As shown in Fig. 31A, at the time of writing a memory cell, about 6 to 8 V is applied to the gate G and about 4 to 5 V to the drain D, respectively, and the source S is grounded. In this way, a voltage is applied and electrons are injected into the charge storage layer 4b on the drain region side by the channel thermal electrons CHE. When electrons are injected into the charge storage layer 4a on the source region side, the voltage applied to each of the drains D and S may be changed from the above. On the other hand, the memory cell is erased from the charge storage layers 4a and 4b by applying a negative voltage (˜-5V) to the gate G as shown in FIG. 31B and using a Fowler node-heim (FN) type tunnel current. By emitting electrons. When the gate G is shared by a plurality of memory cells, electrons can be emitted from these memory cells at the same time. In this case, the source S and the drain D may be coincident with the p-type semiconductor substrate 1. If a constant voltage different from the potential of the p-type semiconductor substrate 1 is applied to the drain electrode, and the source electrode is a floating potential, electrons can be emitted from only the charge storage layer 4b on the drain electrode side. When electrons are emitted from only the charge storage layer 4a on the source electrode side, it is sufficient to apply a constant voltage to the source electrode and set the drain electrode to the floating potential.

Although not shown, reading of the memory cell is performed by detecting a read current flowing between the source S and the drain D. FIG. The current transfer characteristic (channel conductance) in the vicinity of the source region and the drain region is modulated in accordance with the accumulation state of the charge accumulation layers 4a and 4b. Which one of the source S and the drain D is biased may be selected in which the modulation of the current transfer characteristic is remarkable. Four different current transfer characteristics are obtained according to the four accumulation states of the charge accumulation layers 4a and 4b, thereby storing two bits of information in one cell.

Next, the operation of the nonvolatile memory according to the thirteenth embodiment of the present invention constituted of the p-type MOS transistor will be described with reference to FIGS. 32A and 32B. 32A is a sectional view of a nonvolatile memory for explaining a write operation. 32B is a sectional view of the nonvolatile memory for explaining the erase operation. The memory cells of FIGS. 32A and 32B are composed of p-type MOS transistors. As shown in Fig. 32A, at the time of writing a memory cell, about 5V is applied to the gate G and about -5V to the drain D, respectively, and the source S is made a floating potential. In this way, a voltage is applied, and electrons are supplied to the charge accumulation layer 4b on the drain region side by supplying energy to the electrons caused by the interband tunnel phenomenon by an electric field near the drain region. When electrons are injected into the charge storage layer 4a on the source region side, the voltage applied to each of the drains D and S may be changed from the above. On the other hand, the erasing of the memory cells is performed by applying a negative voltage (˜-5 V) to the gate G as shown in Fig. 32B and emitting electrons from the charge storage layers 4a and 4b using the FN current. When the gate G is shared by a plurality of memory cells, electrons can be emitted from these memory cells at the same time. In this case, the source S and the drain D are the n-type semiconductor substrate 19 and coin or floating potential.

Although not shown, reading of the memory cell is performed by detecting a read current flowing between the source S and the drain D. FIG. The current transfer characteristic (channel conductance) in the vicinity of the source region and the drain region is modulated in accordance with the accumulation state of the charge accumulation layers 4a and 4b. Which one of the source S and the drain D is biased may be selected in which the modulation of the current transfer characteristic is remarkable. Four different current transfer characteristics are obtained according to the four accumulation states of the charge accumulation layers 4a and 4b, thereby storing two bits of information in one cell.

In the thirteenth embodiment of the present invention, as shown in Fig. 33, a normal MOS transistor having no memory function can also be realized. This is because in this MOS transistor, the charge storage layer 4 is disposed only on the source and drain regions 10 and 11, but not on the channel region. For this reason, the conduction characteristic of this MOS transistor is not influenced at all by the holding state of the electric charge of the charge storage layer 4. In addition, the parasitic capacitance between the gate, the source, and the drain is reduced due to the presence of the recessed portion of the gate electrode 3, so that the high speed operation of the MOS transistor is possible.

Fourteenth Embodiment

Next, a fourteenth embodiment of the present invention will be described. In the thirteenth embodiment, in the thirteenth embodiment, the charge storage layer 4 and the sidewall spacers 9 are integrated. 34 is a sectional view showing the memory cell structure of the nonvolatile semiconductor memory according to the fourteenth embodiment of the present invention. This memory cell is composed of n-type MOS transistors. In the memory cell structure of the nonvolatile semiconductor memory according to the fourteenth embodiment of the present invention, the gate electrode 3 is provided on the surface of the p-type semiconductor substrate 1 via the first gate insulating film 13. Recesses are provided at both ends of the gate electrode 3, and charge storage layers 4 (4a, 4b) are formed in each recess. An oxide film 30 is formed between the charge storage layer 4 and the gate electrode 3. Sidewall spacers 9 are provided on the side of the gate electrode 3 via the oxide film 16, and a part of the sidewall spacers 9 constitutes the charge storage layer 4. The main surface of the p-type semiconductor substrate 1 below the sidewall spacer 9 has an n ⁻ type diffusion layer 10 having a low impurity concentration in contact with the channel region and a high impurity positioned outside the n ⁻ type diffusion layer 10. The concentration n ⁺ type diffusion layer 11 is provided. The conductive layer 12 is provided on the surface of each of the first gate electrode 3 and the n ⁺ type diffusion layer 11.

In the fourteenth embodiment of the present invention, the sidewall spacer 9 and the charge accumulation layer 4 may be made of a silicon nitride film having a high charge accumulation capability by the CVD method. This is because by accumulating electrons at the discrete charge trapping level of the silicon nitride film, it is possible to obtain charge holding characteristics that are hardly affected by the film quality of the lower insulating film. Moreover, if it comprises a silicon film and a polycrystalline silicon film, it can manufacture at low cost.

In the fourteenth embodiment of the present invention, similarly to the thirteenth embodiment, a normal MOS transistor as shown in FIG. 35 can also be realized. This is because in this MOS transistor, the charge storage layer 4 is disposed only on the source and drain regions 10 and 11, but not on the channel region. For this reason, the conduction characteristic of this MOS transistor is not influenced at all by the holding state of the electric charge of the charge storage layer 4. In addition, the parasitic capacitance between the gate, the source, and the drain is reduced due to the presence of the recessed portion of the gate electrode 3, so that the high speed operation of the MOS transistor is possible.

In addition, this invention is not limited to each embodiment mentioned above, It can variously deform and implement within the range which does not deviate from the summary.

According to the present invention, a structure of a nonvolatile semiconductor memory device capable of storing a plurality of bits of information in a simple cell structure can be provided.

Further, according to the present invention, it is possible to provide a method of manufacturing a nonvolatile semiconductor memory device which manufactures a nonvolatile semiconductor memory device for storing a plurality of bits of information in a simple manufacturing process.

In addition, according to the present invention, it is possible to provide a semiconductor memory device in which a nonvolatile memory that can be electrically written and erased and a volatile memory that can be read and read at high speed can be provided in a simple manufacturing process.

According to the present invention, there can be provided a method of manufacturing a semiconductor memory device in which a nonvolatile memory that can be electrically written and erased and a volatile memory that can be read and read at high speed in a simple manufacturing process.

Claims (45)

(a) a first gate electrode disposed on a main surface of the semiconductor substrate via a gate insulating film; (b) charge storage layers disposed on side surfaces of both ends of the first gate electrode, (c) a second gate electrode disposed on the side surface of the first gate electrode via the charge storage layer; and (d) a conductive layer arranged by self-matching to electrically connect the first gate electrode and the second gate electrode. The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage layer is formed by stacking a silicon oxide film and a silicon nitride film. The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage layer is composed of three layers of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. (a) forming a first gate electrode on the main surface of the semiconductor substrate through a gate insulating film; (b) sequentially forming a charge storage layer and a second gate electrode on both side surfaces of the first gate electrode; and (c) forming a conductive layer which electrically connects the first gate electrode and the second gate electrode by self-alignment. (a) a gate insulating film composed of first, second and third insulating films disposed on a main surface of the semiconductor substrate, (b) a charge storage layer comprising silicon nitride films disposed at both ends of the second insulating film; (c) a gate electrode disposed on the gate insulating film, A nonvolatile semiconductor memory device, characterized in that the etching rates of the first and third insulating films are different from the etching rates of the second insulating films. delete delete (a) a step of sequentially forming first, second and third insulating films on the main surface of the semiconductor substrate, and forming a gate insulating film composed of these first, second and third insulating films; (b) forming a gate electrode by depositing a gate electrode constituent material on the gate insulating film, and then patterning the gate electrode constituent material and the gate insulating film; (c) forming a space by selectively removing both ends of the second insulating film; (d) A method of manufacturing a nonvolatile semiconductor memory device, comprising: forming a charge storage layer in a space thereof. The method of claim 8, wherein the space forming step includes a step of selectively etching only the second insulating layer using a difference in etching rates between the first and third insulating layers and the second insulating layer. Method of manufacturing a semiconductor memory device. The method of claim 8, wherein the charge accumulation layer forming step includes a step of depositing a charge accumulation layer constituent material to cover the gate electrode, and an anisotropic etching of the charge accumulation layer constituent material. Method of manufacturing volatile semiconductor memory device. (a) a nonvolatile semiconductor memory device comprising: (i) a first lower insulating film disposed on a main surface of a semiconductor substrate; and (ii) a first intermediate insulating film disposed on an upper portion of the center of the first lower insulating film. A first charge storage layer disposed over both ends of the first lower insulating film, (i) a first upper insulating film disposed over the first intermediate insulating film and the first charge storage layer, and (v) A nonvolatile semiconductor memory device including a first gate electrode disposed on an upper insulating layer; (b) a volatile semiconductor memory device comprising (i) a second lower insulating film made of the same material as the first intermediate insulating film and disposed on the main surface of the semiconductor substrate, and (ii) on the main surface of the semiconductor substrate. An ultra-thin insulating film disposed on both ends of the second lower insulating film, a second charge storage layer made of the same material as the first charge storage layer disposed on the ultra-thin insulating film, and A second upper insulating film made of the same material as the first upper insulating film disposed on the second lower insulating film and the second charge storage layer, and (iii) a second gate electrode disposed on the second upper insulating film. And a volatile semiconductor memory device. 12. The method of claim 11, wherein the etching rate of the first lower insulating film and the first upper insulating film is different from that of the first intermediate insulating film, and the etching rate of the second lower insulating film is different from that of the second upper insulating film. A semiconductor memory device, characterized in that. 12. The semiconductor memory device according to claim 11, wherein the first and second charge storage layers are formed of a silicon nitride film. 12. The semiconductor memory device according to claim 11, wherein the ultrathin insulating film has a film thickness capable of directly causing tunneling. (a) a nonvolatile semiconductor memory device comprising: (i) a first lower insulating film disposed on a main surface of a semiconductor substrate; and (ii) a first intermediate insulating film disposed on an upper portion of the center of the first lower insulating film. A first charge storage layer disposed over both ends of the first lower insulating film, (i) a first upper insulating film disposed over the first intermediate insulating film and the first charge storage layer, and (v) A nonvolatile semiconductor memory device including a first gate electrode disposed on an upper insulating layer; (b) a volatile semiconductor memory device comprising: (i) an ultrathin insulating film disposed on the main surface of the semiconductor substrate; and (ii) a second charge accumulation layer made of the same material as the first charge accumulation layer disposed on the ultrathin insulating film. A volatile semiconductor memory device comprising a layer, (i) a second upper insulating film disposed on a second charge storage layer, and (iii) a second gate electrode disposed on a second upper insulating film. Semiconductor memory device. The semiconductor memory device according to claim 15, wherein an etching rate of the first lower insulating layer and the first upper insulating layer is different from an etching rate of the first intermediate insulating layer. 16. The semiconductor memory device according to claim 15, wherein the first and second charge storage layers are made of a silicon nitride film. 16. The semiconductor memory device according to claim 15, wherein the ultrathin insulating film has a film thickness capable of directly causing tunneling. (a) a lower insulating film disposed on the main surface of the semiconductor substrate, (b) an ultrathin insulating film disposed on the main surface of the semiconductor substrate and on both ends of the lower insulating film, (c) a charge storage layer disposed on the ultrathin insulating film, (d) an upper insulating film disposed over the lower insulating film and the charge storage layer, (e) a volatile semiconductor memory device comprising a gate electrode disposed over the upper insulating film. (a) an ultrathin insulating film having a film thickness capable of causing direct tunneling phenomenon disposed on a main surface of a semiconductor substrate; (b) charge storage layers disposed on both ends of the ultrathin insulating film; (c) an upper insulating film disposed on the charge storage layer, and (d) a gate electrode disposed on the upper insulating film. (a) forming a first insulating film on a part of the main surface of the semiconductor substrate; (b) sequentially forming second and third insulating films on top of the first insulating film and a part of the main surface of the semiconductor substrate; (c) depositing a gate electrode constituent material on top of this third insulating film; (d) forming a first gate electrode by patterning the gate electrode constituent material, the third insulating film, the second insulating film and the first insulating film, (e) forming a second gate electrode constituent material by patterning the gate electrode constituent material, the third insulating film and the second insulating film, (f) forming a space by selectively removing both ends of the second insulating film on both sides of the first and second gate electrodes; (g) forming a charge storage layer in the space. 22. The semiconductor memory according to claim 21, wherein the space forming step includes a step of selectively etching only the second insulating film by using a difference in etching rates between the first and third insulating films and the second insulating film. Method of manufacturing the device. 22. The method of claim 21, wherein the charge accumulation layer forming step includes depositing a charge accumulation layer constituent material to cover the first and second gate electrodes, and anisotropically etching the charge accumulation layer constituent material. A method of manufacturing a semiconductor memory device, characterized in that. (a) sequentially forming first, second and third insulating films on the main surface of the semiconductor substrate; (b) after depositing a first gate electrode constituent material on the third insulating film, patterning the first gate electrode constituent material, the third insulating film, the second insulating film, and the first insulating film to form a first gate electrode. Forming process, (c) a step performed simultaneously with the first gate electrode forming step, wherein the gate electrode constituent material, the third insulating film, the second insulating film, and the first insulating film are removed from a part of the main surface of the semiconductor substrate. Forming a region for forming a gate electrode, (d) selectively removing both ends of the second insulating film of the first gate electrode to form a space; (e) forming an ultrathin insulating film on the main surface of the semiconductor substrate, (f) forming a charge storage layer in the space of the first gate electrode by anisotropically etching the charge storage layer constituting material after depositing a material constituting the charge storage layer on the main surface of the semiconductor substrate; (g) depositing a fourth insulating film and a second gate electrode constituent material on the main surface of the semiconductor substrate, and then patterning the second gate electrode constituent material, the fourth insulating film, the charge accumulation layer constituent material, and an ultrathin insulating film. A method of manufacturing a semiconductor memory device comprising the step of forming a second gate electrode. (a) an iron portion disposed on the main surface of the semiconductor substrate, (b) a gate insulating film composed of first, second and third insulating films disposed on a main surface of the semiconductor substrate including the convex portion, (c) charge storage layers disposed at both ends of the second insulating film; and (d) a gate electrode arranged on the gate insulating film. 27. The nonvolatile semiconductor memory device according to claim 25, wherein the charge storage layer is formed of a silicon nitride film. 27. The nonvolatile semiconductor memory device according to claim 25, wherein the etching rates of the first and third insulating films are different from the etching rates of the second insulating films. (a) forming a convex portion on the main surface of the semiconductor substrate; (b) a step of sequentially forming first, second and third insulating films on the main surface of the semiconductor substrate including the convex portions, and forming a gate insulating film composed of these first, second and third insulating films; (c) forming a gate electrode by depositing a gate electrode constituent material on the gate insulating film, and then patterning the gate electrode constituent material and the gate insulating film; (d) selectively removing both ends of the second insulating film to form a space; (e) A method of manufacturing a nonvolatile semiconductor memory device comprising the step of forming a charge storage layer in a space thereof. 29. The nonvolatile method as claimed in claim 28, wherein the space forming step includes a step of selectively etching only the second insulating film using a difference in etching rates between the first and third insulating films and the second insulating film. Method of manufacturing a semiconductor memory device. 29. The method of claim 28, wherein the charge accumulation layer forming step includes depositing a charge accumulation layer constituent material to cover the gate electrode, and anisotropic etching the charge accumulation layer constituent material. Method of manufacturing volatile semiconductor memory device. (a) a convex portion disposed on the main surface of the semiconductor substrate, (b) a gate insulating film composed of first and second insulating films disposed on a main surface of the semiconductor substrate including the convex portion; (c) a charge storage layer disposed between the first and second insulating films; and (d) a gate electrode arranged on the gate insulating film. 32. The nonvolatile semiconductor memory device according to claim 31, wherein the charge storage layer is formed of a silicon nitride film. (a) forming a convex portion on the main surface of the semiconductor substrate; (b) sequentially forming a first insulating film, a charge accumulation layer constituent material, and a third insulating film on the main surface of the semiconductor substrate including the iron portions; (c) forming a gate electrode by patterning the first insulating film, the charge accumulation layer constituent material, and the third insulating film. (a) a concave portion disposed on the main surface of the semiconductor substrate, (b) a gate insulating film composed of first, second and third insulating films disposed on the main surface of the semiconductor substrate including the recessed portions, (c) charge storage layers disposed at both ends of the second insulating film; and (d) a gate electrode arranged on the gate insulating film. 35. The nonvolatile semiconductor memory device according to claim 34, wherein the charge storage layer is formed of a silicon nitride film. 35. The nonvolatile semiconductor memory device according to claim 34, wherein the etching rates of the first and third insulating films are different from the etching rates of the second insulating films. (a) forming recesses on the main surface of the semiconductor substrate; (b) a step of sequentially forming first, second and third insulating films on the main surface of the semiconductor substrate including this recessed portion, and forming a gate insulating film composed of these first, second and third insulating films; (c) forming a gate electrode by depositing a gate electrode constituent material on the gate insulating film, and then patterning the gate electrode constituent material and the gate insulating film; (d) selectively removing both ends of the second insulating film to form a space; (e) A method of manufacturing a nonvolatile semiconductor memory device comprising the step of forming a charge storage layer in a space thereof. 38. The nonvolatile method according to claim 37, wherein the space forming step includes a step of selectively etching only the second insulating film by using a difference in etching rates between the first and third insulating films and the second insulating film. Method of manufacturing a semiconductor memory device. 38. The method of claim 37, wherein the charge accumulation layer forming step includes depositing a charge accumulation layer constituent material so as to cover the gate electrode, and anisotropic etching the charge accumulation layer constituent material. Method of manufacturing volatile semiconductor memory device. (a) a recess disposed on the main surface of the semiconductor substrate, (b) a gate insulating film composed of first and second insulating films disposed on a main surface of the semiconductor substrate including the recessed portion, (c) a charge storage layer disposed between the first and second insulating films; and (d) a gate electrode arranged on the gate insulating film. (a) forming recesses on the main surface of the semiconductor substrate; (b) sequentially forming a first insulating film, a charge storage layer forming material, and a third insulating film on the main surface of the semiconductor substrate including the recesses; (c) forming a gate electrode by patterning the first insulating film, the charge accumulation layer constituent material, and the third insulating film. (a) forming recesses on the main surface of the semiconductor substrate; (b) a step of sequentially forming first, second and third insulating films on the main surface of the semiconductor substrate including this recessed portion, and forming a gate insulating film composed of these first, second and third insulating films; (c) depositing a gate electrode component on top of the gate insulating film, and then removing the gate electrode component by chemical mechanical polishing to form a gate electrode embedded in the recess; (d) selectively removing both ends of the second insulating film to form a space; (e) A method of manufacturing a nonvolatile semiconductor memory device comprising the step of forming a charge storage layer in a space thereof. (a) forming recesses on the main surface of the semiconductor substrate; (b) a step of sequentially forming a first insulating film, a charge storage layer constituent material, and a third insulating film on the main surface of the semiconductor substrate including this recess; (c) depositing a gate electrode component on top of the third insulating film, and then removing the gate electrode component by chemical mechanical polishing to form a gate electrode embedded in the recess. Method for manufacturing nonvolatile semiconductor memory device. (a) a gate electrode arranged on the main surface of the semiconductor substrate via a gate insulating film; (b) a recess disposed at an end of the gate electrode, (c) the recess includes a charge storage layer disposed through an insulating film, And the charge storage layer is disposed above both the channel region and the source and drain regions. 45. The nonvolatile semiconductor memory device according to claim 44, wherein the charge storage layer is integrated with sidewalls arranged on the side surfaces of the gate electrode.