KR100385946B1 - Method for forming a metal layer by an atomic layer deposition and a semiconductor device with the metal layer as a barrier metal layer, an upper electrode, or a lower electrode of capacitor - Google Patents

Method for forming a metal layer by an atomic layer deposition and a semiconductor device with the metal layer as a barrier metal layer, an upper electrode, or a lower electrode of capacitor Download PDF

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KR100385946B1
KR100385946B1 KR20000006251A KR20000006251A KR100385946B1 KR 100385946 B1 KR100385946 B1 KR 100385946B1 KR 20000006251 A KR20000006251 A KR 20000006251A KR 20000006251 A KR20000006251 A KR 20000006251A KR 100385946 B1 KR100385946 B1 KR 100385946B1
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metal layer
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metal
atomic
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KR20010066730A (en
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강상범
임현석
채윤숙
전인상
최길현
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삼성전자주식회사
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    • C23C16/45531Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations specially adapted for making ternary or higher compositions
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Abstract

Semiconductor films include insulating films including contact holes in semiconductor substrates, capacitors comprising lower electrodes formed on conductive material films in the contact holes, high dielectric films formed on the lower electrodes and upper electrodes formed on the high dielectric films, and barrier metal layers positioned between conductive materials in the contact holes and the lower electrodes, the barrier metal layers including metal layers formed in A-B-N structures in which a plurality of atomic layers are stacked by alternatively depositing reactive metal (A), an amorphous combination element (B) for preventing crystallization of the reactive metal (A) and nitrogen (N). The composition ratios of the barrier metal layers are determined by the number of depositions of the atomic layers.

Description

원자층 증착법을 이용한 금속층 형성방법 및 그 금속층을 장벽금속층, 커패시터의 상부전극, 또는 하부전극으로 구비한 반도체 소자{Method for forming a metal layer by an atomic layer deposition and a semiconductor device with the metal layer as a barrier metal layer, an upper electrode, or a lower electrode of capacitor} A metal layer forming method using the atomic layer deposition method and a metal layer barrier metal layer, a semiconductor element {Method for forming a metal layer by an atomic layer deposition and provided with an upper electrode or lower electrode of the capacitor a semiconductor device with the metal layer as a barrier metal layer, an upper electrode, or a lower electrode of capacitor}

본 발명은 원자층 증착법(atomic layer deposition)을 이용한 금속층 형성방법 및 그 금속층을 장벽금속층, 커패시터의 상부전극, 또는 하부전극으로 구비한 반도체 소자에 관한 것이다. The present invention relates to a semiconductor device including a method of forming a metal layer using an ALD (atomic layer deposition), and the metal layer as a barrier metal layer, the upper electrode or lower electrode of the capacitor.

반도체 소자가 점점 고집적화됨에 따라, 작은 면적에서 큰 커패시턴스를 얻기 위하여 유전상수가 큰 고유전물질(high dielectric material)들이 개발되고 있다. As more and more highly integrated semiconductor devices, a high dielectric material having a large dielectric constant (high dielectric material) have been developed in order to obtain large capacitance in a small area. 예컨대, 페로브스카이트(perovskite) 결정 구조를 가지는 BST(BaSrTiO 3 )의 경우 기존의 커패시터에 사용되었던 실리콘 질화막, 실리콘 질화산화막 또는 산화탄탈륨(Ta 2 O 5 )막과는 달리 유전상수가 벌크 상태에서 수백 ∼ 1000 정도 되는 물질이다. For example, the perovskite BST (BaSrTiO 3) the silicon has been used in conventional capacitor nitride film, a silicon nitride oxide film or a tantalum oxide (Ta 2 O 5), unlike the film has a dielectric constant bulk case of having a (perovskite) crystal structure from a few hundred to 1,000 substances. 이러한 BST를 사용하는 경우 막의 두께를 500Å 이상으로 하더라도 등가산화막 두께(equivalent oxide thickness)를 10Å 이하로 유전막을 박막화할 수 있다는 장점을 가진다. When using these BST, even if the thickness of the film to more than 500Å has the advantage that the equivalent oxide film thickness (equivalent oxide thickness) to thin the dielectric layer to less than 10Å. BST용 전극으로는 백금(Pt)과 같이 산화가 되지 않는 전극이나, 또는 루테늄(Ru), 이리듐(Ir)과 같이 산화되어 산화 루테늄(RuO 2 ), 산화 이리듐(IrO 2 )을 형성하더라도 전도체의 성질을 가지는 전극을 사용한다. The electrode for BST is platinum is oxidized, such as (Pt), electrodes or not an oxide, such as or a ruthenium (Ru), iridium (Ir) of the conductor be formed of ruthenium oxide (RuO 2), iridium oxide (IrO 2) It uses an electrode having a property.

BST 고유전막에서 우수한 커패시턴스와 누설전류 특성을 얻기 위해서는 BST를 증착한 후 고온에서의 열처리가 필요하다. In order to obtain excellent capacitance and leakage current characteristics in the BST unique conductive film after depositing a BST it requires a heat treatment at a high temperature. 이때 산소의 확산에 의한 오믹층과 폴리 실리콘 플러그의 산화를 막기 위해 장벽 금속층을 형성할 필요가 있다. In this case it is necessary to form a barrier metal layer to prevent the ohmic layer and the oxidation of the polysilicon plug due to diffusion of oxygen. 장벽 금속층은 폴리실리콘 플러그와 하부전극 사이에 개재되어진다. A barrier metal layer is interposed between the polysilicon plug and the bottom electrode.

상기 장벽 금속층으로 TiN막이 주로 사용되고 있으나 TiN의 경우 450℃ 이상이면 산화된다. Although TiN film is mainly used as the barrier metal layer it is oxidized in the case of TiN over 450 ℃. 그리고, BST막 증착후에 산소 분위기에서 고온 열처리를 진행할 경우 백금(Pt)은 산소를 쉽게 통과시키므로 TiN막 및 폴리 실리콘 플러그가 산화되는 문제가 있다. Further, in the case proceed with the high temperature heat treatment in an oxygen atmosphere after BST film deposited platinum (Pt) is to pass the oxygen because there is a problem in that the TiN film, and the polysilicon plug from being oxidized. 상기 TiN막이 산화되면 부도체인 TiO 2 가 생성되는 문제가 있다. When the TiN film is oxidized, there is a problem that is non-conductive TiO 2 is produced.

또한, 상기 TiN막은 Pt와 Si 등이 내부로 확산하여 결과적으로 장벽 금속층으로서의 역할을 할 수 없다. In addition, the TiN film can not be the result serves as a barrier metal layer to diffuse into the interior, such as Pt and Si. Pt와 Si의 확산은 TiN의 칼럼형 결정구조(columnarstructure)에 기인하는 것으로 알려져 있다. Diffusion of Pt and Si is known to be due to the TiN columnar crystal structure (columnarstructure). 따라서 막 구조를 확산경로가 되는 결정입계를 갖지 않는 비정질(amorphous) 구조로 함으로써 산소의 확산을 억제할 필요가 있다. Thus, by an amorphous (amorphous) structure having no grain boundary diffusion paths to which the membrane structure it is necessary to suppress the diffusion of oxygen.

이러한 필요로부터 현재 고융점 금속이 포함된 화합물(compound)에 대한 연구가 활발히 진행되고 있다. From this current needs and has become a research on a compound (compound) containing a refractory metal actively. 상기한 고융점 금속이 포함된 화합물로 이루어진 장벽 금속층은 화학기상증착법에 의하여 증착하는 경우 조성의 복잡함으로 인하여 조성의 조절 및 재현성이 떨어지는 문제점이 있다. A barrier metal layer made of the above high melting point metal contains the compound may be adjusted and the lowered reproducibility of the composition due to the complexity of the composition if deposited by a chemical vapor deposition method. 이러한 문제점으로 인하여, 고융점 금속이 포함된 화합물의 장벽금속층 형성시에는 질소 분위기에서의 반응성 스퍼터링(reactive sputtering) 공정이 일반적으로 사용되고 있다. Due to this problem, and the formation of the barrier metal layer that contains the refractory metal compound has a reactive sputtering (reactive sputtering) process in a nitrogen atmosphere is generally used. 그러나 이러한 스퍼터링에 의하여 형성된 장벽 금속층은 또한 스텝커버리지가 나쁜 단점이 있으므로, 반도체 소자가 고집적화됨에 따라 복잡한 구조를 가지는 커패시터 등에서의 장벽금속층, 예를 들면 트렌치형 커패시터 등에서와 같이 종횡비가 높은 트렌치의 저부에 형성되어야 하는 장벽금속층으로는 사용하기 어렵게 된다. However, the barrier metal layer formed by this sputtering is also a bottom of the high aspect ratio trenches, such as the barrier metal layer, for example, etc. trench capacitors, etc. capacitor having a complex structure as it is a disadvantage that the step coverage is bad, the semiconductor device is highly integrated a barrier metal layer to be formed is difficult to use.

본 발명이 이루고자 하는 기술적 과제는 원자층 증착법을 이용하여 스텝 커버리지가 우수하며, 조성의 적절한 조절에 의하여 원하는 저항 및 전도도를 용이하게 결정할 수 있고, 산소의 확산을 방지할 수 있는 우수한 금속층 형성 방법을 제공하는 데 있다. The present invention is superior to the step coverage by atomic layer deposition method, it is possible to easily determine a desired resistance and conductivity by appropriate adjustment of the composition, the excellent metal layer forming method that can prevent the diffusion of oxygen to provide.

본 발명이 이루고자 하는 다른 기술적 과제는 상기한 금속층 형성 방법에 의하여 형성된 금속층을 장벽 금속층, 커패시터의 하부 전극 및 상부 전극으로 구비한 반도체 소자를 제공하는 데 있다. The present invention is to provide a semiconductor device having a metal layer formed by the method of forming the metal layer as a barrier metal layer, the lower electrode and the upper electrode of the capacitor.

도 1a 및 도 1b는 본 발명의 제1 태양에 따른 금속층의 형성시 원자층 증착을 위한 소스가스들 및 퍼지가스의 주입방법의 일 예를 나타내는 그래프들이다. Figures 1a and 1b are graphs showing an example of the injection method of the source gas and the purge gas for the formation during an atomic layer deposition of a metal layer according to the first aspect of the present invention.

도 2a 및 도 2b는 본 발명에 제1 태양에 따른 금속층의 형성시 원자층 증착을 위한 소스가스들 및 퍼지가스의 주입방법의 다른 예를 나타내는 그래프들이다. Figures 2a and 2b are graphs showing another example of the injection method of the source gas and the purge gas for the formation during an atomic layer deposition of a metal layer according to the first aspect to the present invention.

도 3은 TiAlN층의 조성에서 Al의 조성비가 증가함에 따른 TiAlN층의 비저항값의 변화를 나타내는 그래프이다. Figure 3 is a graph showing a change in the specific resistance value of the TiAlN layer according as the composition ratio of Al in the composition of the TiAlN layer increases.

도 4는 본 발명에 따라 형성된 TiAlN막의 XRD 결과를 나타내는 그래프이다. 4 is a graph showing the XRD results TiAlN film is formed in accordance with the present invention.

도 5는 종래의 TiN막 및 본 발명에 의한 TiAlN막의 표면 SEM 사진들이다. 5 are the TiAlN film is a surface SEM photo of the conventional TiN film, and the present invention.

도 6은 본 발명에 따른 TiAlN막의 내열성과 내산화성을 실험하기 위하여 산소분위기에서 열처리된 TiAlN막의 Rs 변화를 나타낸 그래프이다. 6 is a graph showing the TiAlN film Rs changes the heat treatment in an oxygen atmosphere in order to test the heat resistance to TiAlN film and the oxidation resistance of the present invention.

도 7a 내지 도 7d는 본 발명의 일 실시예에 따라 금속층을 장벽금속층으로 채용한 반도체 소자의 제조방법을 순차적으로 도시한 단면도들이다. Figures 7a to 7d are the sectional views illustrating in sequence a method of manufacturing a semiconductor device employing a metal layer as a barrier metal layer in accordance with an embodiment of the invention.

도 8a 내지 도 8e는 본 발명의 일 실시예에 따라 금속층을 커패시터의 상부전극으로 채용한 반도체 소자의 제조방법을 순차적으로 도시한 단면도들이다. Figures 8a through 8e are the sectional views illustrating in sequence a method of manufacturing a semiconductor device employing a metal layer as an upper electrode of the capacitor, according to one embodiment of the invention.

도 9a 내지 도 9e는 본 발명의 일 실시예에 따라 금속층을 커패시터의 하부전극으로 채용한 반도체 소자의 제조방법을 순차적으로 도시한 단면도들이다. Figures 9a through 9e are the sectional views illustrating in sequence a method of manufacturing a semiconductor device employing a metal layer as the lower electrode of the capacitor, according to one embodiment of the invention.

도 10은 본 발명의 제2 태양에 따른 원자층 증착법을 이용한 금속층 형성방법을 설명하기 위한 단면도이다. 10 is a sectional view illustrating a metal layer forming method using the atomic layer deposition according to the second aspect of the present invention.

도 11은 도 10의 내산화층 형성시 원자층 증착을 위한 소스가스들 및 퍼지가스의 주입방법의 예를 나타내는 그래프이다. 11 is a graph showing an example of the injection method of the source gases and purge gases for an atomic layer deposition during the formation of the oxide layer in Fig.

도 12 및 도 13은 본 발명의 제3 태양에 따른 원자층 증착법을 이용한 금속층 형성방법을 설명하기 위한 단면도이다. 12 and 13 are cross-sectional views illustrating a metal layer forming method using the atomic layer deposition according to the third aspect of the present invention.

도 14 및 도 15는 본 발명의 제2 및 제3 태양에 따라 원자층 증착법을 이용하여 형성된 금속층을 장벽금속층으로 채용한 반도체 소자의 제조방법을 도시한 단면도이다. 14 and 15 are sectional views showing a manufacturing method of a second and a semiconductor device employing the metal layer is formed by using the atomic layer deposition according to the third aspect as a barrier metal layer of the present invention.

상기 기술적 과제를 달성하기 위하여, 본 발명의 제1 태양에 의한 금속층 형성 방법은 반도체 기판 상에 Ti, Ta, W, Zr, Hf, Mo 또는 Nb로 이루어진 반응성 금속(A), 질소(N), 및 상기 반응성 금속과 질소의 결정화를 방지하기 위해 Al, Si 또는 B로 이루어진 비정질결합용 원소(B)의 각 소스가스들을 펄스 형태로 주입하여 상기 반도체 기판 상에 상기 소스가스들을 화학흡착시킴으로써 원자층 증착법으로 복수의 원자층들이 적층된 ABN 구조의 금속층을 형성하는 단계를 포함한다. To an aspect, the metal layer forming method according to the first aspect of the present invention is reactive metals consisting of Ti, Ta, W, Zr, Hf, Mo or Nb on a semiconductor substrate (A), nitrogen (N), and atomic layer by chemical adsorption of the source gas of each source gas on the semiconductor substrate by injecting a pulse form of the amorphous binding element (B) for consisting of Al, Si or B in order to prevent the crystallization of the reactive metal and nitrogen and forming a metal layer of ABN structure of a plurality of atomic layers are stacked by vapor deposition.

특히, 상기 각 소스가스들을 서로 교번되도록 순서를 정하여 주입함으로써 각 원자층이 서로 교대로 배열되도록 하고, 상기 각 소스가스의 주입회수를 조절하여 상기 금속층의 조성비를 결정할 수 있다. In particular, it is possible to the appointed by each injection in order to alternate with each other and the source gas so as to be arranged to each other, each atomic layer alternately, by adjusting the number of the injection for each of the source gas to determine the composition ratio of the metal layers.

상기 비정질결합용 원소의 소스 가스의 주입회수를 조절함으로써 상기 금속층의 전기전도도 및 저항을 결정할 수 있다. By adjusting the number of times of injecting a source gas of the amorphous element for coupling it can determine the electrical conductivity and resistivity of the metal layers. 상기 금속층이 TiAlN층인 경우, 상기 TiAlN층에서의 Ti에 대한 Al의 함량은 10∼35 %로 할 수 있다. When the metal layer TiAlN layer, the content of Al to Ti in the TiAlN layer may be in 10-35%.

또한, 상기 다른 기술적 과제를 달성하기 위하여, 본 발명의 반도체 소자는반도체 기판 상에 콘택홀을 구비한 절연막; Further, in order to achieve the above another aspect, the semiconductor device of the present invention, an insulating film having a contact hole on a semiconductor substrate; 상기 콘택홀의 저면 상에 형성된 도전성 물질막; A conductive material layer formed on the bottom surface of the contact hole; 및 상기 콘택홀 내부의 도전성 물질막 상부에 형성된 하부전극, 상기 하부전극 상에 형성된 고유전막 및 상기 고유전막 상부에 형성된 상부전극을 포함하는 커패시터를 구비한다. And a capacitor including a unique conductor film and an upper electrode formed on an upper part of the specific conductive film formed on the contact hole, inside the lower electrode conductive material film formed on the upper portion of the lower electrode.

특히, 상기 콘택홀 내부의 도전성 물질막과 상기 하부전극 사이에, Ti, Ta, W, Zr, Hf, Mo 또는 Nb로 이루어진 반응성 금속(A), 질소(N), 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위해 Al, Si 또는 B로 이루어진 비정질결합용 원소(B)가 원자층 증착법에 의하여 서로 교대로 적층된 상태로 배열된 원자층들로 구성된 ABN 구조의 장벽금속층을 구비하며 상기 장벽금속층의 각 원자층의 조성비는 각 원자층의 적층회수에 의하여 결정됨을 특징으로 한다. In particular, between the contact holes inside of the conductive material layer and the lower electrode of Ti, Ta, W, Zr, Hf, Mo or Nb reactive metal (A), nitrogen (N), and the reactive metal and nitrogen consisting of the amorphous bonding element (B) for consisting of Al, Si or B in order to prevent crystallization having a barrier metal layer of ABN structure consisting of the atomic layers arranged in a stacked state to each other alternately by atomic layer deposition method, and the barrier metal layer the composition ratio of the atoms of the layer is characterized in that it is determined by the stacking number of each atomic layer.

상기 비정질결합용 원소(B)에 의한 원자층의 적층회수의 비율에 따라 상기 장벽금속층의 전기전도도 및 저항을 결정할 수 있다. Depending on the ratio of the number of lamination of atoms on the amorphous layer by coupling element (B) can be determined for the electrical conductivity and resistivity of the barrier metal layer.

또한, 상기 다른 기술적 과제를 달성하기 위하여, 본 발명의 반도체 소자는 반도체기판 상의 물질층 상에 형성된 하부전극, 상기 하부전극 상에 형성된 고유전막 및 상기 고유전막 상부에 형성된 상부전극을 구비한 커패시터를 포함한다. Further, in order to achieve the above another aspect, the semiconductor device of the present invention is a capacitor comprising a lower electrode, an upper electrode formed on the specific conductive film and above the specific conductive film formed on the lower electrode formed on the material layer on the semiconductor substrate It includes.

특히, 상기 하부 전극은 Ti, Ta, W, Zr, Hf, Mo 또는 Nb로 이루어진 반응성 금속(A), 질소(N), 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위해 Al, Si 또는 B로 이루어진 비정질 결합용 원소(B)가 원자층 증착법에 의하여 서로 교대로 적층된 상태로 배열된 원자층들로 구성된 ABN 구조이며, 상기 하부 전극의 각 원자층의 조성비는 각 원자층의 적층회수에 의하여 결정된다. In particular, the lower electrode is to Al, Si or B in order to prevent reactive metal (A), nitrogen (N), and the crystallization of the reactive metal and nitrogen consisting of Ti, Ta, W, Zr, Hf, Mo or Nb is made of amorphous coupling element (B) for an ABN structure consisting of the atomic layers arranged in a stacked state to each other alternately by atomic layer deposition method, the composition ratio of the atomic layer of the lower electrode, by stacking number of each atomic layer It is determined.

상기 상부 전극도 상기 하부 전극과 동일하게 구성할 수 있다. The upper electrode may also be configured in the same manner as the lower electrode. 상기 비정질 결합용 원소에 의한 원자층의 적층회수의 비율에 따라 상기 상부 전극의 전기전도도 및 저항을 결정할 수 있다. Depending on the ratio of the number of lamination of atoms on the amorphous layer by binding elements for can determine the electrical conductivity and resistance of the upper electrode.

상기 기술적 과제를 달성하기 위하여, 본 발명의 제2 태양에 의한 금속층 형성 방법은 반도체 기판 상에 Ti, Ta, W, Zr, Hf, Mo 또는 Nb로 이루어진 반응성 금속(A), 질소(N) 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위해 Al, Si 또는 B로 이루어진 비정질결합용 원소(B)의 각 소스가스를 펄스형태로 서로 교번되도록 순서를 정하여 공급하고, 조성비를 조절하게끔 상기 각 소스가스의 주입회수를 조절하면서 공급하여 상기 반도체 기판 상에 화학흡착시킴으로써 ABN 구조의 금속층을 형성하는 단계를 포함한다. To an aspect, the metal layer forming method according to the second aspect of the present invention is reactive metals consisting of Ti, Ta, W, Zr, Hf, Mo or Nb on a semiconductor substrate (A), nitrogen (N) and the reactive metal, and each of the source gas of the amorphous binding element (B) for consisting of Al, Si or B in order to prevent the crystallization of the nitrogen supply appointed order to alternate with each other in pulse form, and wherein each of the source gas hagekkeum adjusting the composition ratio to the feed by adjusting the injection number of times and forming a metal layer of ABN structure by chemical adsorption onto the semiconductor substrate. 더하여, 상기 금속층 상에 산소 확산 방지층을 형성하여 상기 금속층과 산소 확산 방지층이 각각 복수회 증착된 다중 금속층을 형성할 수 있다. In addition, there is the metal layer and the oxygen diffusion barrier layer to form a multiple metal-layer deposition a plurality of times each by forming an oxygen diffusion barrier layer on the metal layer.

상기 산소 확산 방지층은 상기 금속층이 형성된 반도체 기판 상에 금속 원소 및 산소의 소스 가스를 펄스 형태로 서로 교번되도록 공급하여 형성할 수 있다. The oxygen diffusion barrier layer can be formed by supplying to each other so that the alternating source gas of the metal element and oxygen on the semiconductor substrate where the metal layer formed as a pulse shape. 또한, 상기 산소 확산 방지층은 상기 금속층 상에 원자층 증착법으로 산소가 포함된 물질층을 형성한 후 상기 금속층 및 물질층이 형성된 반도체 기판을 열처리하여 얻어질 수 도 있다. Further, the oxygen diffusion barrier layer can also be obtained after forming a layer of a material that contains oxygen in an atomic layer deposition on the metal layer by heat-treating the metal layer and the semiconductor substrate material layer is formed. 상기 비정질 결합용 원소의 소스 가스의 주입회수를 조절함으로써 상기 금속층의 전기전도도 및 저항을 결정한다. By adjusting the number of times of injecting a source gas of the amorphous element for coupling to determine the electrical conductivity and resistivity of the metal layers. 상기 산소 확산 방지층은 알루미늄 산화막으로 형성할 수 있다. The oxygen diffusion barrier layer can be formed of aluminum oxide.

또한, 상기 다른 기술적 과제를 달성하기 위하여, 본 발명의 반도체 소자는 반도체기판 상에 콘택홀을 구비한 절연막; Further, in order to achieve the above another aspect, the semiconductor device of the present invention, an insulating film having a contact hole on a semiconductor substrate; 상기 콘택홀의 저면 상에 형성된 도전성 물질막; A conductive material layer formed on the bottom surface of the contact hole; 및 상기 콘택홀 내부의 도전성 물질막 상부에 형성된 하부전극, 상기 하부전극 상에 형성된 고유전막 및 상기 고유전막 상부에 형성된 상부전극을 포함하는 커패시터를 구비한다. And a capacitor including a unique conductor film and an upper electrode formed on an upper part of the specific conductive film formed on the contact hole, inside the lower electrode conductive material film formed on the upper portion of the lower electrode.

특히, 본 발명의 반도체 소자는 상기 콘택홀 내부의 도전성 물질막과 상기 하부전극 사이에, Ti, Ta, W, Zr, Hf, Mo 또는 Nb로 이루어진 반응성 금속(A), 질소(N) 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위해 Al, Si 또는 B로 이루어진 비정질결합용 원소(B)가 원자층 증착법에 의하여 서로 교대로 적층되고 적층 회수에 의하여 조성비가 결정되는 ABN 구조의 금속층과, 상기 금속층 상에 산소 확산 방지층이 형성되어 상기 금속층과 산소 확산 방지층이 각각 복수회 적층된 장벽 금속층이 형성되어 있다. In particular, the semiconductor device of the present invention between the lower electrode and the conductive material layer within the contact holes, the reactive metal (A), nitrogen (N) and the consisting of Ti, Ta, W, Zr, Hf, Mo or Nb metal layer of ABN structure in which the amorphous coupling element (B) for consisting of Al, Si or B in order to prevent the crystallization of the reactive metal and a nitrogen laminated to each other alternately by atomic layer deposition method, and the composition ratio is determined by the lamination number and the is the oxygen diffusion barrier layer formed on the metal layer has a metal layer and the oxygen diffusion barrier layer are laminated a plurality of times the barrier metal layer is formed.

상기 산소 확산 방지층 상에 산소가 포함된 물질층을 더 형성되어 있을 수 있다. A layer of a material that contains oxygen on the oxygen diffusion barrier layer may be further formed. 상기 비정질 결합용 원소에 의한 원자층의 적층회수의 비율에 따라 상기 장벽 금속층의 전기전도도 및 저항을 결정할 수 있다. Depending on the ratio of the number of lamination of atoms on the amorphous layer by binding elements for can determine the electrical conductivity and resistivity of the barrier metal layer. 상기 산소 확산 방지층은 알루미늄 산화막으로 구성할 수 있다. The oxygen diffusion barrier layer can be comprised of aluminum oxide.

상기한 바와 같이, 본 발명에 따른 원자층 증착법을 이용하여 형성된 금속층(다중 금속층)은 내열성 및 내산화성이 높으며, 각각의 원자층을 증착하여 형성하므로 매우 콤팩트한 영역에서도 스텝 커버리지가 우수하다. As described above, the atomic layer deposition method of the metal layer (multi-metal layer) is formed by using in accordance with the present invention is excellent in the step coverage of a very compact area, it is formed by depositing a heat resistance and a high oxidation resistance, each atomic layer. 또한, 본 발명의 금속층(다중 금속층)은 각각의 원자층을 순서대로 흡착하여 형성하므로 조성비의 조절이 용이하며 이에 따라 저항 및 전기 전도도를 매우 용이하게 조절할 수 있다. In addition, metal layers (multi-metal layer) of the present invention can very easily adjust the resistance and the electrical conductivity thus form it is easy to control the composition ratio of In to adsorb each of the atomic layers in order: 또한, 본 발명의 원자층 증착법을 이용하여 형성되는 금속층을 반도체 소자의 장벽금속층, 하부 전극 또는 상부 전극에 채용할 수 있다. In addition, there may be employed a metal layer formed by using the atomic layer deposition method of the present invention on the barrier metal layer, the lower electrode or the upper electrode of the semiconductor element.

이하, 첨부 도면을 참조로 하여 본 발명의 바람직한 실시예를 설명한다. Below with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

본 발명의 제1 태양에 따른 원자층 증착법을 이용한 금속층 형성방법 The method of forming the metal layer by atomic layer deposition according to the first aspect of the present invention

먼저, 원자층 증착법을 간단히 설명한다. First, a brief description of the atomic layer deposition method. 반도체 소자 제조시 원자층 증착법 (Atomic Layer Deposition)이란 반응물질을 챔버 내로 순차적으로 주입하고 제거하는 방식으로 반도체 기판 상에 복수의 원자층들을 순차적으로 증착하는 방법이다. The semiconductor device fabrication is when the reactants atomic layer deposition (Atomic Layer Deposition) in such a manner as to sequentially injected into the chamber and removing as a method of sequentially depositing a plurality of atomic layers on a semiconductor substrate. 이러한 원자층 증착법은 화학기상증착법(CVD)처럼 화학반응을 사용하는 증착법이지만 각각의 가스를 동시에 주입하여 챔버 내에서 혼합되지 않고 한 종류의 가스씩 펄스 형태로 흘려진다는 점에서 CVD와 구별된다. This atomic layer deposition is distinguished from CVD in deposition, but that it is flush with one type of gas by pulse forms and should not be mixed in the chamber by injecting of the gases at the same time to use a chemical reaction such as chemical vapor deposition (CVD). 예컨대, A와 B 가스를 사용하는 경우, 먼저 A 가스를 주입하여 기판 상에 A 가스 분자를 화학흡착(Chemisorption)시켜 A 원자층을 형성한다. For example, in the case of using the A and B gases, the first gas A to injection by chemisorption (Chemisorption) a A gas molecules on a substrate to form an A atom layer. 챔버에 잔류한 A 가스는 아르곤이나 질소와 같은 불활성가스로 퍼지한다. Han A gas remaining in the chamber is purged with an inert gas such as argon or nitrogen. 이후 B 가스를 주입하여 화학흡착시킴으로써 A 원자층 상에 B 원자층을 형성한다. After subject to gas B injected to form the B atom layer on the layer A atoms by chemisorption. 상기 A 원자층과 B 원자층사이의 반응은 화학흡착된 A 원자층의 표면에서만 일어난다. The reaction between the A atom and B atom layer layer takes place only on the surface of the A atom chemisorbed layer. 이 때문에 어떠한 몰포로지를 가진 표면이라 해도 탁월한 스텝커버리지를 획득할 수 있다. For this reason, even as a surface with whether any morphology can be obtained an excellent step coverage. A 및 B의 반응 후 챔버에 잔존하는 B 가스 및 반응부산물을 퍼지시킨다. After the reaction of A and B causes the purge gas B, and reaction by-products remaining in the chamber. 상기의 A 또는 B 가스를 유입시켜 원자층 증착을 반복함으로써 박막의 두께를 원자층 단위로 조절할 수 있게 된다. By repeating the atomic layer deposition to the inlet of the gas A or B it is able to control the thickness of thin films by atomic layer unit.

다음에, 본 발명의 제1 태양에 따라 형성된 원자층 증착법으로 금속층을 형성하는 방법을 설명한다. Next, the method for forming the second metal layer by atomic layer deposition formed in accordance with the first aspect of the present invention. 상기 금속층은 복수의 원자층들이 적층되어 있는 ABN 구조이다. The metal layer is a structure in which ABN is a plurality of atomic layers are stacked. 여기서, 상기 A는 반응성 금속이며, 상기 N은 질소, 및 상기 B는 비정질결합용 원소(B)이다. Wherein A is a reactive metal, N is nitrogen, and B is the element (B) for amorphous bonding. 상기 반응성 금속(A)은 전이금속(transition metal)으로써 Ti, Ta, W, Zr, Hf, Mo, Nb 등이 사용되고, 상기 비정질 결합용 원소(B)는 Al, Si, B 등이 사용된다. The reactive metal (A) is a transition metal (transition metal) as such as Ti, Ta, W, Zr, Hf, Mo, Nb is used, the amorphous coupling element (B) for this Al, Si, B or the like is used. 상기 비정질 결합용 원소(B)는 상기 반응성 금속을 구성하는 원소를 이용할 수 도 있다. The amorphous bonding element for (B) can also be used for the elements constituting the reactive metal. 상기 비정질 결합용 원소(B)는 상기 반응성금속과 질소의 결합을 방해하여 상기 금속층을 비정질로 형성하는 역할을 한다. The amorphous bonding element (B) for the acts of forming the metal layer into an amorphous by interfering with the binding of the reactive metal and nitrogen. 또한, 상기 비정질 결합용 원소는 후속의 열처리공정에서 ABN 구조의 금속층이 결정화되는 것을 막아주는 역할을 한다. In addition, the amorphous bonding element for serves to prevent the metal layer of ABN structure crystallized in the heat-treating step of the follow-up.

본 발명의 금속층의 대표적인 예로서 TiAlN막을 들 수 있다. TiAlN film may be mentioned as a representative example of the metal layer of the present invention. 상기 TiAlN막을 형성시 Ti의 소스가스로서 TiCl 4 , TDMAT(Tetrakis DeMethyl Amino Titanium), TDEAT(Tetrakis DeEthyl Amino Titanium) 중에서 선택된 어느 하나를 사용한다. The TiAlN film as the source gas for forming a Ti use any one selected from the group consisting of TiCl 4, TDMAT (Tetrakis DeMethyl Amino Titanium), TDEAT (Tetrakis DeEthyl Amino Titanium). Al의 소스가스는 TMA(TriMethyl Aluminum), TEA(TriEthyl Aluminum), TIBA(Tri-I-Buthyl Aluminum), AlClx 중에서 선택된 어느 하나를 사용한다. Al source gas is used any one selected from the group consisting of TMA (TriMethyl Aluminum), TEA (TriEthyl Aluminum), TIBA (Tri-I-Buthyl Aluminum), AlClx. 질소(N)의 소스가스로는 N 2 , NH 3 중에서 선택된 어느 하나를 사용한다. Source gas of nitrogen (N) uses at least one selected from N 2, NH 3.

상기 TiAlN 막을 형성하는 경우, 먼저, 반도체 기판을 원자층 증착 챔버 내에 로딩한다. In the case of forming the TiAlN film, first, it loads the semiconductor substrate within an atomic layer deposition chamber. 이어서, 가스 공급기로부터 가스 공급관을 통하여 원자층 증착챔버 내로 상기 금속층을 구성하는 세가지 원소, 즉, 반응성 금속(A), 질소(N), 및 알루미늄(Al)의 소스가스들을 공급한다. Then, the gas supplied from the gas supply source of the three elements, that is, the reactive metal (A), nitrogen (N), and aluminum (Al) constituting the metal layer into an atomic layer deposition chamber through the gas supply pipe. 각 소스가스의 공급시 각 소스가스들은 펄스형태로 서로 교번하면서 주입됨으로써 반도체 기판 상에 Ti, N, Al 원자층을 적층하여 형성한다. Each source gas for supply of the respective source gases are being implanted, while alternating with each other in pulse form is formed by laminating Ti, N, Al atomic layers on a semiconductor substrate. 상기 각 소스가스의 주입순서 및 주입회수를 적절히 결정함으로써Ti, N, Al로 구성된 금속층의 조성비를 적절히 조정한다. The gak by appropriately determining the injection sequence and the injection number of the source gas is adjusted to a composition ratio of the metal layer composed of Ti, N, Al properly. 특히, 상기 비정질 결합용 원소, 예컨대 Al에 의한 원자층의 적층회수의 비율에 따라 상기 금속층의 조성비를 조절할 수 있고, 이에 따라 전기전도도 및 저항을 결정할 수 있다. In particular, according to the ratio of the number of atomic layers stacked by the amorphous element for coupling, for example, Al can adjust the composition ratio of the metal layer, thereby to determine the electrical conductivity and resistance. 이하에서 Ti, N, Al의 조성의 조절의 예를 설명한다. Hereinafter will be described an example of control of the composition of Ti, N, Al.

도 1a 및 도 1b는 본 발명의 제1 태양에 따른 금속층의 형성시 원자층 증착을 위한 소스가스들 및 퍼지가스의 주입방법의 일 예를 나타내는 그래프들이다. Figures 1a and 1b are graphs showing an example of the injection method of the source gas and the purge gas for the formation during an atomic layer deposition of a metal layer according to the first aspect of the present invention.

도 1a 및 1b를 참조하면, TiCl 4 , TMA, NH 3 을 TiCl 4 - TMA - TiCl 4 - NH 3 의 싸이클로 반복하면서 주입함으로써, Ti가 풍부한 TiAlN층을 형성한다. Referring to Figure 1a and 1b, TiCl 4, TMA, the NH 3 TiCl 4 - TMA - TiCl 4 - by injection while repeating cycle of NH 3, to form a TiAlN layer Ti-enriched. 증착시 기판온도는 300∼700℃가 바람직하고, 챔버 내 압력은 0.1∼10 Torr, 상기 소스가스가 주입되는 펄스 온 시간은 0.1∼10 초가 적당하다. The substrate temperature is preferably in a pulse-on time 300~700 ℃, and the pressure in the chamber is from 0.1 to 10 Torr, the source gas is injected is suitably from 0.1 to 10 seconds.

도 1a에서는 상기 소스가스의 주입 중에 퍼지가스를 온오프없이 연속적으로 계속 주입하여 퍼지작업을 수행하는 경우이고, 도 1b에서는 상기 소스가스의 주입 펄스 사이에 퍼지가스를 펄스로 주입하여 퍼지작업을 수행한다. In Figure 1a, and the case of performing the purge operation was continuously continued infusion with no on-off the purge gas during the injection of the source gas, and Fig 1b in performing the purge operation by injecting a purge gas into a pulse in between the injection pulses of the source gas do. 이 때 퍼지가스로는 Ar, N 2 , He, H 2 등의 가스가 사용된다. At this time, the purge gas is a gas such as Ar, N 2, He, H 2 is used.

도 2a 및 도 2b는 본 발명의 제2 태양에 따른 금속층의 형성시 원자층 증착을 위한 소스가스들 및 퍼지가스의 주입방법의 다른 예를 나타내는 그래프들이다. Figures 2a and 2b are graphs showing another example of the injection method of the source gas and the purge gas for the second form when the atomic layer deposition of metal layers according to an aspect of the present invention.

도 2a 및 2b를 참조하면, TiCl 4 , TMA, NH 3 을 TiCl 4 - NH 3 - TMA - NH 3 의 싸이클로 반복하면서 주입함으로써 Al이 풍부한 TiAlN층을 형성한다. Referring to Figures 2a and 2b, TiCl 4, TMA, the NH 3 TiCl 4 - to form an Al-rich layer TiAlN by injection, repeating cycles of the NH 3 - NH 3 - TMA. 상기 증착시 챔버 조건은 도 1a 및 도 1b와 동일하다. During the deposition, the chamber conditions are the same as in Figure 1a and 1b. 즉, 기판온도는 300∼700℃가 바람직하고, 챔버 내 압력은 0.1∼10 Torr, 상기 소스가스가 주입되는 펄스 온 시간은 0.1∼10 초가 적당하다. That is, the substrate temperature is 300~700 ℃ is preferable, and the chamber pressure is from 0.1 to 10 Torr, the pulse on-time in which the source gas is injected is suitably from 0.1 to 10 seconds.

도 2a에서는 상기 소스가스의 주입 중에 퍼지가스를 온오프없이 연속적으로 계속 주입하여 퍼지작업을 수행하는 경우이고, 도 2b에서는 상기 소스가스의 주입 펄스 사이에 퍼지가스에 의한 퍼지작업을 수행한다. In Figure 2a performs a purge operation according to a case of continuously injection continues with no on-off the purge gas during the injection of said source gas perform a purge operation, in Figure 2b the purge gas between injection pulse of the source gas. 이 때 퍼지가스로는 Ar, N2, He, H2 등의 가스가 사용된다. At this time, the purge gas is a gas such as Ar, N2, He, H2 are used.

상기한 조성의 조절방법을 이용하여 각 소스가스의 주입회수를 적절히 조절함으로써 각 원자층의 증착비를 적절히 조절할 수 있으며, 각 원자층은 그 증착비에 따라 아래의 표 1에 나타난 바와 같이 전기전도도 및 저항이 서로 다르게 나타난다. Electrical conductivity, as by appropriately adjusting the injection number of times for each of the source gas using the control method of the aforementioned composition can be appropriately adjust the deposition rate of each atomic layer, each atomic layer is shown in Table 1 below in accordance with the deposition rate and resistance appears differently.

시료 1 Sample 1 시료 2 Sample 2 시료 3 Sample 3
Ti Ti 35% 35% 24% 24% 21% 21%
Al Al 15% 15% 26% 26% 31% 31%
N N 30% 30% 35% 35% 35% 35%
C C 17% 17% 10% 10% 8% 8%
Cl Cl 3% 3% 3% 3% 3% 3%
Ti:Al Ti: Al 1:0.43 1: 0.43 1:1.1 1: 1.1 1:1.48 1: 1.48
비저항ρ(μΩ-cm) Resistivity ρ (μΩ-cm) 589 589 3701 3701 9161 9161

상기의 표 1을 참조하면, TiAlN층의 조성에서 Ti에 비한 Al의 함량이 증가함에 따라 TiAlN층의 비저항이 증가함을 알 수 있다. Referring to the above Table 1, it can be seen that the specific resistance of the TiAlN layer is increased as in the composition of the TiAlN layer increasing the amount of Al to Ti ruthless. 비저항(ρ)은 전기전도도의 역수에 비례하므로, 비저항이 증가하면 전기전도도는 감소하게 된다. The specific resistance (ρ) is proportional to the reciprocal of the electric conductivity, the specific resistance is increased when the electric conductivity is decreased. 따라서 TiAlN층의 용도에 따라 적절한 전기전도도 및 저항값을 가지도록 적절히 형성할 수 있다. Therefore, it is possible to suitably formed so as to have an appropriate electrical conductivity, and a resistance value according to the application of the TiAlN layer.

도 3은 TiAlN층의 조성에서 TiN+AlN에 대한 AlN의 조성비가 증가함에 따른 TiAlN층의 비저항값의 변화를 나타내는 그래프이다. Figure 3 is a graph showing a change in the specific resistance value of the TiAlN layer according as the composition ratio of AlN of the TiN + AlN increase in the composition of the TiAlN layer.

도 3을 참조하면, TiAlN층의 조성에서 Al의 함량이 증가함에 따라 TiAlN층의 비저항이 증가함을 알 수 있다. Referring to Figure 3, it can be seen that the specific resistance of the TiAlN layer increases as the content of Al increases from the composition of the TiAlN layer. 커패시터의 전극 또는 하부전극과 폴리실리콘층 사이의 장벽금속층으로 사용되는 경우 비저항값은 소자의 패턴 제작에 따라 달라질 수 있으나 보통 300∼10000μΩ-cm 정도가 적당하며, 이에 따라 TiAlN층에서의 Ti에 대한 Al의 함량은 10∼35% 정도가 바람직하다. When used as a barrier metal layer between the capacitor electrode or the lower electrode and the polysilicon layer, the specific resistance value, and may vary depending on the pattern design of the device, but usually 300~10000μΩ-cm degree is suitable, so that for the Ti in TiAlN layer the content of Al is preferably about 10 to 35 percent.

도 4는 본 발명에 따라 형성된 TiAlN막의 XRD 결과를 나타내는 그래프이고,도 5는 종래의 TiN막 및 본 발명에 의한 TiAlN막의 표면 SEM 사진들이다. Figure 4 is a graph showing the XRD results TiAlN film is formed in accordance with the invention, Figure 5 are the TiAlN film is a surface SEM photo of the conventional TiN film, and the present invention.

구체적으로, 도 4의 상측 그래프는 Ti가 풍부한 TiAlN막의 XRD 결과이며, 하측 그래프는 Al이 풍부한 TiAlN막의 XRD 결과이다. Specifically, the upper graph of Figure 4 is the XRD results TiAlN film Ti is rich, and the lower graph is the XRD results Al-rich TiAlN film. 도 4에 도시된 바와 같이 본 발명의 제1 태양에 의하여 형성된 TiAlN막은 미미하게 TiAlN 피크가 관찰되나 전체적으로 비정질상태 임을 알 수 있다. Also the TiAlN film is formed by a slight first aspect of the present invention, as shown in 4, but TiAlN peak is observed it can be seen that as a whole the amorphous state. 그리고, 도 5에 도시된 바와 같이 본 발명의 TiAlN막은 TiN 막에 비하여 매우 평탄한 표면을 가진다. And has a very smooth surface compared to the TiAlN film is a TiN film of the present invention, as shown in FIG.

도 6은 본 발명에 따른 TiAlN막의 내열성과 내산화성을 실험하기 위하여 산소분위기에서 열처리된 TiAlN막의 Rs변화를 나타낸 그래프이다. 6 is a graph showing the TiAlN film Rs changes the heat treatment in an oxygen atmosphere in order to test the heat resistance to TiAlN film and the oxidation resistance of the present invention.

도 6을 참조하면, 본 발명에 따른 TiAlN막의 내열성과 내산화성을 실험하기 위하여 산소분위기에서 열처리된 TiAlN막의 Rs변화이다. 6, the TiAlN film is a change Rs heat treatment in an oxygen atmosphere in order to test the oxidation resistance and heat resistance TiAlN film according to the present invention. 0.1Torr의 산소분위기에서 600℃ 30분간 열처리된 250Å의 TiAlN막의 Rs는 아무 처리도 되지 않은 상태의 TiAlN막의 Rs와 비교하여 변하지 않는다. Rs TiAlN film in an oxygen atmosphere at 0.1Torr 600 ℃ 30 bungan the heat-treated 250Å is not changed as compared with the TiAlN film of the Rs is not any process condition. 따라서 우수한 내열성 및 내산화성을 가진다는 것을 알 수 있다. Thus it can be seen that has excellent heat resistance and oxidation resistance. 이렇게 TiAlN막이 내열성 및 내산화성이 좋은 이유는 열처리시 TiAlN막 내의 Al이 표면으로 이동하여 TiAlN막 표면상에 산화막, 즉 Al 2 O 3 막을 형성하여 산소의 확산을 방지하기 때문이다. Thus TiAlN film is why a good heat resistance and oxidation resistance is due to oxide film on the TiAlN film surface by moving the surface of Al in TiAlN film during heat treatment, that is to form a film Al 2 O 3 to prevent the diffusion of oxygen.

상기한 바와 같이 TiAlN막은 내열성 및 내산화성이 높으며, 각각의 원자층을 증착하여 형성하므로 매우 콤팩트한 영역에서도 스텝커버리지가 우수하고, 각각의 원자층을 순서대로 흡착하여 형성하므로 CVD법에 비하여 조성비의 조절이 용이하며 조성의 재현성이 뛰어난 특성을 가진다. Since TiAlN film heat resistance and has high oxidation resistance, and the step coverage excellent in a very compact area so formed by depositing each of the atomic layers, formed by adsorption of the respective atomic layer in the order as described above, the composition ratio compared with the CVD method control is easy, and has the excellent reproducibility of the composition characteristics.

이하에, 상기한 바와 같은 원자층 증착법을 이용하여 형성된 금속층을 장벽금속층으로 구비한 트렌치형 커패시터 및 그 제조방법, 상기 금속층을 상부전극으로 구비한 실린더형 커패시터 및 그 제조방법, 및 상기 금속층을 하부전극으로 구비한 트렌치형 커패시터 및 그 제조방법을 실시예 1 내지 3에서 상세히 설명한다. In the following, a trench capacitor comprises a metal layer formed by using the atomic layer deposition as described above, the barrier metal layer and a manufacturing method, the metal layer a cylindrical capacitor and a manufacturing method provided with the upper electrode, and the lower the metal layer It will be described in detail a trench capacitor and a method of manufacturing the same provided with electrodes in examples 1-3.

실시예 1 Example 1

본 실시예 1에서는 도 7a 내지 7d를 참조로 하여, 원자층 증착법을 이용하여 형성된 금속층을 장벽금속층으로 채용한 트렌치형 커패시터에 관하여 설명한다. In this Example 1, Figure 7a to 7d by reference, will be described with respect to a trench capacitor employed a metal layer is formed by using the atomic layer deposition as a barrier metal layer.

도 7a를 참조하면, 반도체 기판(104) 상에 실리콘 산화막(SiO 2 )으로 구성된 절연층(210)을 형성한다. Referring to Figure 7a, to form the insulating layer consisting of a silicon oxide film (SiO 2) on a semiconductor substrate 104 (210). 이어서, 상기 절연층(210)을 사진식각하여 콘택홀을 형성한다. Then, the photo etching the insulating layer 210 to form a contact hole.

도 7b를 참조하면, 트렌치형 커패시터를 형성하기 위하여 상기 콘택홀의 내부는 필요에 따라, 예컨대 필요한 커패시턴스에 따라, 매립하지 않을 수도 있고 소정의 깊이까지 일부분 매립할 수도 있다. Referring to Figure 7b, inside the contact holes to form trench capacitors, as needed, for example, according to the required capacitance may not be filled or may be embedded in a portion to a predetermined depth. 일부분 매립시 콘택홀 내에 폴리실리콘을 매립한 다음 습식식각 또는 화학 기계적 연마와 결합된 습식식각을 수행하여 콘택홀의 하부에 소정의 높이까지만 폴리실리콘막(212)을 남긴다. By filling the polysilicon in a contact hole during a portion embedded in and then by performing the wet etching combined with a wet etch or chemical mechanical polishing to leave the polysilicon film 212 only up to a predetermined height in the contact hole bottom.

도 7c를 참조하면, 상기 폴리실리콘막(212)을 포함한 절연층(210) 상부에 내열성 및 내산화성이 향상된 장벽금속층(214)을 형성한다. Referring to Figure 7c, to form the polysilicon film 212, the heat resistance and oxidation resistance are improved barrier metal layer 214 on the top insulating layer 210, including. 상기 장벽금속층(214)은 반응성 금속(A), 질소(N), 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위한 비정질 결합용 원소(B)가 원자층 증착법에 의하여 서로 교대로 적층된 상태로 배열된 도전층이다. The barrier metal layer 214 is a reactive metal (A), nitrogen (N), and in the stacked state to the reactive metal, and for amorphous bonding to prevent crystallization of the nitrogen element (B) with each other alternately by atomic layer deposition It is arranged in the conductive layer. 상기 반응성 금속(A)은 Ti, Ta, W, Zr, Hf, Mo, Nb 등이 사용되고, 상기 비정질 결합용 원소(B)는 Al, Si, B 등이 사용된다. The reactive metal (A) is such as Ti, Ta, W, Zr, Hf, Mo, Nb is used, the combination of the amorphous element (B) for the Al, Si, B or the like is used. 상기 비정질 결합용 원소는 상기 반응성금속과 질소의 결합을 방해하여 상기 금속층을 비정질로 형성하는 역할을 한다. The amorphous bonding element for serves to form the metal layer into an amorphous by interfering with the binding of the reactive metal and nitrogen.

예를 들어, 상기 장벽 금속층은 반응성 금속(Ti), 질소(N), 및 비정질 결합용 원소(Al)의 각 소스가스들, TiCl 4 , TMA, NH 3 을 펄스형태로 공급하여 상기 폴리실리콘막(212) 상에 상기 소스가스들을 화학적으로 흡착시켜 복수의 원자층으로 구성된 TiAlN층을 구성한다. For example, the barrier metal layer is a reactive metal (Ti), nitrogen (N), and each of the source gas of the amorphous binding element (Al) for, TiCl 4, TMA, wherein by supplying NH 3 by the pulse type polysilicon film adsorption of the source gas on the 212 chemically to constitute a TiAlN layer consisting of a plurality of atomic layers. 이 TiAlN층은 각 소스가스들이 서로 교번되면서 공급되도록 순서가 결정되어 각 대응 원자층이 서로 교대로 배열되는 구성을 가진다. The TiAlN layer is determined such that the sequence supplied as they alternate with each other each of the source gas has a configuration which is arranged to each other, each corresponding to an atomic layer alternately. 상기 TiAlN층은 상술한 바와 같이 내열성 및 내산화성이 좋다. The TiAlN layer is good in heat resistance and oxidation resistance as described above. 그리고, 상기 각 소스가스의 주입회수를 적절히 조절하는 것에 의하여 상기 장벽금속층(214)을 구성하는 Ti, Al, 및 N의 각 조성비를 적절히 결정한다. Then, the suitably determined for each composition ratio of Ti, Al, and N constituting the barrier metal layer 214 by being appropriately adjusting the injection number of times for each of the source gas. 상기 각 조성비를 적절히 결정함에 의하여 필요한 전기전도도 및 저항을 적절히 결정할 수 있는 구성을 가진다. As the composition ratio appropriately determined by each has a configuration which can appropriately determine the required electrical conductivity and resistance.

조성의 조절의 예는 도 1a, 1b, 2a, 2b를 참조로 하여 상기에서 설명한 예들이 적용될 수 있고, 원자층의 증착시 증착조건도 동일하기 적용될 수 있다. The composition of the control example may be applied to the example described above with the Figure 1a, 1b, 2a, 2b by reference, may be applied to the same degree the deposition conditions during deposition of an atomic layer. 퍼지작업도, 도 1a 및 도 2a 에서 처럼 상기 소스가스의 주입 중에 퍼지가스를 온오프없이 연속적으로 계속 주입하여 퍼지작업을 수행할 수 있고, 도 1b 및 도 2b에서 처럼 상기 소스가스의 주입 펄스 사이에 퍼지가스에 의한 퍼지작업을 수행할 수 있다. Between the purge operation also, it is possible to continuously keep the injection into a purge gas without on-off during the injection of the source gas, as shown in Figure 1a and 2a to perform the purge operation, the injection pulse of the source gas as in FIG. 1b and 2b the purge operation can be performed by the purge gas. 이 때 퍼지가스로는 Ar, N 2 , He, H 2 등의 가스가 사용된다. At this time, the purge gas is a gas such as Ar, N 2, He, H 2 is used.

상기 폴리실리콘막(212)을 포함한 절연층(210) 상부에 TiAlN층을 형성한 후, 상기 콘택홀 외부에 증착된 금속층 부분을 습식식각이나 화학 기계적 연마로 에치백하여 제거함으로써 콘택홀 내부에만 형성된 장벽금속층(214)을 완성한다. After the formation of the TiAlN layer on the insulating layer 210 including the polysilicon film 212, it is formed only within the contact hole by removing a metal layer portion deposited on the outside of the contact hole by etching back by a wet etching or a chemical mechanical polishing to complete the barrier metal layer 214. 본 발명의 원자층 증착법을 이용한 장벽금속층(214)은 종래와 다르게 두께를 두껍게 할 수 있으며 두께의 조절이 자유롭고, 조성의 조절이 정확하고 용이하다. A barrier metal layer 214 by the atomic layer deposition method of the present invention may be different, and the thickness of the conventional free and control of the thickness, the adjustment of the composition is accurately and easily. 장벽금속층의 비저항값은 300∼10000 μΩ-cm 정도가 적당하며, 이에 따라 TiAlN층에서의 Ti에 대한 Al의 함량은 10∼35% 정도가 되도록 적절히 Al의 조성을 조절한다. Resistivity of the barrier metal layer is 300-10000 and μΩ-cm degree is suitable, so that the content of Al to Ti in TiAlN layer is appropriately adjusted so that the Al composition of about 10-35%.

도 7d를 참조하면, 상기 결과물의 상부에 Cu, Al, W 등과 같은 금속으로 구성된 실린더형 하부전극(216)을 형성한다. Referring to Figure 7d, it forms a cylindrical lower electrode 216 composed of a metal such as Cu, Al, W at an upper side of the resultant. 하부전극(216)이 Cu와 같이 확산이 쉬운 금속일 경우에는 상기한 바와 같은 장벽금속층(214)은 확산방지에 우수한 특성을 보인다. When the lower electrode 216 is a diffusion easy metals such as Cu, the barrier metal layer 214, as described above exhibit excellent properties to prevent diffusion.

다음, 유전율이 큰 탄탈륨산화막(Ta2O5) 또는 PZT((Pb,Zr)TiO3), BST((Ba,Sr)TiO3), STO(SrTiO3) 등과 같은 강유전체를 사용하여, 상기 트렌치형 하부전극층(216)을 덮는 유전막(218)을 형성하고, 그 상부에 상부전극(220)을 차례로 형성한다. Next, a tantalum oxide film is large dielectric (Ta2O5) or PZT ((Pb, Zr) TiO3), BST ((Ba, Sr) TiO3), STO using a ferroelectric, wherein the trench bottom electrode layer 216, such as (SrTiO3) forming a dielectric layer 218 for covering the to form an upper electrode 220, in turn thereon.

실시예 2 Example 2

본 실시예 2에서는 도 8a 내지 도 8e를 참조로 하여, 원자층 증착법을 이용하여 형성된 금속층을 상부전극으로 채용한 실린더형 커패시터에 관하여 설명한다. In the second embodiment to the Fig. 8a to Fig 8e as a reference, it will be described below a metal layer is formed by using the atomic layer deposition on a cylindrical capacitor employed as an upper electrode.

도 8a를 참조하면, 반도체기판(104) 상에 실리콘 산화막(SiO 2 )으로 구성된 절연층(210)을 형성한다. Referring to Figure 8a, to form an insulating layer composed of a silicon oxide film (SiO 2) on a semiconductor substrate 104 (210). 이어서, 상기 절연층(210) 내에 사진식각공정을 이용하여 콘택홀을 형성한다. Then, using a photolithography process in the insulator layer 210 to form a contact hole.

도 8b를 참조하면, 상기 콘택홀(212)의 내부를 채우는 도전성 물질로 매립하여 플러그(212)를 형성한다. Referring to Figure 8b, by filling a conductive material filling the interior of the contact holes 212 to form the plug 212. The 예를 들면 도핑된 폴리실리콘으로 매립하여 폴리플러그를 형성할 수 있다. For example, it is filled with doped polysilicon to form a poly plug.

도 8c를 참조하면, 상기 플러그(212)를 포함한 절연층 상부에 포토레지스트 패턴(미도시)을 이용하여 Al, W 등과 같은 금속으로 구성된 실린더형 하부전극(214)을 형성한다. Referring to Figure 8c, with the plug (not shown) photoresist pattern for the upper insulating layer, including 212 forms a cylinder-type lower electrode 214 composed of a metal such as Al, W. 상기 실린더형 하부전극(214) 및 폴리플러그(212) 사이에는 후속하는 열처리 공정시 폴리 플러그의 산화를 방지하기 위하여 TiN, TaN 등을 이용하여 장벽금속층(216)을 형성한다. To form a barrier metal layer 216 by using a TiN, TaN to between the cylindrical lower electrode 214 and the poly plug 212 is to prevent oxidation of the poly plug during the heat treatment process that follows. 그리고, 하부전극(214)이 Cu와 같이 확산이 쉬운 금속일 경우에는 삼원계 금속층, 예컨대 TiSiN, TaSiN, TiAlN 등으로 된 장벽금속층(114)은 확산방지에 우수한 특성을 보인다. Then, when the lower electrode 214 is a diffusion is easy, the metal such as Cu ternary metal layer, for example, a barrier metal layer 114 by TiSiN, TaSiN, TiAlN, etc. show excellent properties in anti-proliferation.

도 8d를 참조하면, 유전율이 큰 탄탈륨산화막(Ta 2 O 5 ) 또는 PZT((Pb,Zr)TiO 3 ), BST((Ba,Sr)TiO 3 ), STO(SrTiO 3 ) 등과 같은 강유전체를 사용하여, 상기 실린더형 하부전극(214)을 덮는 실린더형의 유전막(218)을 형성한다. Referring to Figure 8d, the large dielectric constant of tantalum oxide (Ta 2 O 5) or PZT ((Pb, Zr) TiO 3), BST ((Ba, Sr) TiO 3), using a ferroelectric such as STO (SrTiO 3) to thereby form a dielectric film 218 of the cylindrical covering the cylindrical lower electrode (214).

도 8e를 참조하면, 상기 유전막(218) 상부에 상부전극(220)을 형성한다. Referring to Figure 8e, to form a top electrode 220 on top of the dielectric layer 218. 상기 상부전극(220)은 반응성 금속(A), 질소(N), 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위한 비정질 결합용 원소(B)가 원자층 증착법에 의하여 서로 교대로 적층된 상태로 배열된 도전층이다. The upper electrode 220 is a reactive metal (A), nitrogen (N), and in the stacked state to the reactive metal, and for amorphous bonding to prevent crystallization of the nitrogen element (B) with each other alternately by atomic layer deposition It is arranged in the conductive layer. 상기 상부전극(220)의 각 원자층의 조성비는 각 원자층의 적층회수에 의하여 결정되고, 상기 각 원자층 중 비정질 결합용 원소에 의한 원자층의 적층회수의 비율에 따라 상부전극의 전기전도도 및 저항을 적절히 결정할 수 있다. The composition ratio of the atomic layer of the upper electrode 220 is determined by the stacking number of each atomic layer, and the electric conductivity of the upper electrode according to the ratio of the stacked number of atomic layers of the amorphous coupling element for the above each atomic layer It can be appropriately determined resistance. 상기 반응성 금속(A)은 Ti, Ta, W, Zr, Hf, Mo, Nb를 포함한다. And the reactive metal (A) comprises a Ti, Ta, W, Zr, Hf, Mo, Nb. 상기 반응성 금속 및 질소의 결정화를 방지하기 위한 비정질 결합용 원소(B)는 Al, Si, B를 포함한다. And the reactive metal and the element (B) for amorphous bonding to prevent crystallization of nitrogen comprises an Al, Si, B.

본 실시예에서는 상기 상부전극(220)을 TiAlN 층으로 형성한다. In this embodiment, to form the upper electrode 220 with TiAlN layer. 상기 금속층이 TiAlN층인 경우, Ti 소스가스는 TiCl 4 , TDMAT(Tetrakis DeMethyl Amino Titanium), TDEAT(Tetrakis DeEthyl Amino Titanium) 중에서, Al 소스가스는 TMA(TriMethyl Aluminum), TEA(TriEthyl Aluminum), TIBA(Tri-I-Buthyl Aluminum), AlClx 중에서, 그리고 질소(N)의 소스가스로는 N 2 , NH 3 중에서 선택된 어느 하나를 사용할 수 있다. When the metal layer TiAlN, Ti source gas comprises TiCl 4, TDMAT (Tetrakis DeMethyl Amino Titanium), TDEAT (Tetrakis DeEthyl Amino Titanium) from, Al source gas TMA (TriMethyl Aluminum), TEA ( TriEthyl Aluminum), TIBA (Tri among -I-Buthyl Aluminum), AlClx, and the source gas of nitrogen (N) may be any one selected from the group consisting of N 2, NH 3.

구체적으로, 상기 상부전극(220)은 다음과 같은 방법에 의하여 형성된다. Specifically, the upper electrode 220 is formed by the method described below.

원자층 증착챔버 내로의 상기 삼원계 질소화물의 각 소스가스의 공급시 각 소스가스들은 펄스형태로 서로 교번하면서 주입됨으로써 반도체 기판(104) 상의 고유전막(218) 상부에 각 원소층을 적층하여 형성한다. Each source gas for supply of each of the source gas of a ternary nitride into an atomic layer deposition chamber are formed by laminating each element layer on the inherent conductor film 218 on the semiconductor substrate 104 by being implanted while alternating with each other in pulse form do.

상기 상부전극(220)으로서 TiAlN층을 구성하기 위하여 반응성 금속(Ti), 질소(N), 및 비정질 결합용 원소(Al)의 각 소스가스들, TiCl 4 , TMA, NH 3 을 펄스형태로공급하여 상기 고유전막(218) 상에 상기 소스가스들을 화학적으로 흡착시켜 복수의 원자층을 구성한다. Of the upper electrode 220 as a respective source of a reactive metal (Ti), nitrogen (N), and amorphous bonding element (Al) for to form a TiAlN layer gas, TiCl 4, TMA, supplying the NH 3 into a pulse form to the specific conductive film by adsorbing said gas on the source 218 to the chemical make up a plurality of atomic layers. 또한 상기 상부전극(220)은, 각 소스가스들이 서로 교번되면서 공급되도록 순서가 결정되어 각 대응 원자층이 서로 교대로 배열되는 구성을 가진다. In addition, the upper electrode 220, the order is determined such that as each supplied source gases are alternated with each other has a configuration which is arranged to each other, each corresponding to an atomic layer alternately. 상기 각 소스가스의 주입회수를 적절히 조절하는 것에 의하여 상기 상부전극(220)을 구성하는 Ti, Al, 및 N의 각 조성비를 적절히 결정하고, 상기 각 조성비를 적절히 결정함에 의하여 필요한 전기전도도 및 저항을 적절히 결정할 수 있는 구성을 가진다. By being appropriately adjusting the injection number of times for each of the source gas, and suitably determined in each composition ratio of Ti, Al, and N constituting the upper electrode 220, the electrical conductivity and resistance required by as properly determining the respective compositions It has a configuration that can be determined appropriately.

조성의 조절의 예는 도 1a, 1b, 2a, 2b를 참조로 하여 상기에서 설명한 예들이 적용될 수 있고, 원자층의 증착시 증착조건도 동일하기 적용될 수 있다. The composition of the control example may be applied to the example described above with the Figure 1a, 1b, 2a, 2b by reference, may be applied to the same degree the deposition conditions during deposition of an atomic layer.

퍼지작업도, 도 1a 및 도 2a 에서 처럼 상기 소스가스의 주입 중에 퍼지가스를 온오프없이 연속적으로 계속 주입하여 퍼지작업을 수행할 수 있고, 도 1b 및 도 2b에서 처럼 상기 소스가스의 주입 펄스 사이에 퍼지가스에 의한 퍼지작업을 수행할 수 있다. Between the purge operation also, it is possible to continuously keep the injection into a purge gas without on-off during the injection of the source gas, as shown in Figure 1a and 2a to perform the purge operation, the injection pulse of the source gas as in FIG. 1b and 2b the purge operation can be performed by the purge gas. 이 때 퍼지가스로는 Ar, N 2 , He, H 2 등의 가스가 사용된다. At this time, the purge gas is a gas such as Ar, N 2, He, H 2 is used.

본 실시예에서의 실린더형 커패시터의 경우에서와 같이 복잡한 구성의 상부전극을 증착할 때에도 상부전극의 스텝커버리지가 매우 우수하여 유전율이 높고 전기적 신뢰성이 우수한 커패시터를 제조할 수 있다. Even when depositing a top electrode of a complicated configuration as in the case of cylindrical capacitors in this embodiment a high dielectric constant to the step coverage of the upper electrode excellent capacitor can be manufactured with excellent electrical reliability.

상술한 바와 같이 본 실시예에서는 상부전극 형성시 각각의 원자층을 순서대로 흡착하여 형성하므로 CVD법에 비하여 조성비의 조절이 용이하며 조성의 재현성이 뛰어나다. In this embodiment as described above it is easy to control the composition ratio compared with the CVD method, so formed by the adsorption layer when the individual atoms forming the upper electrode in order, and excellent in reproducibility of the composition. 즉, 상부전극을 구성하는 각 소스가스들의 펄스 주입순서 및 회수를 조절하는 것만에 의하여 상부전극의 조성을 용이하게 조절할 수 있게 됨으로써, 상부전극의 전기전도도 및 저항을 필요에 따라 매우 용이하게 조절할 수 있다. That is, it is possible by being able to, by simply adjusting the pulse injection sequence and withdrawal of the respective source gas constituting the upper electrode easily adjust the composition of the upper electrode, it is very easy, as needed for electrical conductivity and resistivity of the upper electrode to adjust . 또한, 각 소스가스들의 펄스 주입순서 및 회수를 조절하는 것만에 의하여 조성을 조절할 수 있게 되므로, 조성의 재현성이 뛰어난 특성을 가진다. In addition, since the composition can be adjusted by simply controlling the injection pulse sequence, and recovery of each of the source gas, the reproducibility of the composition has excellent properties.

실시예 3 Example 3

본 실시예 3에서는 도 9a 내지 9e를 참조로 하여, 원자층 증착법을 이용하여 형성된 금속층으로 하부전극으로 채용한 트렌치형 커패시터에 관하여 설명한다. In the third embodiment even if the 9a to 9e by reference, using the atomic layer deposition method will be described with respect to a trench capacitor employed as a lower electrode is formed by metal layers.

도 9a를 참조하면, 반도체기판(104) 상에 실리콘 산화막(SiO 2 )으로 구성된 절연층(310)을 형성한다. Referring to Figure 9a, to form an insulating layer composed of a silicon oxide film (SiO 2) on a semiconductor substrate 104 (310). 이어서, 상기 절연층(310) 내에 사진식각공정을 이용하여 콘택홀을 형성한다. Then, using a photolithography process in the insulator layer 310 to form a contact hole.

도 9b를 참조하면, 트렌치형 커패시터를 형성하기 위하여 상기 콘택홀의 내부는 필요에 따라, 예컨대 필요한 커패시턴스에 따라, 매립하지 않을 수도 있고 소정의 깊이까지 일부분 매립할 수도 있다. Referring to Figure 9b, the inner hole of the contact so as to form a trench capacitor, as needed, for example, according to the required capacitance may not be filled or may be embedded in a portion to a predetermined depth. 일부분 매립시 콘택홀 내에 폴리실리콘을 매립한 다음 습식식각 또는 화학 기계적 연마와 결합된 습식식각을 수행하여 콘택홀의 하부에 소정의 높이까지만 폴리실리콘막(312)을 남긴다. By filling the polysilicon in a contact hole during a portion embedded in and then by performing the wet etching combined with a wet etch or chemical mechanical polishing to leave the polysilicon film 312 only up to a predetermined height in the contact hole bottom.

도 9c를 참조하면, 상기 폴리실리콘막(312)을 포함한 절연층 상부에 하부전극(314)을 형성한다. Referring to Figure 9c, to form a lower electrode 314 on the upper insulating layer including the polysilicon film 312. 상기 하부전극(314)은 실시예 1의 상부전극(220)과 유사한 방법으로 형성된다. The lower electrode 314 is formed in a manner similar to the upper electrode 220 of the first embodiment.

즉, 상기 하부전극(314)은, 반응성 금속(A), 질소(N), 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위한 비정질 결합용 원소(B)가 원자층 증착법에 의하여 서로 교대로 적층된 상태로 배열된 도전층이다. That is, the lower electrode 314, a reactive metal (A), nitrogen (N), and the reactive metal and the amorphous coupling element (B) are stacked with each other alternately by atomic layer deposition method for for preventing the crystallization of the N a conductive layer arranged in a state. 상기 하부전극(312)의 각 원자층의 조성비는 각 원자층의 적층회수에 의하여 결정되고, 상기 각 원자층 중 비정질 결합용 원소에 의한 원자층의 적층회수의 비율에 따라 상부전극의 전기전도도 및 저항을 적절히 결정할 수 있다. The composition ratio of the atomic layer of the lower electrode 312 is determined by the stacking number of each atomic layer, and the electric conductivity of the upper electrode according to the ratio of the stacked number of atomic layers of the amorphous coupling element for the above each atomic layer It can be appropriately determined resistance.

상기 반응성 금속(A) 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위한 비정질 결합용 원소(B)를 구성하는 물질의 예도 실시예 2의 경우와 마찬가지이다. The reactive metal (A) and the same as those of the above-described reactive metal and examples of the material constituting the element (B) for amorphous bonding to prevent crystallization of nitrogen Example 2.

본 실시예에서, 상기 하부전극(314)은 실시예 2의 상부전극(220)과 마찬가지로 TiAlN 층으로 형성하고, 소스가스도 Ti 소스가스는 TiCl 4 , TDMAT(Tetrakis DeMethyl Amino Titanium), TDEAT(Tetrakis DeEthyl Amino Titanium) 중에서, Al 소스가스는 TMA(TriMethyl Aluminum), TEA(TriEthyl Aluminum), TIBA(Tri-I-Buthyl Aluminum), AlClx 중에서, 그리고 질소(N)의 소스가스로는 N 2 , NH 3 중에서 선택된 어느 하나를 사용한다. In this embodiment, the lower electrode 314 is the second embodiment, like the upper electrode 220 of forming a TiAlN layer, source gas is Ti source gas comprises TiCl 4, TDMAT (Tetrakis DeMethyl Amino Titanium), TDEAT (Tetrakis among DeEthyl Amino Titanium), Al source gas in the source gas of TMA (TriMethyl Aluminum), TEA ( TriEthyl Aluminum), TIBA (Tri-I-Buthyl Aluminum), from AlClx, and nitrogen (N) are N 2, NH 3 It uses at least one selected.

상기 하부전극(314)은 다음과 같은 방법에 의하여 형성된다. The lower electrode 314 is formed by the method described below. 하부전극(314)은 상기 실시예 2의 상부전극(220)의 형성방법과 유사하다. The lower electrode 314 is similar to the method for forming the upper electrode 220 of the second embodiment.

상기 하부전극(314)으로서 TiAlN층을 구성하기 위하여 반응성 금속(Ti), 질소(N), 및 비정질 결합용 원소(Al)의 각 소스가스들, TiCl 4 , TMA, NH 3 을 펄스형태로 공급하여 상기 고유전막(218) 상에 상기 소스가스들을 화학적으로 흡착시켜 복수의 원자층을 구성한다. Reactive metals (Ti) to form a TiAlN layer as the lower electrode 314, a nitrogen (N), and each of the source gas of the amorphous binding element (Al) for, TiCl 4, TMA, supplying the NH 3 into a pulse form to the specific conductive film by adsorbing said gas on the source 218 to the chemical make up a plurality of atomic layers.

또한 상기 하부전극(314)은, 각 소스가스들이 서로 교번되면서 공급되도록순서가 결정되어 각 대응 원자층이 서로 교대로 배열되는 구성을 가진다. In addition, the lower electrode 314, the order is determined such that as each supplied source gases are alternated with each other has a configuration which is arranged to each other, each corresponding to an atomic layer alternately. 상기 각 소스가스의 주입회수를 적절히 조절하는 것에 의하여 상기 하부전극(314)을 구성하는 Ti, Al, 및 N의 각 조성비를 적절히 결정하고, 상기 각 조성비를 적절히 결정함에 의하여 필요한 전기전도도 및 저항을 적절히 결정할 수 있는 구성을 가진다. By being appropriately adjusting the injection number of times for each of the source gas, and suitably determined in each composition ratio of Ti, Al, and N constituting the lower electrode 314, the electrical conductivity and resistance required by as properly determining the respective compositions It has a configuration that can be determined appropriately.

조성의 조절의 예는 도 1a, 1b, 2a, 2b를 참조로 하여 상기에서 설명한 예들이 적용될 수 있고, 원자층의 증착시 증착조건도 동일하기 적용될 수 있다. The composition of the control example may be applied to the example described above with the Figure 1a, 1b, 2a, 2b by reference, may be applied to the same degree the deposition conditions during deposition of an atomic layer.

퍼지작업도, 도 1a 및 도 2a 에서 처럼 상기 소스가스의 주입 중에 퍼지가스를 온오프없이 연속적으로 계속 주입하여 퍼지작업을 수행할 수 있고, 도 1b 및 도 2b에서 처럼 상기 소스가스의 주입 펄스 사이에 퍼지가스에 의한 퍼지작업을 수행할 수 있다. Between the purge operation also, it is possible to continuously keep the injection into a purge gas without on-off during the injection of the source gas, as shown in Figure 1a and 2a to perform the purge operation, the injection pulse of the source gas as in FIG. 1b and 2b the purge operation can be performed by the purge gas. 이 때 퍼지가스로는 Ar, N 2 , He, H 2 등의 가스가 사용된다. At this time, the purge gas is a gas such as Ar, N 2, He, H 2 is used.

상기한 바와 같이 소정의 회수의 원자층을 증착한 후, 포토레지스트 패턴 등과 같은 마스크를 이용하여 필요한 패턴의 하부전극(314)을 형성한다. To form a lower electrode 314 of the pattern required by the mask, such as after deposition of atomic layers of a predetermined number of times, the photoresist pattern as described above.

도 9d를 참조하면, 유전율이 큰 탄탈륨산화막(Ta 2 O 5 ) 또는 PZT((Pb,Zr)TiO 3 ), BST((Ba,Sr)TiO 3 ), STO(SrTiO 3 ) 등과 같은 강유전체를 사용하여, 상기 트렌치형 하부전극(314)을 덮는 트렌치형의 유전막(318)을 형성한다. Referring to Figure 9d, the large dielectric constant of tantalum oxide (Ta 2 O 5) or PZT ((Pb, Zr) TiO 3), BST ((Ba, Sr) TiO 3), using a ferroelectric such as STO (SrTiO 3) to thereby form the dielectric layer 318 of the trench to cover the trench-type lower electrode 314.

도 9e를 참조하면, 상기 고유전막(318) 상부에 상부전극(320)을 형성한다. Referring to Figure 9e, to form a top electrode 320 on top of the specific conductive film 318. 상기 상부전극(320)은 열처리 공정시 하부의 고유전막(318)에 의한 산화를 방지하기 위하여 TiN, TaN 등을 이용하여 장벽층의 역할을 하는 금속층(320a)을 형성하고, 그 상부에 폴리실리콘층(320b)을 형성한다. The upper electrode 320 is a polysilicon to TiN, the upper part, and by using the TaN including forming a metal layer (320a) which acts as a barrier layer in order to prevent oxidation due to the unique conductive film 318 of the lower part during the heat treatment process to form a layer (320b).

선택적으로, 상기 상부전극(320)은, 상기 금속층(320a) 및 폴리실리콘층(320b)으로 형성하는 대신에, 반응성 금속(A), 질소(N), 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위한 비정질 결합용 원소(B)로 구성된 금속층, 예컨대 TiAlN층으로 형성할 수 있다. Alternatively, the upper electrode 320, instead of forming a metal layer (320a) and the polysilicon layer (320b), a reactive metal (A), nitrogen (N), and prevent crystallization of the reactive metal and a nitrogen a metal layer composed of the element (B) for binding to amorphous, for example, can be formed of a TiAlN layer. 이 때, 트렌치형의 고유전막(318)의 스텝커버리지를 우수하게 하기 위하여 상부전극(320) 형성시 상기 하부전극(314) 형성시와 마찬가지로 원자층 증착법을 이용하여 형성하는 것도 바람직하다. At this time, it is also preferable to form by using the atomic layer deposition method like the upper electrode 320 when forming the lower electrode 314 during the formation in order to make excellent the step coverage of the specific conductive film 318 of the trench.

상기한 바와 같이 하부전극(314)을 원자층 증착법에 의하여 형성된 TiAlN 층으로 구성하면, 상기 TiAlN층이 내열성 및 내산화성이 높으므로 장벽금속층으로서의 역할을 충분히 하므로 하부전극(314) 아래에 접하는 폴리실리콘층(312) 또는 실리콘 기판(104)과의 사이에 별도의 장벽층을 형성할 필요가 없으므로 공정이 단순화된다. When constituting the lower electrode 314 as described above and TiAlN layer is formed by atomic layer deposition, the poly is the TiAlN layer, so enough to serve as the barrier metal layer has higher heat resistance and oxidation resistance in contact below the lower electrode 314, a silicon the process is simplified since there is no need to form an additional barrier layer between the layer 312 or the silicon substrate (104).

또한 하부전극(314) 형성시 각각의 원자층을 증착하여 형성하므로 매우 콤팩트한 영역에서도 스텝커버리지가 우수하다. It is also an excellent step coverage even in a very compact area so formed by depositing each atomic layer lower electrode 314 during the formation. 따라서, 본 실시예에서의 트렌치형 커패시터의 경우에서와 같이 종횡비가 높은 복잡한 구성의 하부전극을 증착할 때에도 하부전극의 스텝커버리지가 매우 우수하여 유전율이 높고 전기적 신뢰성이 우수한 커패시터를 제조할 수 있다. Therefore, it is possible to, even when the aspect ratio of depositing the lower electrode of high complex configuration with high dielectric constant, the step coverage of the lower electrode by excellent manufacturing excellent capacitor electrical reliability as in the case of a trench capacitor according to the embodiment.

또한, 하부전극 형성시 각각의 원자층을 순서대로 흡착하여 형성하므로 CVD법에 비하여 조성비의 조절이 용이하며 조성의 재현성이 뛰어나다. Further, by forming the lower electrode of each atomic layer when forming the adsorption sequence it is easy to control the composition ratio compared with the CVD method and excellent in reproducibility of the composition. 즉, 상부전극을 구성하는 각 소스가스들의 펄스 주입순서 및 회수를 조절하는 것만에 의하여 상부전극의 조성을 용이하게 조절할 수 있게 됨으로써, 상부전극의 전기전도도 및 저항을 필요에 따라 매우 용이하게 조절할 수 있다. That is, it is possible by being able to, by simply adjusting the pulse injection sequence and withdrawal of the respective source gas constituting the upper electrode easily adjust the composition of the upper electrode, it is very easy, as needed for electrical conductivity and resistivity of the upper electrode to adjust . 또한, 각 소스가스들의 펄스 주입순서 및 회수를 조절하는 것만에 의하여 조성을 조절할 수 있게 되므로, 조성의 재현성이 뛰어난 특성을 가진다. In addition, since the composition can be adjusted by simply controlling the injection pulse sequence, and recovery of each of the source gas, the reproducibility of the composition has excellent properties.

본 발명의 제2 태양에 따른 원자층 증착법을 이용한 금속층 형성방법 The method of forming the metal layer by atomic layer deposition according to the second aspect of the present invention

도 10은 본 발명의 제2 태양에 따른 원자층 증착법을 이용한 금속층 형성방법을 설명하기 위한 단면도이고, 도 11은 도 10의 내산화층 형성시 원자층 증착을 위한 소스가스들 및 퍼지가스의 주입방법의 예를 나타내는 그래프이다. 10 is a injection method of the source gas and the purge gas for the second aspect sectional view, and FIG. 11 in the oxide layer formed during the atomic layer deposition in Figure 10 illustrating a metal layer forming method using the atomic layer deposition method according to the invention of a graph of an example.

도 10을 참조하면, 본 발명의 제2 태양에 따른 원자층 증착법을 이용한 금속층은 다중 금속층(405)이다. 10, the metal layer by atomic layer deposition according to the second aspect of the invention is a multi-metal layer (405). 상기 다중 금속층(405)은 금속층(401)과 산소 확산 방지층(403)이 복수회 적층된 2층 구조로 구성된다. The multi-metal layer 405 is a metal layer 401 and the oxygen diffusion barrier layer 403 is composed of a plurality of times the laminated two-layer structure. 상기 금속층(401)과 산소 확산 방지층(403)은 원자층 증착 장비를 이용하여 인시츄로 형성한다. The metal layer 401 and the oxygen diffusion barrier layer 403 is formed by in-situ by using the atomic layer deposition equipment. 상기 산소 확산 방지층(403)은 전자의 흐름이 방해되지 않도록 얇은 두께, 예컨대 5-15Å의 두께로 형성한다. The oxygen diffusion barrier layer 403 is formed to a small thickness, for example, a thickness of 5-15Å not to interfere with the flow of electrons.

구체적으로, 상기 금속층(401)은 제1 태양의 금속층 형성방법에서 설명한 바와 동일하게 형성된다. Specifically, the metal layer 401 is formed in the same manner as described in the metal layer forming method of the first aspect. 다시 말하면, 상기 금속층(401)은 반응성 금속(A), 질소(N) 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위한 비정질결합용 원소(B)가 원자층 증착법에 의하여 서로 교대로 적층된 상태로 배열된 ABN 구조로 형성한다. The other words, the laminated in the metal layer 401 is a reactive metal (A), nitrogen (N) and the reactive metal and the element for the amorphous bond (B) with each other alternately by atomic layer deposition method for preventing the crystallization of the nitrogen status It is formed in a structure arranged in ABN. 즉, 상기 금속층(401)은 반도체 기판(도시 안함) 상에 반응성 금속(A), 질소(N) 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위한 비정질결합용 원소(B)의 각 소스가스를 펄스형태로 서로 교번되도록 순서를 정하여 공급하고, 조성비를 조절하게끔 상기 각 소스가스의 주입회수를 조절하면서 공급하여 상기 반도체 기판 상에 화학흡착시킴으로써 ABN 구조로 형성된다. That is, each of the source gas of the metal layer 401 is a semiconductor substrate reactive metal (A), nitrogen (N) and an element (B) for amorphous bonding to prevent crystallization of the reactive metal and nitrogen in the (not shown) alternating with each other to form a pulse sequence appointed to supply, and by chemical adsorption onto the semiconductor substrate was supplied while adjusting the number of the injection for each of the source gas hagekkeum adjusting the composition ratio is formed from a structure ABN.

상기 반응성 금속(A)은 Ti, Ta, W, Zr, Hf, Mo, Nb 등이 사용되고, 상기 비정질 결합용 원소(B)는 Al, Si, B 등이 사용된다. The reactive metal (A) is such as Ti, Ta, W, Zr, Hf, Mo, Nb is used, the combination of the amorphous element (B) for the Al, Si, B or the like is used. 상기 금속층(401)의 형성시 공정 조건, 예컨대 증착 온도, 소스 가스 등은 제1 태양의 금속층 형성 방법과 동일하게 하게 조절한다. The metal layer 401 is formed upon process conditions, such as deposition temperature, the source gas or the like is adjusted to the same as the metal layer forming method of the first aspect. 본 태양에서는 상기 금속층(401)을 TiAlN층으로 형성한다. In this aspect to form the metal layer 401 as a TiAlN layer.

다음에, 상기 금속층(401) 상에는 원자층 증착법을 이용하여 산소 확산 방지층(403)을 형성한다. Next, using the metal layer 401 formed on the atomic layer deposition to form an oxygen diffusion barrier layer (403). 상기 산소 확산 방지층(403)은 외부로부터 확산하는 산소의 침투를 방지할 수 있다. The oxygen diffusion barrier layer 403 can prevent the penetration of oxygen from diffusing from the outside. 상기 산소 확산 방지층(403)은 상기 금속 원소, 예컨대 알루미늄 소스 및 산소 소스를 도 11과 같이 펄스 형태로 서로 교번되도록 공급하여 상기 금속층(401) 상에 산소 확산 방지층을 형성한다. The oxygen diffusion barrier layer 403 to form the metal elements, such as oxygen diffusion barrier layer on the metal layer 401 is supplied to a pulse type alternating with each other as shown in Figure 11 an aluminum source and an oxygen source. 본 태양에서는 상기 산소 확산 방지층으로 알루미늄 산화막을 이용한다. In this aspect it utilizes aluminum oxide as the oxygen diffusion barrier layer. 상기 알루미늄 산화막 형성시 알루미늄 소스 가스는 TMA(TriMethyl Aluminum), TEA(TriEthyl Aluminum), TIBA(Tri-I-Buthyl Aluminum) 또는 AlClx를 이용하며, 상기 산소 소스 가스로는 O 2 , N 2 O를 이용하고, 퍼지 가스로는 아르곤, 질소 또는 헬륨 가스를 이용한다. The aluminum oxide layer formed when the aluminum source gas using a TMA (TriMethyl Aluminum), TEA ( TriEthyl Aluminum), TIBA (Tri-I-Buthyl Aluminum) or AlClx, and the oxygen source gas, and use of O 2, N 2 O , the purge gas used is argon, nitrogen or helium gas.

이렇게 형성되는 다중 금속층(405)은 제1 태양에서 설명한 바와 같이 내열성 및 내산화성이 좋은 금속층(401) 내부(금속층과 금속층 사이)에 산소 확산 방지층(403)이 추가로 형성되어 내열성 및 내산화성을 더욱더 향상시킬 수 있다. This multi-metal layer 405 is formed is formed of a heat-resistant and oxygen diffusion barrier layer 403 on the inside (between the metal layer and the metal layer), oxidation resistance, good metal layer 401 is added as described in the first aspect of heat resistance and oxidation resistance, It can be further improved. 다시 말하면, 제1 태양에 의한 금속층은 표면에서 산화층이 형성되어 산소의 확산을 방지하나, 제2 태양에 의한 다중 금속층(405)은 표면 및 내부에 산소 확산 방지층(403)이 형성되어 산소의 확산을 확실하게 방지한다. In other words, the first metal layer by the sun is the oxide layer on the surface is formed on one prevent the diffusion of oxygen, a second multi-metal layer 405 due to the sun is an oxygen diffusion barrier layer 403 on the inside and the surface is formed on the diffusion of oxygen to be reliably prevented.

본 발명의 제3 태양에 따른 원자층 증착법을 이용한 금속층 형성방법 The method of forming the metal layer by atomic layer deposition according to the third aspect of the present invention

도 12 및 도 13은 본 발명의 제3 태양에 따른 원자층 증착법을 이용한 금속층 형성방법을 설명하기 위한 단면도이다. 12 and 13 are cross-sectional views illustrating a metal layer forming method using the atomic layer deposition according to the third aspect of the present invention.

먼저, 본 발명의 제3 태양에 따른 원자층 증착법을 이용한 금속층은 도 13에 도시된 바와 같이 다중 금속층(507)이다. First, a multi-metal layer 507. The metal layer as shown in Figure 13 using the atomic layer deposition according to the third aspect of the present invention. 다만, 제3 태양에 따른 다중 금속층(507)은 제2 태양과 비교하여 금속층(501), 산소 확산 방지층(503) 및 물질층(505)의 3층 구조가 복수회 적층되어 있고, 산소 확산 방지층(503)을 후술하는 바와 같이 열처리에 의하여 자연적으로 형성한다. However, the multi-metal layer 507 according to the third aspect is the second, and the three-layer structure in relation to the sun metal layer 501, the oxygen diffusion barrier layer 503 and the material layer 505 are laminated a plurality of times, the oxygen diffusion barrier layer It is formed naturally by the heat treatment as described later to 503.

다음에, 본 발명의 제3 태양에 따른 원자층 증착법을 이용한 금속층 형성방법을 설명한다. Next, the metal layer forming method using the atomic layer deposition according to the third aspect of the present invention.

도 12를 참조하면, 기판(도시 안함) 상에 금속층(501)을 형성한다. 12, to form a metal layer 501 on a substrate (not shown). 상기 금속층(501)은 제1 태양의 금속층 형성방법에서 설명한 바와 동일하게 형성된다. The metal layer 501 is formed in the same manner as described in the metal layer forming method of the first aspect. 다시 말하면, 상기 금속층(501)은 반응성 금속(A), 질소(N) 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위한 비정질결합용 원소(B)가 원자층 증착법에 의하여 서로 교대로 적층된 상태로 배열된 ABN 구조로 형성한다. The other words, the metal layer 501 is deposited to a reactive metal (A), nitrogen (N) and the reactive metal and the element for amorphous bonding to prevent crystallization of nitrogen (B) with each other alternately by atomic layer deposition conditions It is formed in a structure arranged in ABN. 상기 반응성 금속(A)은 제1 태양과 동일하게 Ti, Ta, W, Zr, Hf, Mo, Nb 등이 사용되고, 상기 비정질 결합용 원소(B)는 Al, Si, B 등이 사용된다. Wherein the reactive metal (A) is the first in the same manner as in the sun, such as Ti, Ta, W, Zr, Hf, Mo, Nb is used, the amorphous coupling element (B) for the Al, Si, B or the like is used. 상기 금속층(501)의 형성시 공정 조건, 예컨대 증착 온도, 소스 가스 등은 제1 태양 및 제2 태양의 금속층 형성 방법과 동일하게 하게 조절한다. The metal layer 501 is formed upon process conditions, such as deposition temperature, the source gas or the like is adjusted to the same as the metal layer forming method of the first aspect and the second aspect. 본 태양에서는 상기 금속층(501)을 TiAlN층으로 형성한다. In this aspect to form the metal layer 501 in the TiAlN layer.

다음에, 상기 금속층(501) 상에 산소가 포함된 물질층(505)을 형성한다. Next, to form the metal layer 501 material layer 505 containing oxygen onto. 상기 물질층(505)은 원자층 증착법을 이용하여 형성하는데, 본 태양에서는 TiON막으로 형성한다. The material layer 505 is to form by using the atomic layer deposition method, in this aspect to form the TiON film. 즉, 원자층 증착 챔버에 타이타늄, 산소 및 질소의 각 소스가스를 펄스형태로 서로 교번되도록 순서를 정하여 공급함으로써 상기 TiON막을 형성한다. That is, by an appointed alternating with each other in order to feed the respective source gases of titanium, oxygen and nitrogen in an atomic layer deposition chamber in a pulse form to form the TiON film.

도 13을 참조하면, 상기 금속층(501) 및 물질층(505)이 형성된 반도체 기판을 열처리하여 상기 금속층(501)과 물질층(505) 사이에 산소 확산 방지층(503)을 형성한다. 13, to form the metal layer 501 and the material layer 505, the metal layer by heat-treating a semiconductor substrate having (501) and the oxygen diffusion barrier layer (503) between the material layer 505. 상기 산소 확산 방지층(503)은 상기 금속층(501)의 금속 물질과 물질층(505)의 산소가 반응하여 형성된다. The oxygen diffusion barrier layer 503 is formed by the reaction of oxygen of the metal material and the material layer 505 of the metal layer 501. 예컨대, 상기 금속층(501)을 TiAlN막으로 형성하고 상기 물질층(505)을 TiON막으로 형성할 경우, 상기 금속층(501)의 알루미늄이 표면으로 이동하여 상기 물질층(505)의 산소와 반응하여 알루미늄 산화막으로 산소 확산 방지층(503)이 형성된다. For example, when forming the metal layer 501 in the TiAlN film, and to form the material layer 505 as TiON film, react with the oxygen of the aluminum of the metal layer 501 migrate to the surface the material layer 505 the oxygen diffusion barrier layer 503 is formed of aluminum oxide. 결과적으로, 제3 태양에 따른 다중 금속층(507)은 금속층(501), 산소 확산 방지층(503) 및 물질층(507)의 3층 구조가 복수회 적층된다. Consequently, the multi-metal layer 507 according to the third aspect is a metal layer 501, a three-layer structure of the oxygen-diffusion barrier layer 503 and the material layer 507 is deposited a plurality of times.

이렇게 형성되는 다중 금속층은 제1 태양에서 설명한 바와 같이 내열성 및 내산화성이 좋은 금속층(501) 내(금속층과 금속층 사이)에 산소 확산 방지층(503)이 추가로 형성되어 내열성 및 내산화성을 더욱더 향상시킬 수 있다. This multi-metal layer to be formed is to the heat resistance and the oxidation resistance is good metal layer 501 the oxygen diffusion barrier layer 503 (between the metal layer and the metal layer) is formed further more improving the heat resistance and oxidation resistance, as described in the first aspect can.

이하에, 본 발명의 제2 및 제3 태양에 따라 원자층 증착법을 이용하여 형성된 금속층을 장벽금속층으로 구비한 반도체 소자의 제조방법을 도 14 및 도 15를 이용하여 상세히 설명한다. In the following, using the second and the third one 14 and 15 a method of manufacturing a semiconductor device having a metal layer formed by using the atomic layer deposition method according to the aspect as a barrier metal layer of the present invention will be described in detail.

도 14를 참조하면, 반도체 기판(601) 상에 실리콘 산화막(SiO 2 )으로 구성된절연층(603)을 형성한다. 14, to form an insulating layer composed of a silicon oxide film (SiO 2) on a semiconductor substrate 601 (603). 이어서, 상기 절연층(603) 내에 사진식각공정을 이용하여 콘택홀을 형성한다. Then, using a photolithography process in the insulator layer 603 to form a contact hole. 계속하여, 상기 콘택홀의 내부의 일정 높이까지 폴리실리콘막으로 도전성 물질막인 플러그(605)를 형성한다. Subsequently, and up to a certain height within the contact hole formed in the plug 605, a conductive material layer into a polysilicon film. 상기 플러그(605)는 폴리실리콘을 매립한 다음 습식식각 또는 화학 기계적 연마와 결합된 습식식각을 수행하여 콘택홀의 하부에 소정의 높이까지만 폴리실리콘막을 남김으로써 형성할 수 있다. The plug 605 by a buried polysilicon and then performing a wet etching combined with a wet etch or chemical mechanical polishing to form a contact hole by leaving the lower polysilicon film is only up to a predetermined height.

도 15를 참조하면, 상기 플러그(605)가 형성된 반도체 기판(601)의 전면에 금속층을 형성한 후 에치백 또는 화학기계적연마하여 상기 콘택홀을 메우는 장벽 금속층(607)을 형성한다. Referring to Figure 15, to form the plug 605 is formed of a barrier metal layer 607 to the front after the formation of the metal layer etch-back or CMP to fill the contact hole of the semiconductor substrate 601. 상기 장벽 금속층(607)은 본 발명의 제2 태양 및 제3 태양에 의한 금속층 형성 방법으로 형성한다. The barrier metal layer 607 is formed of a metal layer forming method of the second aspect and the third aspect of the present invention. 즉, 상기 장벽 금속층(607)은 원자층 증착법을 이용하여 반응성 금속(A)-비정질 결합용 원소(B)- 질소(N) 구조의 금속층과 5∼15Å 두께의 산소 확산 방지층이 복수회, 예컨대 3-10회 적층된 2층 구조의 다중 금속층으로 형성하거나, ABN 구조의 금속층, 산소 확산 방지층 및 물질층의 3층 구조가 복수회, 예컨대 3-10회 적층된 다중 금속층으로 형성한다. That is, the barrier metal layer 607 by using the atomic layer deposition reactive metal (A) - amorphous coupling element (B) for - a plurality of oxygen diffusion barrier layer of the metal layer and the thickness of the 5~15Å nitrogen (N) structure times, e.g. forming a metal layer of 3 to 10 multiple times a laminated two-layer structure, or be a three-layer structure of a metal layer structure of ABN, the oxygen diffusion barrier layer and a material layer formed of a multi-metal layer a plurality of times, for example 3-10 times laminated.

상기 반응성 금속(A)은 Ti, Ta, W, Zr, Hf, Mo, Nb 등이 사용되고, 상기 비정질 결합용 원소(B)는 Al, Si, B 등이 사용된다. The reactive metal (A) is such as Ti, Ta, W, Zr, Hf, Mo, Nb is used, the combination of the amorphous element (B) for the Al, Si, B or the like is used. 본 실시예에서는 상기 금속층을 TiAlN층으로 형성하여, 50∼500Å의 두께로 형성한다. In this embodiment, by forming the metal layer with TiAlN layer, it is formed to have a thickness of 50~500Å. 이렇게 장벽 금속층(607)을 다중 금속층으로 형성할 경우, 후속하는 열처리 공정시 플러그의 산화를 더욱 확실하게 방지할 수 있다. So the case of forming a barrier metal layer 607 with multiple metal layers, a subsequent heat treatment process which can prevent oxidation of the plug more reliably.

다음에, 상기 장벽 금속층(607)이 형성된 반도체 기판(601) 상에 하부 전극(609)을 형성한다. Next, to form a lower electrode 609 on the barrier metal layer the semiconductor substrate 601, 607 is formed. 상기 하부 전극(609)은 백금(Pt), 루테늄(Ru), 이리듐(Ir)이나, 산화 루테늄(RuO 2 ), 산화 이리듐(IrO 2 )을 이용하여 형성한다. The lower electrode 609 is formed using platinum (Pt), ruthenium (Ru), iridium (Ir) or ruthenium (RuO 2), iridium oxide (IrO 2). 상기 하부 전극(609) 상에 유전율이 큰 탄탈륨산화막(Ta 2 O 5 ) 또는 PZT((Pb,Zr)TiO 3 ), BST((Ba,Sr)TiO 3 ), STO(SrTiO 3 ) 등과 같은 강유전체를 사용하여 유전막(611)을 형성한다. Ferroelectric, such as the lower electrode a large dielectric constant in the 609 tantalum oxide (Ta 2 O 5) or PZT ((Pb, Zr) TiO 3), BST ((Ba, Sr) TiO 3), STO (SrTiO 3) by using form a dielectric layer (611). 계속하여, 상기 유전막(611) 상부에 상부전극(613)을 형성한다. Subsequently, to form the upper electrode 613 above the dielectric layer 611. 상기 상부 전극(613)은 상기 하부 전극(609)과 동일한 물질로 형성할 수도 있다. The upper electrode 613 may be formed of the same material as the lower electrode 609.

상술한 바와 같이 본 발명의 원자층 증착법을 이용하여 형성되는 금속층 또는 다중 금속층은 내열성 및 내산화성이 높으며, 각각의 원자층을 증착하여 형성하므로 매우 콤팩트한 영역에서도 스텝커버리지가 우수하고, 각각의 원자층을 순서대로 흡착하여 형성하므로 CVD법에 비하여 조성비의 조절이 용이하며 조성의 재현성이 뛰어난 특성을 가진다. Metal layer or a multi-formed using an atomic layer deposition process the metal layer of the present invention as described above, heat resistance and has high oxidation resistance, and formed by depositing each of the atomic layer so that a step coverage excellent in a very compact area, each atom It formed by an absorption layer in order it is easy to control the composition ratio compared with the CVD method, and has an excellent reproducibility of the composition characteristics.

또한, 본 발명의 원자층 증착법을 이용하여 형성되는 금속층 또는 다중 금속층은 소스가스의 주입회수를 적절히 결정하는 것만에 의하여 조성비를 원하는 상태로 적절히 조정할 수 있게 된다. In addition, a metal layer or multiple metal layers formed using atomic layer deposition method of the present invention, it is possible to suitably adjust the composition ratio by simply determining the appropriate number of times of injecting a source gas as desired. 이에 따라, 금속층 또는 다중 금속층의 저항 및 전기 전도도를 매우 용이하게 조절할 수 있다. Accordingly, the metal layer or the resistance and electrical conductivity of the multi-metal layer can be very easily adjusted.

또한, 본 발명의 원자층 증착법을 이용하여 형성되는 금속층 또는 다중 금속층을 반도체 소자의 장벽 금속층, 하부 전극 또는 상부 전극에 채용할 수 있다. In addition, there may be employed a metal layer or multiple metal layers formed using atomic layer deposition method of the present invention on the barrier metal layer, the lower electrode or the upper electrode of the semiconductor element. 특히, 본 발명의 금속층 또는 다중 금속층을 장벽 금속층으로 채용할 경우 상술한 효과 외에 폴리실리콘 플러그의 산화를 방지할 수 있고, 하부 전극으로 채용할 경우는 하부 전극과 기판이 접하는 면에 별도의 장벽 금속층을 형성할 필요가 없어 제조공정이 단순해진다. In particular, when employing a metal layer or multiple metal layers of the present invention as a barrier metal layer can prevent the oxidation of the polysilicon plug in addition to the above effect, when employed as a lower electrode is a separate barrier to face the lower electrode and the substrate in contact with the metal layer it is not necessary to form the manufacturing process is simplified. 그리고, 본 발명의 금속층 또는 다중 금속층을 장벽 금속층으로 채용할 경우 상부전극의 조성을 용이하게 조절할 수 있고 이에 따라 전기전도도 및 저항을 용이하게 조절할 수 있다. Then, when to employ a metal layer or multiple metal layers of the present invention as a barrier metal layer can be easily adjusted the composition of the upper electrode Accordingly, it is possible to easily adjust the electrical conductivity and resistance.

Claims (36)

  1. 반도체 기판 상에 Ti, Ta, W, Zr, Hf, Mo 또는 Nb로 이루어진 반응성 금속(A), 질소(N), 및 상기 반응성 금속과 질소의 결정화를 방지하기 위해 Al, Si, 또는 B로 이루어진 비정질결합용 원소(B)의 각 소스가스들을 펄스 형태로 주입하여 상기 반도체 기판 상에 상기 소스가스들을 화학흡착시킴으로써 원자층 증착법으로 복수의 원자층들이 적층된 ABN 구조의 금속층 형성방법에 있어서, Reactive made on a semiconductor substrate with a Ti, Ta, W, Zr, Hf, Mo or Nb metal (A), consisting of Al, Si, or B in order to prevent nitrogen (N), and the crystallization of the reactive metal and nitrogen by chemical adsorption of the source gas on the semiconductor substrate by injecting each source gas into a pulse form of the amorphous binding element (B) for forming a metal layer according to the method of ABN structure it is stacked a plurality of atomic layer by atomic layer deposition,
    상기 각 소스가스들을 서로 교번되도록 순서를 정하여 주입함으로써 각 원자층이 서로 교대로 배열되도록 하고, 상기 각 소스가스의 주입회수를 조절하여 상기 금속층의 조성비를 결정함을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. The by respective appointed inject order to alternate with each other the source gas, and so as to be arranged to each other, each atomic layer alternately, with the atomic layer deposition method which is characterized by determining the composition ratio of the metal layer by adjusting the injection number of times for each of the source gas The method of forming metal layers.
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  3. 제1항에 있어서, 상기 비정질결합용 원소의 소스 가스의 주입회수를 조절함으로써 상기 금속층의 전기전도도 및 저항을 결정함을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. Method according, to form the metal layer by atomic layer deposition method which is characterized by determining the electrical conductivity and resistivity of the metal layer by adjusting a number of injection of the source gas of the amorphous binding element for in claim 1.
  4. 제1항에 있어서, 상기 금속층이 TiAlN층인 경우, 상기 TiAlN층에서의 Ti에 대한 Al의 함량은 10∼35 %로 함을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. The method of claim 1, wherein, when the metal layer TiAlN, how the content of the Al metal layer is formed using an atomic layer deposition method, characterized in that a 10-35% for the Ti in the TiAlN layer.
  5. 제1항에 있어서, 상기 반응성 금속(A)이 Ti인 경우, Ti의 소스가스는 TiCl 4 , TDMAT(Tetrakis DeMethyl Amino Titanium) 및 TDEAT(Tetrakis DeEthyl Amino Titanium)으로 이루어진 일군에서 선택된 어느 하나를 사용함을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. The method of claim 1, wherein when the reactive metal (A) is a Ti, a source gas of Ti is that it uses at least one selected from the group consisting of TiCl 4, TDMAT (Tetrakis DeMethyl Amino Titanium) and TDEAT (Tetrakis DeEthyl Amino Titanium) the method of forming the metal layer by atomic layer deposition method according to claim.
  6. 제1항에 있어서, 상기 비정질 결합용 원소(B)가 Al일 경우, 상기 알루미늄(Al)의 소스가스는 TMA(TriMethyl Aluminum), TEA(TriEthyl Aluminum), TIBA(Tri-I-Buthyl Aluminum) 및 AlClx으로 이루어진 일군에서 선택된 어느 하나를 사용함을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. The method of claim 1, wherein when the amorphous coupling element (B) for the Al, the source gas is TMA (TriMethyl Aluminum), (TriEthyl Aluminum) TEA, TIBA (Tri-I-Buthyl Aluminum) of the aluminum (Al) and the method of forming a metal layer using atomic layer deposition, characterized by using any one selected from the group consisting of AlClx.
  7. 제1항에 있어서, 상기 질소(N)의 소스가스로는 N 2 또는 NH 3 를 사용함을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. The method of claim 1, wherein the source gas of the nitrogen (N) is a method of forming a metal layer using atomic layer deposition, characterized by using an N 2 or NH 3.
  8. 제1항에 있어서, 상기 소스가스를 퍼지하기 위한 퍼지가스는 상기 금속층 형성시 처음부터 끝까지 연속적으로 주입됨을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. The method of claim 1, wherein the purge gas for purging the gas source is a method of forming a metal layer using atomic layer deposition, characterized in that the injected continuously from beginning to end when forming the metal layer.
  9. 제1항에 있어서, 상기 소스가스를 퍼지하기 위한 퍼지가스는 상기 금속층 형성시 각 소스가스가 주입되지 않는 시간에 주입되도록 펄스형으로 주입됨을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. The method of claim 1, wherein the purge gas for purging the gas source is a method of forming a metal layer using atomic layer deposition, characterized in that the pulse-like injection so that the injection time is not that each source gas when forming the metal layer injection.
  10. 반도체기판 상에 콘택홀을 구비한 절연막; An insulating film having a contact hole on a semiconductor substrate; 상기 콘택홀의 저면 상에 형성된 도전성 물질막; A conductive material layer formed on the bottom surface of the contact hole; 및 상기 콘택홀 내부의 도전성 물질막 상부에 형성된 하부전극, 상기 하부전극 상에 형성된 고유전막 및 상기 고유전막 상부에 형성된 상부전극을 포함하는 커패시터를 구비한 반도체 소자에 있어서, And according to a semiconductor device comprising a capacitor including a unique conductor film and an upper electrode formed on an upper part of the specific conductive film formed on the contact hole, inside the lower electrode conductive material film formed on the upper portion of the lower electrode,
    상기 콘택홀 내부의 도전성 물질막과 상기 하부전극 사이에, Ti, Ta, W, Zr, Hf, Mo 또는 Nb로 이루어진 반응성 금속(A), 질소(N), 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위해 Al, Si, 또는 B로 이루어진 비정질 결합용 원소(B)가 원자층 증착법에 의하여 서로 교대로 적층된 상태로 배열된 원자층들로 구성된 ABN 구조의 장벽금속층을 구비하며, 상기 장벽금속층의 각 원자층의 조성비는 각 원자층의 적층회수에 의하여 결정됨을 특징으로 하는 반도체 소자. Between the electrically conductive material layer within the contact holes and the lower electrode, the reactive metals consisting of Ti, Ta, W, Zr, Hf, Mo or Nb (A), nitrogen (N), and the crystallization of the reactive metal and a nitrogen the amorphous bonding element (B) for consisting of Al, Si, or B to prevent and provided with a barrier metal layer of ABN structure consisting of the atomic layers arranged in a stacked state to each other alternately by atomic layer deposition, the barrier metal layer the composition ratio of the atomic layers of a semiconductor device which is characterized by a determined number of laminated layers of each atom.
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  12. 제10항에 있어서, 상기 비정질결합용 원소(B)에 의한 원자층의 적층회수의 비율에 따라 상기 장벽금속층의 전기전도도 및 저항을 결정함을 특징으로 하는 반도체 소자. The method of claim 10, wherein the semiconductor device is characterized in that the amorphous coupling element (B) determining the electrical conductivity and resistivity of the barrier metal layer in accordance with the ratio of the number of times of stacking atomic layers by for.
  13. 제10항에 있어서, 상기 장벽금속층이 TiAlN인 경우 알루미늄(Al)의 조성비가 커질수록 장벽금속층의 비저항이 커짐을 특징으로 하는 반도체 소자. The method of claim 10, wherein the semiconductor device characterized in that the specific resistance of the barrier metal layer when the TiAlN The larger the composition ratio of aluminum (Al), a barrier metal layer increases.
  14. 제10항에 있어서, 상기 장벽금속층이 TiAlN인 경우 반응성금속에 대한 Al의 함량은 10∼35 % 임을 특징으로 하는 반도체 소자. 11. The method of claim 10, when the barrier metal layer of TiAlN semiconductor device characterized in that the content of Al is 10-35% of the reactive metal.
  15. 반도체기판 상의 물질층 상에 형성된 하부전극, 상기 하부전극 상에 형성된 고유전막 및 상기 고유전막 상부에 형성된 상부전극을 구비한 커패시터를 포함하는 반도체 소자에 있어서, A semiconductor device comprising a capacitor having a lower electrode, an upper electrode formed on the conductive film, and an upper part of the own unique conductive film formed on the lower electrode formed on the material layer on the semiconductor substrate,
    상기 하부 전극은 Ti, Ta, W, Zr, Hf, Mo 또는 Nb로 이루어진 반응성 금속(A), 질소(N), 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위해 Al, Si, 또는 B로 이루어진 비정질 결합용 원소(B)가 원자층 증착법에 의하여 서로 교대로 적층된 상태로 배열된 원자층들로 구성된 ABN 구조이며, 상기 하부전극의 각 원자층의 조성비는 각 원자층의 적층회수에 의하여 결정됨을 특징으로 하는 반도체 소자. Wherein the lower electrode is made of Al, Si, or B in order to prevent reactive metal (A), nitrogen (N), and the crystallization of the reactive metal and nitrogen consisting of Ti, Ta, W, Zr, Hf, Mo or Nb the amorphous bonding element (B) for an ABN structure consisting of the atomic layers arranged in a stacked state to each other alternately by atomic layer deposition method, the composition ratio of the atomic layer of the lower electrode is determined by the stacking number of each atomic layer a semiconductor element, characterized by.
  16. 삭제 delete
  17. 삭제 delete
  18. 삭제 delete
  19. 제15항에 있어서, 상기 상부 전극은 Ti, Ta, W, Zr, Hf, Mo 또는 Nb로 이루어진 반응성 금속(A), 질소(N), 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위해 Al, Si, 또는 B로 이루어진 비정질 결합용 원소(B)가 원자층 증착법에 의하여 서로 교대로 적층된 상태로 배열된 원자층들로 구성된 ABN구조이며, 상기 상부전극의 각 원자층의 조성비는 각 원자층의 적층회수에 의하여 결정됨을 특징으로 하는 반도체 소자. The method of claim 15, wherein the upper electrode is Ti, Ta, W, Zr, Hf, reactive metal (A) consisting of Mo or Nb, Al to prevent nitrogen (N), and the crystallization of the reactive metal and nitrogen, Si, or an ABN structure consisting of an atomic layer arranged in the amorphous bonding element (B) for lamination with each other alternately by atomic layer deposition conditions consisting of B, the composition ratio of the atomic layer of the upper electrode are each atomic layer a semiconductor device which is characterized by a determined number of times of stacking.
  20. 제15항에 있어서, 상기 비정질 결합용 원소에 의한 원자층의 적층회수의 비율에 따라 상기 하부 전극의 전기전도도 및 저항을 결정함을 특징으로 하는 반도체 소자. The method of claim 15, wherein the semiconductor device is characterized according to the ratio of the number of lamination of atoms on the amorphous layer by binding elements for which determines the electric conductivity and the resistance of the lower electrode.
  21. 반도체 기판 상에 Ti, Ta, W, Zr, Hf, Mo 또는 Nb로 이루어진 반응성 금속(A), 질소(N) 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위해 Al, Si 또는 B로 이루어진 비정질결합용 원소(B)의 각 소스가스를 펄스형태로 서로 교번되도록 순서를 정하여 공급하고, 조성비를 조절하게끔 상기 각 소스가스의 주입회수를 조절하면서 공급하여 상기 반도체 기판 상에 화학흡착시킴으로써 원자층 증착법으로 ABN 구조의 금속층을 형성하는 단계; Reactive metal (A), the amorphous bonding consisting of Al, Si or B in order to prevent nitrogen (N) and crystallization of the reactive metal and nitrogen consisting of Ti, Ta, W, Zr, Hf, Mo or Nb on a semiconductor substrate hagekkeum the respective source gases of elements (B) for the appointed order to alternate with each other in pulse form supply, and adjusting the composition ratio with each of the source gas is injected by controlling the number of times while feeding by chemical adsorption onto the semiconductor substrate, atomic layer deposition of forming a metal layer of ABN structure; And
    상기 금속층 상에 산소 확산 방지층을 형성하여 상기 금속층과 산소 확산 방지층이 각각 복수회 증착된 다중 금속층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. The method of forming the metal layer by atomic layer deposition method which comprises using oxygen to form a diffusion barrier layer on the metal layer comprising the metal layer and the oxygen diffusion barrier layer to form a multi-metal layer deposited a plurality of times, respectively.
  22. 제21항에 있어서, 상기 산소 확산 방지층은 상기 금속층이 형성된 반도체 기판 상에 금속 원소 및 산소의 소스 가스를 펄스 형태로 서로 교번되도록 공급하여 형성하는 것을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. The method of claim 21, wherein the oxygen diffusion barrier layer is a method of forming a metal layer using an atomic layer deposition method as to form the supply to alternating with each other in the source gas pulses in the form of metal element and oxygen on the semiconductor substrate where the metal layer is formed.
  23. 제21항에 있어서, 상기 산소 확산 방지층은 상기 금속층 상에 원자층 증착법으로 산소가 포함된 물질층을 형성하는 단계와, 상기 금속층 및 물질층이 형성된 반도체 기판을 열처리하는 단계를 포함하여 얻어지는 것을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. The method of claim 21, wherein the oxygen diffusion barrier layer is characterized in that which is obtained by comprising the step of heat-treating step and the metal layer and the semiconductor substrate material layer is formed to form a layer of material that contains oxygen in an atomic layer deposition on the metal layer the method of forming the metal layer by atomic layer deposition according to.
  24. 삭제 delete
  25. 삭제 delete
  26. 제21항에 있어서, 상기 비정질 결합용 원소의 소스 가스의 주입회수를 조절함으로써 상기 금속층의 전기전도도 및 저항을 결정함을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. Method according, to form the metal layer by atomic layer deposition method which is characterized by determining the electrical conductivity and resistivity of the metal layer by adjusting a number of injection of the source gas of the amorphous binding element for in claim 21.
  27. 제21항에 있어서, 상기 반응성 금속(A)이 Ti인 경우, Ti의 소스가스는 TiCl 4 , TDMAT(Tetrakis DeMethyl Amino Titanium) 및 TDEAT(Tetrakis DeEthyl Amino Titanium)으로 이루어진 일군에서 선택된 어느 하나를 사용함을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. 22. The method of claim 21, wherein, when the reactive metal (A) is a Ti, a source gas of Ti is that it uses at least one selected from the group consisting of TiCl 4, TDMAT (Tetrakis DeMethyl Amino Titanium) and TDEAT (Tetrakis DeEthyl Amino Titanium) the method of forming the metal layer by atomic layer deposition method according to claim.
  28. 제21항에 있어서, 상기 반응성 금속과 질소의 결정화를 방지하기 위한 비정질 결합용 원소(B)가 Al인 경우, 상기 Al의 소스가스는 TMA(TriMethyl Aluminum), TEA(TriEthyl Aluminum), TIBA(Tri-I-Buthyl Aluminum) 및 AlClx으로 이루어진 일군에서 선택된 어느 하나를 사용함을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. 22. The method of claim 21, wherein, when the reactive metal and the amorphous coupling element (B) for to prevent crystallization of the nitrogen is in Al, the source gas of the Al is TMA (TriMethyl Aluminum), TEA (TriEthyl Aluminum), TIBA (Tri -I-Buthyl Aluminum) and a method of forming a metal layer from the group consisting of AlClx using atomic layer deposition, characterized by using any one selected.
  29. 제21항에 있어서, 상기 질소(N)의 소스가스로는 N 2 또는 NH 3 을 사용함을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. 22. The method of claim 21, wherein the source gas of nitrogen (N) is a method of forming a metal layer using atomic layer deposition, characterized by using an N 2 or NH 3.
  30. 제21항에 있어서, 상기 산소 확산 방지층은 알루미늄 산화막으로 형성하는 것을 특징으로 하는 원자층 증착법을 이용한 금속층 형성방법. 22. The method of claim 21, wherein the oxygen diffusion barrier layer is a metal layer formed by an atomic layer deposition method as to form an aluminum oxide film.
  31. 반도체기판 상에 콘택홀을 구비한 절연막; An insulating film having a contact hole on a semiconductor substrate; 상기 콘택홀의 저면 상에 형성된 도전성 물질막; A conductive material layer formed on the bottom surface of the contact hole; 및 상기 콘택홀 내부의 도전성 물질막 상부에 형성된 하부전극, 상기 하부전극 상에 형성된 고유전막 및 상기 고유전막 상부에 형성된 상부전극을 포함하는 커패시터를 구비한 반도체 소자에 있어서, And according to a semiconductor device comprising a capacitor including a unique conductor film and an upper electrode formed on an upper part of the specific conductive film formed on the contact hole, inside the lower electrode conductive material film formed on the upper portion of the lower electrode,
    상기 콘택홀 내부의 도전성 물질막과 상기 하부전극 사이에, Ti, Ta, W, Zr, Hf, Mo 또는 Nb로 이루어진 반응성 금속(A), 질소(N) 및 상기 반응성 금속 및 질소의 결정화를 방지하기 위해 Al, Si 또는 B로 이루어진 비정질결합용 원소(B)가 원자층 증착법에 의하여 서로 교대로 적층되고 적층 회수에 의하여 조성비가 결정되는 ABN 구조의 금속층과, 상기 금속층 상에 산소 확산 방지층이 형성되어 상기 금속층과 산소 확산 방지층이 각각 복수회 적층된 장벽 금속층이 형성되어 있는 것을 특징으로 하는 반도체 소자. Between the electrically conductive material layer within the contact holes and the lower electrode, the reactive metals consisting of Ti, Ta, W, Zr, Hf, Mo or Nb (A), nitrogen (N) and prevent crystallization of the reactive metal and a nitrogen Al, the oxygen diffusion barrier layer on the metal layer and the metal layer of ABN structures are stacked with each other alternately by atomic layer deposition the composition ratio is determined by the stacking number of the amorphous binding element (B) for consisting of Si or B is formed to It is a semiconductor device characterized in that the barrier metal layer is the metal layer and the oxygen diffusion barrier layer are laminated a plurality of times, respectively are formed.
  32. 제31항에 있어서, 상기 산소 확산 방지층 상에 산소가 포함된 물질층이 더 형성되어 있는 것을 특징으로 하는 특징으로 하는 반도체 소자. 32. The method of claim 31, semiconductor elements, characterized in that on the oxygen diffusion barrier layer characterized in that the further layer-forming material containing oxygen.
  33. 삭제 delete
  34. 삭제 delete
  35. 제31항에 있어서, 상기 비정질 결합용 원소에 의한 원자층의 적층회수의 비율에 따라 상기 장벽 금속층의 전기전도도 및 저항을 결정함을 특징으로 하는 반도체 소자. The method of claim 31, wherein the semiconductor device is characterized in that the amorphous bonding element determining the conductivity and resistance of the barrier metal layer in accordance with the ratio of the number of times of stacking atomic layers by for.
  36. 제31항에 있어서, 상기 산소 확산 방지층은 알루미늄 산화막인 것을 특징으로 하는 반도체 소자. The method of claim 31, wherein the semiconductor device is characterized in that the oxygen diffusion barrier layer is an aluminum oxide film.
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