KR100357529B1 - Test Apparatus by Batch Type Contact of multiple semiconductor device - Google Patents

Abstract

The plurality of semiconductor device collective contact test benches include: a lower test bench having a U-groove for receiving a plurality of semiconductor devices, respectively; An upper test bench having a substrate having a through hole formed at a center thereof, and a plurality of probes connected to the substrate to collectively contact the semiconductor element; A plurality of semiconductor devices may be tested by collective contact, including coupling means for detachably coupling the upper test bench to the lower test bench.

Description

Test Apparatus by Batch Type Contact of multiple semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of semiconductor device collective contact test benches, and more particularly, to a test bench for collectively contacting and testing electrodes of respective devices when testing a plurality of semiconductor devices collectively.

In general, semiconductor devices produced through manufacturing and assembly processes must ensure proper quality and reliability. Therefore, by testing whether a semiconductor device that has undergone each process has characteristics that meet specific criteria, it is possible to minimize the occurrence of defects in each process and maximize the reliability of the finished product. Such tests include, for example, burn-in tests, which test semiconductor property changes for a period of time (eg, 96 hours or more) at various temperature ranges from -40 ° C to 85 ° C.

In order to perform such a test, a test bench for mounting a semiconductor device is required. In the conventional semiconductor device test bench, one semiconductor device is mounted using an adhesive or the like and the mounted semiconductor devices are individually tested. In this case, it is very important to mount the semiconductor device in the correct position on the test table because the semiconductor device should be mounted at the correct position to obtain the correct test result. For example, in the case of an optical communication element, an incorrect test result is calculated if the direction and position of light emission and light reception are not correct.

However, since it is not easy to mount the semiconductor device in the correct direction at the exact position of the conventional semiconductor device test bench, there is a problem that requires a skilled technique for this.

In addition, if it is incorrectly mounted in the mounting process, it must be corrected through trial and error, and at this time, since the semiconductor device that is already bonded and fixed must be detached and bonded again, an undesired impact is applied to the semiconductor device under test. There was a problem of this defect.

In addition, there is a problem in that the use efficiency of the test bench is low because one semiconductor device is mounted and tested on each test bench.

An object of the present invention is to solve such a conventional problem, by providing a test bench that can be tested by contacting a large number of semiconductor devices in a batch, not only to increase the test efficiency, but also to easily test the non-skilled person. To help.

Another object of the present invention is to provide a reliable test bench in which the probe for testing is in intimate contact with the semiconductor device under test.

1 is an exploded perspective view of a plurality of semiconductor device package contact test bench according to an embodiment of the present invention.

Figure 2 is a cross-sectional view showing another embodiment of the coupling means used in the multiple semiconductor device package contact test bench according to an embodiment of the present invention.

3 is a cross-sectional view taken along the line III-III of FIG.

4 is an enlarged perspective view of a jig portion used in a plurality of semiconductor element package contact test bench according to an embodiment of the present invention.

5 is a cross-sectional view taken along the line V-V of FIG.

6 is a perspective view of a submount tested in multiple semiconductor device batch contact test benches in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: lower test bench 18: fixed part

20: jig portion 22: U groove

40: upper test bench 41: through hole

42: probe 44: support

48: Board 52, 54: Connector

60: submount

In order to achieve the above object, a plurality of semiconductor device batch contact test bench according to an embodiment of the present invention includes a lower test bench formed with a U groove each receiving a plurality of semiconductor devices to be tested; An upper test bench having a substrate having a through hole formed at a center thereof, and a plurality of probes connected to the substrate to collectively contact the semiconductor element; And a coupling means for detachably coupling the upper test bench to the lower test bench.

The upper test bench is characterized in that it further comprises a fixing portion formed to put the lower test bench on.

The probe may be inclinedly supported by a support part provided around the center through hole in the lower portion of the substrate.

The probe is characterized in that it is fixed to the support by an adhesive.

The U-groove is characterized in that the inclined side is formed along the four edges, and the U-groove and its adjacent portion is characterized in that the Teflon coating.

The semiconductor device may be a submount in which a semiconductor chip and an electrode are formed.

The upper test bench may further include a test pin connected to the probe and a connector electrically connected to the test pin.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Referring to FIG. 1, the upper test bench 40 is detachably coupled onto the lower test bench 10 by, for example, a coupling means 49 such as a fixing nut. The fixed part 18 installed in the lower test bench 10 fixes the position of the upper test bench 40 so that a predetermined interval is formed between the lower test bench 10 and the upper test bench 40. On the other hand, when the fixing unit 18 is installed on the lower test bench 10, the coupling with the lower test bench 10, which is the lower part of the fixing unit 18, for example, to adjust the height of the fixing unit 18 from the upper surface of the lower test bench 10. Screw portions (not shown) may be provided at the site.

Various methods may be used in the method of detachably coupling a predetermined interval between the lower test bench 10 and the upper test bench 40, for example, the fixing pin 420 of the upper test bench 40 as shown in FIG. ) Is inserted into the through hole 410 is inserted into the lower test bench 10 by inserting the fixing pin 420 into the through hole 410 and the upper test bench 40 to the fixed part 480, the lower There is also a method of fixing the upper test bench 40 so as not to move by a removable fastening clip (not shown) installed on both sides of the test bench 10.

The fixed portion 18,480 of the lower test bench 10 and the contact portion of the upper test bench 40 which touches the fixed portion 18,480 are machined with a certain precision, so that there is a constant gap between the lower test bench 10 and the upper test bench 40. It is important to keep it.

The lower test bench 10 is formed with a plurality of U grooves 22 to accommodate the semiconductor device to be tested. The U groove 22 may be formed directly on the lower test bench 10, or as shown, after forming a plurality of U grooves 22 in a separate jig part 20, the fastening part of the jig part 20 is formed. It may be fastened to the lower test bench 10 by (24).

In order to measure the temperature, a thermocouple may be attached to the lower test bench 10 and the terminal 16 for temperature measurement may be connected to the connector 54 of the upper test bench 40. As shown in the drawing, the lower test bench 10 may be installed between the upper and lower parts by separating the upper and lower parts.

Mounting protrusions 19 protruding from both sides of the lower test bench 10 allows the test bench to be easily mounted to a rack-shaped module.

The upper test bench 40 is formed with a probe 42 installed below the substrate 48 and supported by the support 44. An operator views the probe 42 and the semiconductor device 60 in contact therewith. Through-holes 41 are formed at approximately the center of the substrate 48 so as to be possible. One end of the probe 42 is a free end and is in contact with the semiconductor device under test, and the other end is fixed to the substrate 48 and connected to the test pin 47.

Since the connector 52 is electrically connected to the test pin 47, the connector 52 is electrically connected to the semiconductor element 60 which is contacted and connected by the probe 42. Therefore, the connector 52 facilitates supplying an electrical signal to the semiconductor device 60 under test and connecting the current flowing thereto with an external circuit.

Referring to Figure 3, the probe 42 is supported by the support 44, which is preferably fixed to the support 44 with an adhesive 46 such as epoxy. The probe 42 is preferably inclined so as to increase the contact area in contact with the semiconductor device 60 as a test object. The contact with 60 can be made more secure.

The probe 42 is preferably made of a high elastic material having high electrical conductivity. Then, the position of the probe 42 is precisely maintained even after repeated use, and the electrode surface of the semiconductor element 60 is scratched by the elastic force of the probe 42 when the probe 42 comes into contact with the element 60. Because of the contact, there is an effect of removing the oxide film formed on the electrode, thereby improving the contactability and reducing the contact electrical resistance. As the material of the probe 42, for example, tungsten or beryl copper (BeCu) may be used.

As for the support part 44 which fixes the probe 42, it is preferable to use the material with small deformation | transformation, such as ceramic, even at high temperature. The support 44 may be continuously disposed below the substrate 48, which is an edge of the through hole 41, to minimize deformation of the substrate 48.

4 shows the U-groove 22 of the jig portion 20 in which the semiconductor element 60 is placed. The U-groove 22 has a bottom surface 22c and an inclined side surface 22a formed obliquely along the four-sided edges of the U-groove 22, as shown in FIG. Here, the size of the bottom surface 22c is such that the size of the semiconductor element 60 accommodated can be properly seated. The semiconductor element slides along the inclined side surface 22a and is accommodated in the bottom surface 22c. In order to better secure the semiconductor device, a vertical surface 22b that is approximately perpendicular to the bottom surface 22c may be formed.

Meanwhile, the U groove 22 and its adjacent portion are coated with a material having a small coefficient of friction, for example, Teflon (trade name of DuPont, USA) so that the semiconductor device 60 accommodated therein is easily seated in the U groove 22. It is desirable to. The coating prevents scratches from occurring when the semiconductor element 60 to be accommodated is seated in the U groove 22, and further improves the insulating properties between the semiconductor element 60 and the U groove 22.

For convenience of description, the semiconductor device 60, which is a test object of the present invention, has been described as one chip. However, as shown in FIG. 6, a plurality of chips such as an optical communication laser diode 62 and a photodiode 64 are attached. It may also be a submount connected by an electrode 66. The submount can be a variety of materials such as silicon, copper, ceramics, etc. as needed for heat dissipation, reliability and stability of the chip.

Referring to the operation of a plurality of semiconductor device package contact test bench according to the present invention. In other words,

After mounting the semiconductor device 60 to each of the plurality of U grooves 22 while the lower test bench 10 and the upper test bench 40 are separated, the upper test bench 40 is placed on the lower test bench 10 and coupled. Combine both test benches by means. Then, the semiconductor element 60 connected to the external circuit by the connector 52 and the probe 42 installed on the upper test bench 40 in contact with the electrodes of the respective semiconductor elements 60 can be tested. At this time, the through hole 41 is formed in the substrate 48, so that the probe 42 can be easily visually checked whether the semiconductor element 60 is in contact with the semiconductor element 60, and the test pin 47 formed on the substrate 48. It is also possible to simply check whether the contact between the probe 42 and the semiconductor element 60 is properly made using.

The multiple semiconductor device batch contact test bench according to the present invention can be used for various types of semiconductor devices or submounts to which semiconductor devices are attached, as well as non-burn-in tests.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made within the spirit and scope of the present invention. Various modifications can be used in the field of device testing.

According to the present invention, since the U-groove is used to mount the semiconductor device to be tested on the test bench, there is an effect that the semiconductor device can be mounted on the test bench at an accurate position without skilled skills.

In addition, the contact between the probe and the semiconductor device, which is a test terminal, can be visually confirmed, so the contact state can be easily checked.

In addition, the test can be performed effectively because a plurality of semiconductor devices which are the test targets are contacted and tested at the same time.

Therefore, it is possible to effectively test the semiconductor device, thereby increasing the efficiency of manpower and equipment input and significantly reducing the production cost of the semiconductor device.

Claims (8)

A lower test bench having a U groove for receiving a plurality of semiconductor elements to be tested; An upper test bench having a substrate having a through hole formed at a center thereof, and a plurality of probes connected to the substrate to collectively contact the semiconductor element; And A coupling means installed on the lower test bench and detachably coupling the upper test bench, U-groove of the lower test bench is a plurality of semiconductor device batch contact test bench, characterized in that the inclined side is formed along the four edges. The method of claim 1, The upper test bench is a plurality of semiconductor device batch contact test bench, characterized in that further provided with a fixed portion formed to put the lower test bench on. The method according to claim 1 or 2, And the probe is inclinedly supported by a support provided around the center through hole in the lower portion of the substrate. The method of claim 3, wherein And the probe is fixed to the support by an adhesive. delete The method according to claim 1 or 2, The U-groove and its adjacent portion are Teflon coated, a plurality of semiconductor device batch contact test bench. The method according to claim 1 or 2, And said semiconductor device is a submount in which a semiconductor chip and an electrode are formed. The method according to claim 1 or 2, The upper test bench is a plurality of semiconductor device batch contact test bench, characterized in that further comprising a test pin connected to the probe and a connector electrically connected to the test pin.