KR100320210B1 - Bus structure for digital television system - Google Patents

Abstract

The present invention relates to a bus structure of a digital TV system, which requires processing of a larger amount of data than that of a conventional digital TV. Therefore, a low-cost, low-performance CPU has been adopted as a high-performance and high-performance CPU. Because all components are handled by one system bus in configuration, the overall system speed is limited to the components with the lowest processing speed, causing bottlenecks in high-performance CPUs, and adding new function modules to expand the functions of the system. There was a problem that the structure is not easy to add. Accordingly, the present invention provides a CPU bus for connecting and operating a CPU for controlling the entire system and a memory having a high data processing speed; A system bus for connecting and operating devices that perform independent processing operations, such as an audio decoder, a VSB receiver, and an A / V processor; An expansion bus to facilitate installation of various peripherals and expansion of new functions; It includes a bus interface unit for interfacing the signal transmission between the devices connected to each bus to perform smoothly by separating the bus according to the operating speed of the elements constituting the digital TV to increase the bandwidth of the bus to process data This has the effect of speeding up and facilitating the expansion of functionality for new services.

Description

BUS STRUCTURE FOR DIGITAL TELEVISION SYSTEM}

The present invention relates to a bus structure of a digital TV system, and more particularly, to a bus structure of a digital TV system that facilitates processing speed and function expansion of a digital TV system.

In general, MPEG (Motion Picture Expert Group) -2 in 1994 became the international standard for compression / reproduction of broadcast A / V signals, and in 1997 the Advanced Television System Committee (ATSC) of the United States adopted the standard for digital TV. As a result, each country and company has developed systems for transmitting and receiving digital video in various forms. Until now, digital video transmission and reception through direct satellite broadcasting has become widespread. After uploading, it became the digital age in broadcasting.

As described above, a digital TV for receiving a digital broadcast may be connected to an existing TV for PAL / NTSC using a cable, such as a set-top box for receiving a satellite broadcast, or may be built in the TV itself.

The general configuration of the digital TV system as described above is shown in FIG.

That is, the CPU 1 which controls the whole system and performs a calculation; A VSB receiver 6 which receives an RF signal through the antenna 9 and corrects synchronization, equalization, and error to output a TP (Transport Packet Stream); An A / V processing unit 7 for decompressing the compressed MPEG-2 data and converting the compressed MPEG-2 data into various display formats such as 1920x1080 interlace and outputting the same to the screen; A ROM 2 and a RAM 3 for storing programs and data necessary for controlling the system; An audio decoder 5 for decoding and outputting a voice signal; Each component is composed of a glue logic unit (4) to be connected smoothly.

Such a conventional system uses a 16-bit / 32-bit low-cost embedded processor as a CPU to perform basic functions such as interrupt and I / O control.

However, the current digital TV system has added a lot of channels to receive broadcasts due to the efficient use of bandwidth, provides high definition image quality and CD level sound quality, and adds many applications and peripherals to home shopping, electronic newspaper, Various additional services such as stock information can be provided.

Therefore, since a large amount of data has to be processed than conventional digital TVs, high-performance and high-performance CPUs have been adopted from low-cost, low-performance CPUs. (8) Because it is processed through one, the overall system speed is limited to the components with the lowest processing speed, causing bottlenecks in high-performance CPUs, and it is not easy to add new function modules to expand the functions of the system. There was a problem with the structure.

Accordingly, the present invention has been created to solve the above-mentioned conventional problems, by separating the bus according to the operating speed of the elements constituting the digital TV to increase the bandwidth of the bus to improve the data processing speed, new service The purpose is to provide a bus structure of a digital TV system that can be flexible when extending the function.

1 is an exemplary view showing the configuration of a general digital TV system.

Figure 2 is an exemplary view showing a bus configuration of a digital TV according to the present invention.

Figure 3 is an exemplary view showing a physical specification of a slot to enable each device to connect to the bus in accordance with the present invention.

*** Description of the symbols for the main parts of the drawings ***

10: CPU bus 20: System bus

30: expansion bus

The present invention for achieving the above object is a CPU bus for operating by connecting the CPU and the data processing speed of the memory for the control of the entire system; A system bus for connecting and operating devices that perform independent processing operations, such as an audio decoder, a VSB receiver, and an A / V processor; An expansion bus to facilitate installation of various peripherals and expansion of new functions; It characterized in that it comprises a bus interface for interfacing so that the signal transmission between the devices connected to each bus can be performed smoothly.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is an exemplary view showing a bus configuration of a digital TV according to the present invention. As shown in FIG. 2, a CPU 1 for controlling the entire system and a memory 2 and 3 having a high data processing speed are connected and operated. A CPU bus 10; A system bus 20 for connecting and operating devices performing independent processing operations, such as the audio decoder section 5, the VSB receiving section 6, and the A / V processing section 7; An expansion bus 30 for facilitating installation of various peripherals 4 and expansion of new functions; It includes a bus interface unit 40 for interfacing so that the signal transmission between the devices connected to each bus can be performed smoothly.

As a result, the CPU 1 connected to the same CPU bus 10 can process arithmetic and system control operations at high speed while referring to the memory 2 and 3 having a high processing speed.

In addition, the data calculated by the CPU 1 is quickly transmitted to the peripheral device 4 or the A / V processing unit 7 through the bus interface unit 40.

In this case, the peripheral device may be a satellite reception card for receiving a broadcast through a satellite or a network card for configuring a network such as a PC connected to a LAN.

That is, in the related art, when the data calculated by the CPU 1 is transferred to the peripheral device 4, since the speed of the peripheral device 4 is slow, the maximum bus speed is limited thereto, and thus other operations cannot be performed. Once the data is transmitted to the bus interface unit 40, the bus interface unit 40 acts as a buffer for transmitting data according to the speed of each peripheral device 4, so that the CPU 1 can be connected to another bus ( Regardless of the devices connected to the devices 20 and 30, other operations can be performed immediately, thereby improving the processing speed of the system.

In addition, since the bus is divided according to the operation speed and role in the system configuration, it is easy to expand and upgrade.

Figure 3 is an exemplary diagram showing the physical specifications of slots that allow each device to be connected to the bus according to the present invention, where SA [0:23] is an address line used by the CPU, memory and I / O devices during the bus cycle. It has an addressing area of 256M bytes and SA23 is the Most Significant Bit (MSB).

Next, SD [0:31] is a system data bus that outputs Input during read cycles and Output during write cycles, and supports both 8-bit / 16-bit / 32-bit.

Next, STRB # tells the data strobe that valid data has been loaded on the bus during the read cycle, indicates that valid data has been output on the data bus during the write cycle, R / W # indicates the data transfer direction on the bus, and CS [1: 7] represents Chip Select.

Next, MEMOE # (Memory Output Enable) and MEMWE # (Memory Write Enable) are used when CPU or external bus master accesses memory, RDY is used to insert wait between external I / O and host, and DMAR [0: 1] # (DMA Request) and DACK [0: 1] # (DMA Acknoledge) are signals related to DMA requests and responses.

EOT [0: 1] # / TC [0: 2] indicates that the external I / O has completed the DMA transfer, the CPU indicates the last DMA transfer, and the interrupt request signal (INT [0: 3). ]) And (CS_OUT #) to access external I / O using the memory map inside the host and (BUSERR #) to indicate that an invalid bus transfer has been made, (RESET to initialize the CPU and all I / O) #), Which represents the clock stage for inputting the system clock (SYSCLK), and the clock stage for inputting the clock for use in the MPEG system (MPEGCLK).

In addition to the above, there are 12C Bus Clock (SCL), 12C Bus Data (SDA), and GPIO [0: 4] (General Purpose I / O).

As described above, the bus structure of the digital TV system of the present invention divides the bus according to the operation speeds of the elements constituting the digital TV to increase the bandwidth of the bus, thereby improving data processing speed and expanding functions for new services. There is an effect that can facilitate.

Claims (2)

A CPU bus for connecting and operating a CPU for controlling the entire system and a memory having a high data processing speed; A system bus for connecting and operating devices that perform independent processing operations, such as an audio decoder, a VSB receiver, and an A / V processor; An expansion bus to facilitate installation of various peripherals and expansion of new functions; Bus structure of the digital TV system comprising a bus interface for interfacing so that the signal transmission between the devices connected to each bus can be performed smoothly. 2. The method of claim 1, wherein each bus connects devices having the same clock speed and bandwidth to the same bus by using the same bus, and ports of devices connected to each bus can be connected by slots or connectors of the same physical standard. Bus structure of a digital TV system.