KR100296117B1 - Method for forming cobalt disilicide contact hole by chemical vapor deposition process - Google Patents

Method for forming cobalt disilicide contact hole by chemical vapor deposition process Download PDF

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KR100296117B1
KR100296117B1 KR1019980019299A KR19980019299A KR100296117B1 KR 100296117 B1 KR100296117 B1 KR 100296117B1 KR 1019980019299 A KR1019980019299 A KR 1019980019299A KR 19980019299 A KR19980019299 A KR 19980019299A KR 100296117 B1 KR100296117 B1 KR 100296117B1
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cobalt
cosi
forming
source
vapor deposition
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KR19990086355A (en
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안병태
이화성
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윤덕용
한국과학기술원
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metallic silicode formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides

Abstract

PURPOSE: A method for forming a cobalt disilicide contact hole by chemical vapor deposition process is provided to simplify a contact formation process by forming CoSi2 epitaxial layer of a single crystal or nearing to a single crystal having (100) direction such as silicon while depositing cobalt metal on a silicon substrate of (100) direction at temperature of 600 °C using a low pressure CVD method. CONSTITUTION: By introducing a cobalt-organic metal source into a reactor, cobalt is deposited at temperature of 600°C or greater using a low pressure chemical vapor deposition method. An epitaxial layer CoSi2(7) is formed on a source and a drain, and a polycrystalline CoSi2(7) is formed on a gate. A cobalt metal over an oxide layer is etched, thereby forming a cobalt disilicide contact. In CoSi2(7) formation process, the cobalt-organic metal source is selected from (C5H5)2Co, Co(CO)3NO, C5H5Co(CO)2, Co2(CO)8 or Co4(CO)12.

Description

화학기상증착법에 의한 코발트다이실리사이드 콘택 형성방법 Method cobalt di silicide contact is formed by a chemical vapor deposition method

본 발명은 기가디램(Giga D RAM)급 이상의 ULSI(Ultra large scale integration)용 초미세 반도체소자의 콘택형성에 관한 것이다. The present invention relates to a group of contacts forming the ultrafine semiconductor devices for dynamic random access memory (RAM Giga D) class over ULSI (Ultra large scale integration). 보다 상세하게는 고융점 금속과 게이트전극인 폴리실리콘과의 반응에 의해 형성되는 폴리사이드(polycide)와 고융점 금속과 소스, 드레인에서의 실리콘과의 반응에 의해 형성되는 콘택실리사이드 형성방법인 샐리사이드(salicide) 공정에서 코발트 실리사이드를 이용하는 새로운 방법에 관한 것이다. More specifically, the high-melting point metal and the gate electrode is formed by the reaction of the polysilicon polycide (polycide) and a refractory metal and the source, the contact silicide formation method of salicide formed by the reaction between the silicon in the drain (salicide) relates to a new method of using a cobalt suicide in the process.

종래의 기가디램급 이상의 메모리 소자에서 콘택형성 방법은 기술적으로 어려운 점이 많다고 알려져 있으며 그 선행기술로써 한국특허출원 93-21059, 93-616, 93-28017 등의 내용은 미세구조의 고집적 반도체소자에서 소스, 드레인 및 게이트 전극의 저항을 감소시키기 위한 샐리사이드 공정이다. Forming a contact in the conventional group de-raemgeup or more memory devices method known Having technically difficult point, and as the content of the prior art such as Korea Patent Application No. 93-21059, 93-616, 93-28017 includes a source in a highly integrated semiconductor device of the microstructure a salicide process to reduce the resistance of the drain and gate electrodes. 이것의 공정방법은 도1에서 나타낸 것처럼 소스, 드레인과 게이트를 형성한 후 티타늄이나 코발트 금속과 보호층인 TiN을 스퍼터링(Sputtering) 방법에 의하여 200∼400℃에서 증착한 후 700℃ 이하에서 1차 열처리하여 금속과 실리콘의 1차 화합물인 C49 TiSi 2 나 CoSi를 형성시킨다. This process method in the first source, after the drain and after forming the gate by a titanium or cobalt metal and a protective layer of TiN sputtering (Sputtering) method deposited at 200~400 ℃ below 700 ℃ as shown in Figure 1 heat treatment to form a first compound of C49 TiSi or CoSi 2 of metal and silicon. 그런다음 반응하지 않고 남은 금속을 에칭하고 700-800℃ 이상의 고온에서 2차 열처리하여 최종적으로 C54 TiSi 2 나 CoSi 2 등의 접촉저항 및 비저항이 낮은 실리사이드를 형성시키는 방법이다. Without reaction and then etching the rest of metal and a method of forming a final C54 TiSi 2, and CoSi 2, such as contact resistance and a low specific resistance of the silicide by heat-treating at least the second high-temperature 700-800 ℃. 또한 변정수(Byun Jeong Soo, J. Electrochem. Soc., 1997, Vol. 144, 3175)등이 발표한 내용은 질소 분위기 하에서 기판온도를 500℃로 하여 스퍼터링에 의하여 코발트를 증착한 후 반응한 CoSi만을 남기고 미반응한 코발트는 에칭하여 제거하고 최종적으로 TiN의 보호층을 증착한 후 750℃ 이상의 고온에서 급속열처리에 의하여 CoSi 2 를 형성하는 방법이다. Also Byun Jung-soo (Byun Jeong Soo, J. Electrochem. Soc., 1997, Vol. 144, 3175), etc. This information is only released after the deposition of cobalt by sputtering the substrate temperature to 500 ℃ CoSi reacted in a nitrogen atmosphere a method of leaving the unreacted cobalt is removed by etching, and finally forming a CoSi 2 after depositing the protective layer of TiN rapidly at higher temperatures than 750 ℃ by heat treatment. 도만스(Dormans, J. Crystal Growth, 1991, Vol. 114, 364)등은 화학기상증착법에 의하여 300∼600℃에서 코발트 증착이 가능함을 보여주었으나 새로운 샐리사이드 공정을 제안하지는 않았다. Degrees switch (Dormans, J. Crystal Growth, 1991, Vol. 114, 364) and the like were not proposed a new salicide process eoteuna demonstrate a cobalt deposited while in the 300~600 ℃ by a chemical vapor deposition method. 종래의 샐리사이드 공정방법에 의하여 얻어진 실리사이드 박막의 면저항은 1-2Ω/□ 정도이다. The sheet resistance of the silicide thin film obtained by a conventional salicide process method is 1-2Ω / □ or so. 그러나 이들 종래의 방법은 200∼400℃에서 스퍼터링에 의해 증착된 금속을 700℃이하에서 1차 열처리하고 미반응 금속을 에칭한 후 다시 800℃ 이상에서 2차 열처리를 거쳐야 하며 이때 금속의 산화와 응집(agglomeration)를 방지하기 위해 금속보호층을 반드시 필요로 한다. However, these conventional methods is heat-treated first with a metal deposited by sputtering at 200~400 ℃ below 700 ℃ and go through a secondary heat treatment at above 800 ℃ and re-etch the non-reacted metal and wherein the oxidation and aggregation of the metal and a metal protective layer to be necessary in order to prevent (agglomeration). 또한 스퍼터링법에 의한 방법은 초미세구조의 소자에서 도포성이 떨어져 균일한 박막을 얻기 어렵고 특히 소스, 드레인 및 게이트의 콘택홀 깊이와 직경의 비가 매우 클 경우 콘택홀에서 균일한 도포성을 얻기가 매우 어려운 단점이 있다. In addition, the method of the sputtering method is to obtain a coating property is approximately one difficult to obtain a uniform thin film, especially the source, in contact holes for a drain, and a contact hole depth and diameter of the gate ratio is very large, uniform coating characteristics in a device of the ultrastructural there are very difficult.

본 발명의 목적은 종래에 수행되지 않았던 저압 화학기상증착방법을 이용하여 (100) 방위 실리콘 기판위에 600℃이상에서 코발트 금속을 증착함과 동시에 기판의 실리콘과의 반응으로 실리콘과 같은 (100) 방위를 갖는 단결정이나 단결정에 가까운 에피택시층(epitaxial layer)의 CoSi 2 를 형성시킴으로써, 750℃ 이상의 고온 열처리를 수행하지 않고 1회에 반응기 (reaction chamber) 내에서 공정을 수행하여 콘택형성 공정을 단순화시키고 저항을 낮추어 기가디램급 이상의 반도체소자 배선공정 기술개발 및 관련 소자개발을 하는데 있다. An object of the present invention using a low pressure chemical vapor deposition methods have not been performed in the conventional (100) 100, such as silicon into reaction with the substrate silicon at the same time as depositing the cobalt metal at more than 600 ℃ over orientation silicon substrate bearing by performing the process in the reactor (reaction chamber) at a time by forming a CoSi 2 near the epitaxial layer (epitaxial layer), without performing more than 750 ℃ high temperature heat treatment to the single crystal or single crystal having simplifies the contact forming step is to the lower group is di-development more semiconductor device wiring process technology and associated elements raemgeup resistance.

도 1 은 소스, 드레인 및 폴리실리콘 게이트에서의 실리콘과 금속간의 종래의 스퍼터링(sputtering)법에 의한 실리사이드 형성방법을 개략적으로 나타낸 MOS 트랜지스터의 단면구조로서, 1 is a cross-sectional structure of the MOS transistor schematically showing a silicide formed by a conventional sputtering method (sputtering) method between the silicon and the metal of the source, drain and polysilicon gate,

(a)는 MOS 트랜지스터의 소스, 드레인, 게이트를 형성한 상태 (A) shows the state of forming the source of the MOS transistor, a drain, a gate

(b)는 스퍼터링에 의해 Co 또는 Ti 금속을 증착하고 그 위에 Ti 나 Co의 산화 와응집(agglomeration) 방지를 위한 보호층인 TiN을 증착한 상태 (B) the depositing a Co or Ti metal by sputtering, and depositing a protective layer of TiN for Ti and Co in the oxidation and coagulation (agglomeration) protection on the condition

(c)는 700℃ 이하에서 1차 열처리하여 소스, 드레인, 게이트에 금속과 실리콘의 1차 화합물인 다결정 CoSi나 C49 TiSi 2 가 형성된 상태 (c) is below 700 ℃ primary heat treatment by the source, the drain, the gate of the first compound of a metal and the polycrystalline silicon CoSi or TiSi 2 C49 is formed state

(d)는 미반응 금속 및 보호층을 에칭한 상태 (D) is a state in which etching unreacted metal and the protective layer

(e)는 800℃ 이상에서 2차 열처리를 하여 CoSi는 CoSi 2 로, C49 TiSi 2 는 C54 TiSi 2 로 안정된 실리사이드를 형성한 상태 (e) is a secondary heat treatment at above 800 ℃ by CoSi 2 is a CoSi, TiSi 2, C49 will form a stable state in which the silicide to C54 TiSi 2

도 2 는 본 발명의 화학기상증착법에 의한 CoSi 2 형성 공정을 개략적으로 나타낸 단면구조로서, 2 is a cross-sectional view schematically showing the CoSi 2 forming step by a chemical vapor deposition method of the present invention,

(a)는 MOS 트랜지스터의 소스, 드레인 및 게이트가 형성된 상태 (A) shows the state that the source, drain and gate of the MOS transistor formed

(b)는 화학기상증착법에 의해 600℃이상에서 Co의 증착과 동시에 실리콘과 인 시튜(in-situ) 실리사이드 형성 반응하여 소스, 드레인, 게이트에 CoSi 2 가 형 성된 상태 (b) is reacted to form the silicon deposition at the same time and in situ (in-situ) the silicide of Co at more than 600 ℃ by a chemical vapor deposition source, a drain, a gate-type CoSi 2 is generated status

(c)는 산화막 위의 Co 금속을 에칭한 상태 (C) is a state in which etching of the Co metal on the oxide film

도 3은 화학증착온도 550℃와 600℃에서 실리콘 표면의 X-선 회절패턴 도표이다. 3 is an X- ray diffraction pattern chart of the silicon surface in a chemical vapor deposition temperature of 550 ℃ and 600 ℃.

도 4 는 화학증착온도 650℃에서의 실리콘 표면의 X-선 회절패턴 도표이다. 4 is an X- ray diffraction pattern chart of the silicon surface of the chemical vapor deposition temperature of 650 ℃.

< 도면의 주요 부분에 대한 부호의 설명 > <Description of the Related Art>

(1) 실리콘 기판 (2) 산화막 (1) the silicon substrate 2, oxide films

(3) 게이트 (4) Co 또는 Ti 3, the gate (4) Co or Ti

(5) TiN 등 보호막 (6) CoSi 또는 C49 TiSi 2 (5) TiN, such as a protective film (6) CoSi or TiSi 2 C49

(7) CoSi 2 또는 C54 TiSi 2 (15)소스 (7) CoSi 2 or C54 TiSi 2 (15) source

(30) 드레인 30. Drain

본 발명은 MOS 트랜지스터의 소스(15), 드레인(30) 및 게이트(3)에서 직접 콘택(contact)이 가능한 CoSi 2 (7) 콘택을 제시한다. The invention proposes a possible CoSi 2 (7) directly contacts the contact (contact) from the source 15, drain 30 and the gate 3 of the MOS transistor. 본 발명에서 제안한 화학기상증착법을 이용한 콘택형성의 공정방법을 도2에 나타냈다. It exhibited a fair method of forming a contact with the proposed chemical vapor deposition method in the present invention in FIG. 공정을 간단히 설명하면 n+ 및 p+ 의 소스(15), 드레인(30)과 게이트(3)로 구성된 실리콘기판(1)을 600℃로 유지한 다음 시클로펜타디에닐코발트디카보닐[Co(C 5 H 5 )(CO) 2 ]나 비스시클로펜타디에닐코발트[Co(C 5 H 5 ) 2 ]등과 같은 코발트-금속유기물소스를 낮은 온도의 저장용기에서부터 반응기까지 가스상태로 직접 이동시키거나 수소, 질소 및 아르곤가스를 이용하여 반응기까지 이송시켜 화학기상증착법으로 증착하면 소스(15), 드레인(30) 위에서 증착되는 Co(4)와 실리콘과의 반응으로 실리콘기판(1)의 (100)방위와 같은 방위를 가지는 (100)방위의 에피택시층 CoSi 2 (7)가 바로 형성되고 게이트(3)위에는 다결정 CoSi 2 (7)가 바로 형성되며 산화물 위에는 Co(4)와 SiO 2 (7)가 반응하지 않고 남아있게 된다. Briefly the steps n + and p + source 15, drain 30 and gate (3) maintaining the silicon substrate (1) consisting of a 600 ℃ following cyclopentadienyl cobalt -dicarbonyl [Co (C 5 H 5) (CO) 2] or bis-cyclopentadienyl cobalt [Co (C 5 H 5) 2] cobalt such as - to to a metal organic source from the reservoir of the low temperature reactor directly to the gas state, or hydrogen, and nitrogen and using an argon gas was transferred to the reactor when deposited by chemical vapor deposition source 15, the reaction of the Co (4) and the silicon is deposited on the drain (30), such as a (100) orientation of the silicon substrate (1) epitaxial layer CoSi (100) orientation having the azimuth 2 (7) are directly formed the gate (3) above, and polycrystalline CoSi 2 7 is formed directly to Co (4) and SiO 2 (7) the reaction above the oxide thereby not remain. 이 때 소스(15), 드레인(30) 게이트(3)에서의 반응식은 아래와 같다. Scheme in this case the source 15, drain 30, gate (3) is as follows.

Co(C 5 H 5 )(CO) 2 + 2 Si → CoSi 2 + (C 5 H 5 ) ↑ + (CO) 2 Co (C 5 H 5) ( CO) 2 + 2 Si → CoSi 2 + (C 5 H 5) ↑ + (CO) 2 ↑

Co(C 5 H 5 ) 2 + 2 Si → CoSi 2 + 2 (C 5 H 5 ) ↑ Co (C 5 H 5) 2 + 2 Si → CoSi 2 + 2 (C 5 H 5) ↑

다음의 실시예에서 본 발명을 더 자세히 설명하고자 한다. It will be described in more detail the present invention in the following examples. 그러나 이 실시예가 본 발명의 기술적 범위를 한정하는 것은 아니다. However, not limited to this embodiment the technical scope of the present invention.

< 실시예 1 > <Example 1>

n+ 및 p+ 의 소스(15), 드레인(30), 게이트(3)로 구성된 실리콘기판(1)을 600℃로 유지한 다음, 코발트-금속유기물소스로서 시클로펜타디에닐코발트디카보닐[Co(C 5 H 5 )(CO) 2 ] 및 비스시클로펜타디에닐코발트[(C 5 H 5 ) 2 Co]를 저장용기에서부터 반응기까지 수소가스를 이용하여 이송한 후 화학기상증착법으로 증착하였다. n + and p + source 15, a drain 30, a gate (3) maintaining the silicon substrate (1) consisting of a 600 ℃, then a cobalt-as a metal organic source cyclopentadienyl cobalt -dicarbonyl [Co (C 5 H 5) (CO) 2 ] and bis-cyclopentadienyl cobalt [(C 5 H 5) 2 and then transported using the hydrogen gas Co] - from the storage vessel reactor it was deposited by chemical vapor deposition. 이때 저장용기의 온도에 따라 수소가스의 유량을 변화시켜야 하는데 이는 실제로 반응기내로 유입되는 코발트-금속유기물소스의 양을 최소로하여 코발트다이실리사이드가 기판위에 형성되도록 하기 위해서이다. The need to vary the flow rate of the hydrogen gas according to the temperature of the storage container, which the cobalt is actually introduced into the reactor - is to ensure that the amount of the organic metal source to at least the cobalt silicide formed on the die substrate. 저장용기의 온도가 상온일 경우에는 수소나 기타 이송가스를 사용하지 않고 코발트-금속유기물소스의 증기압만으로도 충분히 이송이 가능하여 매우 짧은 시간내에 코발트다이실리사이드를 기판위에 형성시킬 수 있다. Can be formed of cobalt di silicide within a sufficiently short time so the two can only vapor pressure of the organic metal source above the substrate can without the use of hydrogen or other transfer gases cobalt when the temperature of the storage vessel at room temperature. 그러나 이 경우에는 코발트박막의 증착속도가 매우 빠르기 때문에 50nm 이상의 두께로 증착하는 경우에는 에피택시층이 형성되기 어렵고 미반응한 코발트 박막이 기판과 반응하여 생성된 코발트다이실리사이드층 위에 형성되게 된다. In this case, however, it is to be formed on the thin film since the deposition rate of Co is very fast, if deposited to a thickness more than 50nm, it is difficult to form the epitaxial layers of the non-reacted cobalt film is reacted with the substrate produce a cobalt silicide layer die. 또한 이 외에 다른 코발트-실리콘간 화합물이 형성될 수 있다. In addition, other cobalt also may be a silicon intermetallic compound formation. 저장용기의 온도를 0℃로 낮춘 경우에는 충분히 낮은 증착속도를 가지게 되어 에피택시층형성에 필요한 시간이 충분히 공급되기 때문에 100nm 이상의 두께를 가지는 에피택시층 코발트다이실리사이드도 형성시킬 수 있게된다. When lowering the temperature of the storage vessel to 0 ℃ it has been to have a sufficiently low deposition rate it is possible to form also the epitaxial layer of cobalt di silicide has a thickness of 100nm or more, since the time required for forming the epitaxial layer sufficiently supplied. 또한 이 때에는 수소나 기타 다른 이송가스를 이용하여 증착을 하여도 기판위에서 에피택시층 코발트다이실리사이드가 형성된다. In addition, when hydrogen or the other epitaxial layer of cobalt di silicide is formed on the substrate even by using a vapor deposition using a different conveying gas.

< 실시예 2 > <Example 2>

기판온도 550℃에서 코발트-금속유기물소스로서 비스시클로펜타디에닐코발트[Co(C 5 H 5 ) 2 ]를 사용하고 <실시예1>과 같이 화학기상증착법으로 증착하였다. Cobalt at a substrate temperature of 550 ℃ - as a metal organic source was used as the bis-cyclopentadienyl cobalt [Co (C 5 H 5) 2] , and deposited by chemical vapor deposition, such as <Example 1>.

증착시 실리콘기판(1)에 CoSi 2 (7)의 형성됨을 나타내는 X-선 회절패턴을 도3에 표시하였다. The X- ray diffraction pattern showing a formed of CoSi 2 (7), at the time of depositing the silicon substrate 1 are shown in FIG. 저장용기의 온도를 0℃로 유지하고 기판온도가 550℃의 경우 코발트박막의 증착속도가 매우 느리고 코발트다이실리사이드를 형성시킬 수 있는 형성온도 이하이므로 실리콘기판(1)위에서 어떠한 반응도 일어나지 않으므로 실리콘기판(1)에서는 실리콘 이외에 어떤 상도 형성되지 않는다. Maintaining the temperature of the storage vessel to 0 ℃ and the substrate temperature in the case of 550 ℃ because cobalt thin film can be deposited speed is very slow and forming a cobalt di silicide formation temperature than so happen any reaction on the silicon substrate (1) of the silicon substrate ( 1) the top coat is not formed which in addition to silicon. 그러나 증착시간을 길게하면 코발트 및 코발트화합물이 실리콘기판(1)위에 형성될 수 있다. However, when longer deposition times are cobalt or cobalt compound it can be formed on a silicon substrate (1). 600℃에서는 (100)방위의 실리콘과 같은 (100)방위를 가지는 에피택시층 CoSi 2 (7)가 형성되었음을 알 수 있다. In 600 ℃ 100, it can be seen that the formation of epitaxial layer CoSi 2 (7) having a (100) orientation, such as silicon of orientation. 도4는 기판온도 650℃에서 (100) 방위의 에피택시층 CoSi 2 (7)가 형성되었음을 알 수있다. Figure 4 it can be seen that the epitaxial layer CoSi 2 (7) the formation of (100) orientation at a substrate temperature of 650 ℃. 이 때 SiO 2 (2)위의 코발트(4)는 SiO 2 (2)와 반응하지 않으며 이 코발트(4)를 NH 4 OH/H 2 O 2 나 HNO 3 /H 2 O 또는 H 2 SO 4 /H 2 O 2 용액으로 에칭하면 된다. Cobalt (4) above is when SiO 2 (2) is a SiO 2 (2) and does not react with the cobalt (4) NH 4 OH / H 2 O 2 or HNO 3 / H 2 O or H 2 SO 4 / H 2 O 2 is etching with a solution. 위와 같이하여 얻어진 코발트실리사이드 박막의 면저항은 1∼2Ω/□로서 스퍼터링에 의한 방법과 비교해 볼 때 비슷한 면저항 값을 나타내고 있고 비저항 값은 약 16 μΩ·cm 이다. The sheet resistance of the cobalt silicide thin film obtained as described above and represents the same sheet resistance value when compared to the method by sputtering as 1~2Ω / □, and the specific resistance value is about 16 μΩ · cm. 또한 에피택시층의 형성여부 및 에피택시층과 실리콘기판(1) 과의 접합여부를 나타내는 RBS분석시 최소수율값인 X min 값은 9%로 나타났으며 이것으로 매우 우수한 특성의 에피택시층이 형성됨을 알 수 있다. In addition, the epitaxial layer of excellent characteristics which were X min value, the minimum yield value when RBS analysis showing the joint whether the epitaxial whether the formation of the layer and the epitaxial layer and the silicon substrate 1 has appeared to 9% it can be seen formed.

종래의 스퍼터링을 이용한 방법에서는 스퍼터링공정 후에 수행되는 1차 열처리 공정 및 2차 고온 열처리공정 그리고 보호층인 TiN 증착공정등의 여러 공정이 필요하나 본 발명은 화학기상증착법을 이용함으로써 콘택형성시 저항이 낮고 재현성이 높은 에피택시층 CoSi 2 를 여러단계의 열처리공정을 거치지 않고 금속증착과 동시에 형성시킬 수 있어 콘택 배선공정을 크게 단순화 시킬 수 있으며 초미세구조의 콘택 배선공정에서 도포성이 우수하고, 균일한 계면을 형성시킬 수 있다. The present invention one need several processes, such as the primary heat treatment step and the second high-temperature heat treatment step and the protective layer of TiN deposition process performed in the method using the conventional sputtering after the sputtering process is the resistance when the contact is formed by using a chemical vapor deposition method low and it is possible to reproducible form a high epitaxial layer CoSi 2 at the same time as the metallization, without going through a multi-phase heat treatment process can greatly simplify the contact wiring process, and coating property is excellent in a contact wiring process of the second microstructure, and homogeneous it is possible to form a surface. 뿐만 아니라 공정온도가 600℃ 정도로 낮고 에피택시층 실리사이드를 형성하므로 실리사이드와 실리콘 간의 계면 결함이 적어 소스, 드레인에서 우수한 접합특성을 얻을 수 있어 기가디램급 이상의 고집적회로 초미세 반도체 소자의 제조에 활용할 수 있다. As well as the process temperature is low as 600 ℃ forms a epitaxial layer silicide source the interface defect between the silicide and silicon less, to obtain a good bonding characteristic at the drain's group D can be utilized in the production of fine semiconductor elements or more integrated circuits seconds raemgeup have.

Claims (3)

  1. 화학기상증착법을 이용한 MOS 트랜지스터의 소스, 드레인, 게이트에 코발트 다이실리사이드 콘택형성 방법에 있어서, 코발트-금속유기물 소스를 반응기에 주입하여 증착온도를 600℃ 이상으로 하여 코발트를 증착하는 단계와, 전기 단계에 의해 소스(15), 드레인(30)에 에피택시층 CoSi 2 (7)를 형성시키고, 게이트(3)에 다결정 CoSi 2 (7)를 형성시키는 단계와, 산화막 위의 코발트 금속을 에칭하는 단계를 포함함을 특징으로 하는 코발트다이실리사이드 콘택형성방법. In the source, drain, cobalt di silicide contact formation method to the gate of a MOS transistor using a chemical vapor deposition method, a cobalt-step with electric depositing cobalt and the metal organic source and injected into the reactor to a deposition temperature less than 600 ℃ and forming the source 15, drain 30, epitaxial layer CoSi 2 (7), the polycrystalline CoSi 2 (7) to form and, a gate (3) by, in the step of etching the cobalt metal of the oxide film above, also it includes cobalt di silicide contact formation method characterized by the.
  2. 제 1 항에 있어서, CoSi 2 (7) 형성단계에서 코발트-금속유기물소스로 비스시클로펜타디에닐코발트[(C 5 H 5 ) 2 Co], 코발트트리카보닐나이트로실[Co(CO) 3 NO], 시클로펜타디에닐코발트카보닐[C 5 H 5 Co(CO) 2 ], 코발트카보닐[Co 2 (CO) 8 ], 테트라코발트도데카카보닐[Co 4 (CO) 12 ]에서 선택된 1종임을 특징으로 하는 코발트다이실리사이드 콘택형성방법. According to claim 1, CoSi 2 (7) from the forming cobalt-bis-cyclopentadienyl cobalt as metal organic source [(C 5 H 5) 2 Co], cobalt tricarbonyl chamber nitro, [Co (CO) 3 NO], cyclopentadienyl cobalt carbonyl [C 5 H 5 Co (CO ) 2], cobalt carbonyl [Co 2 (CO) 8] , tetra cobalt FIG deca-carbonyl [Co 4 (CO) 12] selected from 1 kinds of cobalt di silicide contact formation method, characterized in that.
  3. 제 1 항에 있어서, 화학기상증착법으로 CoSi 2 (7) 형성 후 반응기 내에서 열처리 또는 급속열처리하여 더욱 안정된 비저항을 갖는 CoSi 2 (7)를 형성하는 것을 특징으로 하는 코발트다이실리사이드 콘택형성방법. According to claim 1, wherein the chemical vapor deposition CoSi 2 (7) after forming CoSi 2 cobalt di silicide contacts forming method so as to form a (7) having a heat treatment or a more stable specific resistance to rapid thermal processing in the reactor to.
KR1019980019299A 1998-05-27 1998-05-27 Method for forming cobalt disilicide contact hole by chemical vapor deposition process KR100296117B1 (en)

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US6727169B1 (en) 1999-10-15 2004-04-27 Asm International, N.V. Method of making conformal lining layers for damascene metallization
US6777565B2 (en) 2000-06-29 2004-08-17 Board Of Trustees, The University Of Illinois Organometallic compounds and their use as precursors for forming films and powders of metal or metal derivatives
US7186630B2 (en) 2002-08-14 2007-03-06 Asm America, Inc. Deposition of amorphous silicon-containing films
US7687383B2 (en) 2005-02-04 2010-03-30 Asm America, Inc. Methods of depositing electrically active doped crystalline Si-containing films
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