KR100271655B1 - Duty cycle correction circuit - Google Patents

Abstract

PURPOSE: A duty cycle correcting circuit is provided to be capable of promoting the information storage in a power saving mode and return to a normal mode by digitalizing information for correcting the phases of points in which duty cycles are matched to have a phase difference of 180 deg with a locking point. CONSTITUTION: A first clock delay adder(201) calculates continuous two clocks(CKn,CKn+1) to generate a clock(CLK) in accordance with a control signal(CTL). A second clock delay adder(202) calculates continuous two clocks(/CKn,/CKn+1) to generate a clock(/CLK) in accordance with a control signal(/CTL). A duty matching part(203) receives respective clocks(CLK,/CLK) of the first and second clock delay adders(201,202) to compensate their phases, thereby outputting clocks(DMC,/DMC) of 180 deg phase difference. An edge adder(204) receives the output signals(DMC,/DMC) of the duty matching part(203) to output a clock(DCLK) in a rising edge of the clock(DMC) as high and output a clock(DCLK) in a rising edge of the clock(/DMC) as low. First/second clock buffers(205,206) respectively output the output of the edge adder(204) to a main block and sub blocks.

Description

Duty cycle compensation circuit

The present invention relates to duty cycles and, more particularly, to duty cycle correction circuits.

1 is a block diagram of a conventional duty cycle correction circuit, K _n , K _{n + 1} Th clock ( CK _n , CK _{n + 1} ) Is calculated according to the control signal (CTL) to CLK ) ( Clock delay adder 101 and duty cycle error value DCE ) ( Output clock of the clock delay adder 101 according to CLK ) ( ) To compensate for duty cycle corrected clock (COUT) ( ) And the duty cycle corrector 102 for outputting the output signal of the duty cycle corrector 102. COUT ) ( ) Is a clock buffer (104, 105) for transmitting the main block and the sub block, respectively, and the output signal ( COUT ) ( ) To check the duty cycle error ( DCE ) ( ) Is configured as a duty cycle detector 103 for outputting the duty cycle corrector 102.

The duty cycle detection unit 103 has a clock CLK ( Is composed of two circuits for detecting the duty cycle error. The circuit operated by the clock CLK is turned on when the clock CLK is high, as shown in the circuit diagram of FIG. ) Is a switching element Q1 for charging a charge, and a switch element Q2 for turning on when the clock CLK is low to discharge the charging charge of the capacitor C.

The duty cycle corrector 102 may include a clock CLK at a gate of a transistor Q1 and Q2 whose source is grounded through a first current source. ) Are applied to the gates of transistors Q3 and Q4 each having a source grounded through a second current source. Are applied to the other terminal of the resistor R1 to which the voltage Vcc is applied to one terminal thereof, and the drain of the transistors Q1 and Q3 is commonly connected to each other. A clock that outputs and commonly connects a drain of the transistors Q2 and Q4 to the other terminal of the resistor R2 to which the voltage Vcc is applied to one terminal thereof, and the duty cycle is corrected at the connection point thereof. ) Is configured to output

Referring to the operation of the conventional circuit as follows.

The clock delay adder 101 has a predetermined phase difference. K _n , K _{n + 1} Th clock ( CK _n , CK _{n + 1} ) Is calculated according to the control signal (CTL) to CLK ) ( ) And its clock ( CLK ) ( ) Is transmitted to the duty cycle correction unit 102.

The output clock of the duty cycle corrector 102 COUT ) ( Are transmitted through the respective clock buffers 104 and 105 to the main block and the sub block.

At this time, the duty cycle detector 103 is a clock (transmitted to the sub-block through the clock buffer 105) COUT ) ( ) And check the duty cycle error amount ( DCE ) ( ) Is transmitted to the duty cycle correction unit 102.

As a result, the duty cycle detection unit 103 performs the duty cycle error amount DCE in the duty cycle detection unit 103 ( Clock CLK in clock delay adder 101 by ) To compensate for the duty cycle of the clock (COUT) ( ) Will be printed.

In the above, the duty cycle corrector 102 has a predetermined phase difference. K _n , K _{n + 1} Th clock ( CK _n ) ( CK _{n + 1} Clock in the clock delay adder 101, CLK ) ( ) And the clock ( COUT ) ( ) And the operation of the duty cycle detector 103 in the transmission to the main block through the clock buffer 104 will be described with reference to the circuit of FIG.

First, when the pull-up switching element Q5 is turned on during the high period of the clock CLK, the charge is charged to the capacitor C and when the pull-down switching element Q6 is turned on during the low period of the clock CLK, the capacitor ( The charging charge of C) is discharged.

If the high section of the clock CLK is longer than the low section as shown in FIG. 4C, charges are charged to the capacitor C during the entire section. In contrast, the high section of the clock CLK as shown in FIG. If it is shorter than the low period, the charge charge of the capacitor C will be discharged during the entire period. Also, if the high period and the low period of the clock CLK coincide with each other as shown in FIG. No charge or discharge occurs.

Therefore, the duty cycle error DCE is detected by the charge / discharge amount of the capacitor C.

However, the duty cycle detection unit 103 uses two duty cycle detectors as shown in the circuit of FIG. ) To perform the opposite operation.

Therefore, the larger the difference between the output values in the two circuits for detecting the duty cycle error, the larger the duty cycle error, and the smaller the difference, the smaller the duty cycle error.

In addition, the operation of the duty cycle correction unit 102 will be described in the circuit of FIG. 3 as follows.

In order to increase the high period of the clock CLK, the fall time of the clock CLK may be increased. This may be achieved by reducing the pull-down current, which is performed by a current steering method.

The opposite can also be done in the same way.

In practice, as shown in the circuit of FIG. 3, when the current needs to be reduced by using a differential amplifier, the current is drawn more, and when the current is increased, the current is less taken.

That is, when the high period of the clock COUT is to be increased, the duty cycle error amount DCE is reduced in the falling period of the clock CLK.

Accordingly, the turn-on amount of the transistors Q1 and Q4 is reduced to increase the high period of the clock COUT.

On the contrary, when the high period of the clock COUT is to be reduced, the duty cycle error amount (in the rising period of the clock CLK) Increased).

As a result, the turn-on amount of the transistors Q1 and Q4 increases to reduce the high period of the clock COUT.

In order to continue operating the DLL in the low power mode, the duty cycle error sampling is performed through the clock buffer 105. The duty cycle matching of the clock buffers 104 and 105 is required to correct the duty cycle of the clock buffer 104. This is important.

However, the prior art must include an integrator that uses a large capacitor to compensate for the duty cycle.

Therefore, conventionally, in order to remember the amount of charge charged to the capacitor C during the power-saving mode, the leakage current of the capacitor C should be taken into consideration, and the capacitor C should return to the normal operation mode again. ), There was a difficulty in considering correction of the changed charge amount.

In particular, there is a difficulty in preserving and restoring the memory state in the power saving mode by using an analog storage.

Accordingly, the present invention relates to a device for storing locking information and duty cycle information during a power saving mode in order to improve the conventional problem, the information for phase correction so that the duty cycle coincides with the locking position by 180 degrees. It is an object of the present invention to provide a duty cycle correction circuit invented to facilitate information preservation in the power saving mode and restoration to the normal mode by digitization.

1 is a block diagram of a conventional duty cycle correction circuit.

FIG. 2 is a circuit diagram illustrating a duty cycle error detector in FIG. 1. FIG.

FIG. 3 is a circuit diagram illustrating a duty cycle correction unit in FIG. 1. FIG.

4 is an exemplary view showing a duty cycle detection waveform.

5 is a block diagram showing an embodiment of the present invention.

6 is an operation timing diagram of FIG. 5.

Explanation of symbols on the main parts of the drawings

201,202: clock delay adder 203: duty matching unit

204: edge adder 205,206: clock buffer

In order to achieve the above object, the present invention provides two continuous clocks according to a control signal (CTL). CK _n , CK _{n + 1} ) To calculate the clock ( CLK And a first clock delay adder for generating ) Two consecutive clocks ( , ) To calculate the clock ( A second clock delay adder for generating?) And each clock CLK in the first and second clock delay adders ( ) Is compensated for the phase by input, and the clock (DMC) having a phase difference of 180 degrees ( ) And a duty matching section for outputting the output signal (DMC) ( ) As the input and outputs the clock DCLK high on the rising edge of the clock DMC. Edge adder for outputting the clock DCLK low at the rising edge of the < RTI ID = 0.0 >)< / RTI > and first and second clock buffers for outputting the output clock DCLK in the edge adder to the main block and the sub-block, respectively. Should be

The first and second clock delay adders are configured as a phase interpolator.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 5 is a block diagram showing an embodiment of the present invention, and as shown therein, has a phase difference of 45 degrees from each other according to a control signal CTL. K _n , K _{n + 1} Th clock ( CK _n , CK _{n + 1} ) To calculate the clock ( CLK And a clock delay adder 201 for generating Have a phase difference of 45 degrees K _n , K _{n + 1} Th clock ( , ) To calculate the clock ( Clock delay adder 202 for generating a clock delay adder 202 and each clock CLK in the clock delay adder 201 and 202. ) Is compensated for the phase by input, and the clock (DMC) having a phase difference of 180 degrees ( ) And a duty matching section 203 for outputting the output signal (DMC) ( ) As the input and outputs the clock DCLK high on the rising edge of the clock DMC. Edge adder 204 for outputting clock DCLK low on the rising edge of < RTI ID = 0.0 >)< / RTI > and clock buffer 205 for outputting output clock DCLK in this edge adder 204 to the main block and sub-block, respectively. 206).

The clock delay adder 201 and 202 is configured as a phase interpolator.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

The clock delay adder 201 has a phase difference of 45 degrees. K _n , K _{n + 1} Th clock ( CK _n , CK _{n + 1} ) Is calculated according to the control signal CTL to obtain a clock ( CLK And the clock delay adder 202 has a phase difference of 45 degrees. K _n , K _{n + 1} Th clock ( , ) The control signal ( ) And the clock as shown in FIG. ).

At this time, the output signal CLK of the clock delay adder 201 and 202 ( Is output to the duty matcher 203, and the duty matcher 203 is configured as the clock CLK ( Is performed as a phase compensation operation by inputting a clock (DMC) as shown in Fig. 6 (c) (d) having a phase difference of 180 degrees. ) Is output to the edge adder 204.

Accordingly, the edge adder 204 outputs the clock DCLK high on the rising edge of the clock DMC, and the clock ( The clock DCLK is output low on the rising edge of the output circuit to output the clock DCLK as shown in FIG. 6E with the duty cycle corrected.

At this time, the clock buffers 205 and 206 are buffered and output to the main block and the sub block because the clock DCLK of the edge adder 204 has a small driving capability, and the duty cycle may be changed during the buffering. As a result, the clock buffers 205 and 206 are composed of two buffers having different delays, thereby outputting the clock MCLK as shown in FIG. 6 (f) in which the duty cycle is finally compensated.

As described in detail above, the present invention has an effect of facilitating information preservation and restoration of the normal mode in the power saving mode by digitizing the duty cycle corrector.

Claims (3)

An apparatus for storing locking information and duty cycle information during a power saving mode, comprising two clocks consecutively according to a control signal (CTL) CK _n , CK _{n + 1} ) To calculate the clock ( CLK And a first clock delay adder for generating ) Two consecutive clocks ( , ) To calculate the clock ( A second clock delay adder for generating?) And each clock CLK in the first and second clock delay adders ( ) Is compensated for the phase by input, and the clock (DMC) having a phase difference of 180 degrees ( ) And a duty matching section for outputting the output signal (DMC) ( ) As the input and outputs the clock DCLK high on the rising edge of the clock DMC. Edge adder for outputting the clock DCLK low at the rising edge of the < RTI ID = 0.0 >),< / RTI > Duty cycle correction circuit. The duty cycle correction circuit of claim 1, wherein the first and second clock delay adders comprise a phase interpolator. The method of claim 1, wherein the continuous clock ( CK _n , CK _{n + 1} ) ( , ) Are each 45 degrees out of phase difference correction circuit.