KR100265842B1 - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- KR100265842B1 KR100265842B1 KR1019930030782A KR930030782A KR100265842B1 KR 100265842 B1 KR100265842 B1 KR 100265842B1 KR 1019930030782 A KR1019930030782 A KR 1019930030782A KR 930030782 A KR930030782 A KR 930030782A KR 100265842 B1 KR100265842 B1 KR 100265842B1
- Authority
- KR
- South Korea
- Prior art keywords
- etching
- pattern
- film
- oxide film
- tantalum oxide
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910001936 tantalum oxide Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 16
- 230000003647 oxidation Effects 0.000 claims abstract description 3
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 14
- 150000004706 metal oxides Chemical class 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 10
- 230000004888 barrier function Effects 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 238000000059 patterning Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1a도 내지 제1e도는 본 발명의 일실시예에 따른 다결정 실리콘막 패턴형성공정 단면도.1A to 1E are cross-sectional views of a polycrystalline silicon film pattern forming process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 5: 실리콘 산화막 2, 2' : 다결정실리콘막1, 5: silicon oxide film 2, 2 ': polycrystalline silicon film
3, 3' : 탄탈륨 산화막 4 : 감광막 패턴3, 3 ': tantalum oxide film 4: photosensitive film pattern
본 발명은 미세 패턴을 형성할 수 있는 반도체 소자 제조 방법에 관한 것이다.The present invention relates to a semiconductor device manufacturing method capable of forming a fine pattern.
디램(Dynamic Random Access Memory, DRAM)을 비롯한 반도체 소자의 집적도가 증가함에 따라 보다 미세한 패턴을 제조할 수 있는 기술이 절실히 요구되고 있다.As the degree of integration of semiconductor devices including DRAM (Dynamic Random Access Memory, DRAM) increases, there is an urgent need for a technology capable of manufacturing finer patterns.
서브-마이크론의 디자인롤을 갖는 고집적 소자에서 기존의 식각기술을 이용하여 다결정실리콘 패턴을 형성하는데는 크게 2가지의 어려운 점이 있다.In a highly integrated device having a sub-micron design roll, there are two major difficulties in forming a polysilicon pattern using a conventional etching technique.
첫째로, 다결정실리콘막의 식각 장벽(Barrier)으로 감광막을 사용할 경우, 식각 선택비(Etching Selectivity)로 인하여 감광막을 두껍게 도포하여야하며 이로 인해 현재의 노광장비로는 원하는 크기의 미세 패턴을 정확하게 노광하기 어렵다.First, when the photoresist film is used as an etch barrier (barrier) of the polysilicon film, the photoresist film needs to be thickly applied due to etching selectivity, which makes it difficult to accurately expose a fine pattern of a desired size with current exposure equipment. .
둘째로, 다결정 실리콘막의 식각시 장벽막으로 실리콘산화막(SiO2)사용할 경우에는 실리콘막과 실리콘산화막의 식각 선택비로 인해서 실리콘산화막을 두껍게 형성하여야 한다. 이로 인해 스텝커버리지(step coverage) 특성이 악화되며 또한 후속 공정시 공정이 복잡해지는 등의 문제를 안고 있다.Second, in the case of using a silicon oxide film (SiO 2 ) as a barrier layer during etching of the polycrystalline silicon film, the silicon oxide film should be formed thick due to the etching selectivity between the silicon film and the silicon oxide film. As a result, the step coverage characteristics are deteriorated and the process is complicated in subsequent processes.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 기존의 식각기술 및 노광장비를 그대로 이용하면서도 보다 용이하게 미세 패턴을 형성할 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method of manufacturing a semiconductor device that can easily form a fine pattern while using the existing etching technology and exposure equipment as it is.
상기 목적을 달성하기 위한 본 발명은, 미세 패턴을 이를 다결정실리콘막을 형성하는 제1단계; 상기 다결정실리콘막 상에 금속산화막을 형성하는 제2단계; 상기 금속산화막을 선택적으로 식각하여 식각마스크로 이용될 금속산화막 패턴을 형성하는 제3단계; 및 상기 금속산화막 패턴을 식각마스크로 이용하여 상기 다결정실리콘막을 식각함으로써 상기 다결정실리콘막으로 이루어지는 미세 패턴을 형성하는 제4단계를 포함하는 반도체 소자 제조 방법을 제공한다.The present invention for achieving the above object, the first step of forming a fine pattern polycrystalline silicon film; Forming a metal oxide film on the polysilicon film; Selectively etching the metal oxide layer to form a metal oxide layer pattern to be used as an etching mask; And a fourth step of forming a fine pattern made of the polycrystalline silicon film by etching the polysilicon film using the metal oxide film pattern as an etching mask.
이하, 첨부된 도면을 참조하여 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1e도는 본 발명의 일실시예에 따른 공정 단면도로, 도면 부호 1, 5는 실리콘 산화막, 2 및 2'는 다결정실리콘막, 3 및 3'는 탄탈륨 산화막, 4는 감광막 패턴을 각각 나타낸다.1A to 1E are cross-sectional views of a process according to an exemplary embodiment of the present invention, wherein 1 and 5 are silicon oxide films, 2 and 2 'are polycrystalline silicon films, 3 and 3' are tantalum oxide films, and 4 are photoresist patterns. Represent each.
제1a도는 실리콘산화막(1) 상부에 형성된 다결정실리콘막(2)의 식각패턴을 형성하기 위해, 상기 다결정실리콘막(2) 상부에 탄탈륨산화막(Ta2O6, 3)을 100 내지 200Å 두께 형성한 단면도이다.FIG. 1A illustrates a tantalum oxide film (Ta 2 O 6 , 3) having a thickness of 100 to 200 Å on the polysilicon film 2 to form an etching pattern of the polysilicon film 2 formed on the silicon oxide film 1. One cross section.
이때, CVD 방법으로 상기 탄탈륨산화막을 형성하거나 또는 탄탈륨을 스퍼터링하여 증착한 후 산화시켜 탄탈륨산화막을 형성하며, 이렇게 형성된 탄탈륨산화막은 실리콘막 식각가스에 대해 높은 선택비(100:1 이상)를 가지며, 다른 금속산화막도 가능하다.In this case, the tantalum oxide film is formed by CVD or by sputtering and depositing tantalum and then oxidizing to form a tantalum oxide film. The tantalum oxide film thus formed has a high selectivity (100: 1 or more) with respect to silicon film etching gas, Other metal oxide films are also possible.
제1b도는 상기 탄탈륨산화막(3) 상부에 탄탈륨산화막만 식각할 수 있으며, 정확하게 레티클(reticle)상이 패턴이 노광될 수 있도록 4000Å 이하로 최소 두께의 감광막을 도포한 후 노광하여 감광막 패턴(4)을 형성한 상태의 단면도이다.In FIG. 1B, only the tantalum oxide film can be etched on the tantalum oxide film 3, and the photosensitive film pattern 4 is exposed by applying a photosensitive film having a minimum thickness of 4000 Å or less so that the pattern on the reticle can be accurately exposed. It is sectional drawing of the state formed.
제1c도는 상기 감광막 패턴(4)을 식각장벽(Etching Barrier)으로 실리콘산화막 식각가스, 예를들면 F계인 CHF3, CF4등으로 상기 탄탈륨산화막(3)만 식각하여 탄탈륨산화막(3') 패턴을 형성하고, 감광막 패턴(4)을 제거한 상태의 단면도이다. 이후, 탄탈륨산화막(3') 패턴을 800℃ 이상의 고온 열처리 공정으로 결정화시키면 Ta-O 결합력이 증대되고 따라서 다결정실리콘막과 탄탈륨산화막의 식각선택비는 더욱 높아지게 된다.FIG. 1C illustrates that the photoresist pattern 4 is etched using an etching barrier, and only the tantalum oxide layer 3 is etched by etching a silicon oxide layer etching gas, for example, F-based CHF 3 or CF 4 . Is a cross-sectional view of a state in which the photosensitive film pattern 4 is formed. Subsequently, when the tantalum oxide film 3 'pattern is crystallized by a high temperature heat treatment process of 800 ° C. or higher, Ta-O bonding force is increased, thereby increasing the etching selectivity of the polysilicon film and the tantalum oxide film.
제1d도는 상기 열공정을 통해 결정화된 탄탈륨산화막(3') 패턴을 식각장벽으로 이용하여 상기 다결정실리콘막(2)을 식각하여 미세 패턴을 형성한 상태의 단면도이다.FIG. 1D is a cross-sectional view of a state in which a fine pattern is formed by etching the polysilicon film 2 using the tantalum oxide film 3 'pattern crystallized through the thermal process as an etching barrier.
제1e도는 패턴 형성된 다결정실리콘막(2')의 식각손실(Etching Damage) 및 고유전 특성을 지닌 탄탈륨산화막이 다결정실리콘막(2')과 직접 접촉되는 것을 방지하기 위해 산화(Oxidation) 공정을 행하여 실리콘산화막(5)을 형성한 상태의 단면도이다.FIG. 1E illustrates an oxidation process in order to prevent the tantalum oxide film having etching damage and high dielectric properties of the patterned polysilicon film 2 'from coming into direct contact with the polysilicon film 2'. It is sectional drawing of the state in which the silicon oxide film 5 was formed.
상기와 같이 이루어지는 본 발명은 다결정실리콘막에 대해 식각선택비가 높은 금속산화막, 예를 들면 탄탈륨 산화막을 식각 장벽으로 사용함으로써, 새로운 장비의 추가구입 없이 기존의 노광장비를 이용하여 미세 소자를 구현할 수 있는 효과가 있다.According to the present invention, the metal oxide film having a high etching selectivity, for example, a tantalum oxide film, may be used as an etch barrier with respect to the polycrystalline silicon film. Thus, the microdevice may be implemented using existing exposure equipment without additional purchase of new equipment. It works.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것은 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930030782A KR100265842B1 (en) | 1993-12-29 | 1993-12-29 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930030782A KR100265842B1 (en) | 1993-12-29 | 1993-12-29 | Semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950021159A KR950021159A (en) | 1995-07-26 |
| KR100265842B1 true KR100265842B1 (en) | 2000-11-01 |
Family
ID=19373766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930030782A KR100265842B1 (en) | 1993-12-29 | 1993-12-29 | Semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100265842B1 (en) |
-
1993
- 1993-12-29 KR KR1019930030782A patent/KR100265842B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR950021159A (en) | 1995-07-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100376628B1 (en) | Conductive Interconnect Structure in Integrated Circuit and Method of Forming Conductive Interconnect | |
| US6136679A (en) | Gate micro-patterning process | |
| JPH0621018A (en) | Dry etching method | |
| US6211557B1 (en) | Contact structure using taper contact etching and polycide step | |
| KR100265842B1 (en) | Semiconductor device manufacturing method | |
| KR100256057B1 (en) | A method of fabricating a semiconductor device | |
| US5902133A (en) | Method of forming a narrow polysilicon gate with i-line lithography | |
| US6583036B1 (en) | Method of manufacturing a semiconductor device | |
| KR100367695B1 (en) | Method for forming via contact in semiconductor device | |
| JPH1056021A (en) | Semiconductor device and manufacture thereof | |
| US20020137331A1 (en) | Method of forming contact holes of reduced dimensions by using reverse-transcription process | |
| KR100911864B1 (en) | Method of manufacturing semiconductor device | |
| JPH07226396A (en) | Pattern forming method | |
| KR100205095B1 (en) | Method for forming bit line of semiconductor device | |
| KR100309133B1 (en) | Method for manufacturing metal interconnection of semiconductor device | |
| KR100275934B1 (en) | A method for forming fine concuctive line of semiconductor device | |
| KR0130379B1 (en) | Manufacturing method of semiconductor device | |
| KR100305642B1 (en) | Method for forming contact hole of semiconductor device | |
| KR100281269B1 (en) | Gate electrode formation method of semiconductor device | |
| KR100399966B1 (en) | Method for manufacturing semiconductor device | |
| KR20050068363A (en) | Method for fabricating thin pattern using the hard mask | |
| JPH06295888A (en) | Fabrication of semiconductor device | |
| KR100365745B1 (en) | Method for forming contact hole in semiconductor device | |
| KR950009293B1 (en) | Single layer resist patterning method enhanced etching selective ration | |
| KR100226790B1 (en) | Method of manufacturing capacitor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20080527 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |