KR100231965B1 - High performance interconnection system for an integrated circuit - Google Patents

Abstract

Semiconductor integrated circuit devices include a high performance interconnect structure having a plurality of interconnect portions each structurally separated from the remaining interconnect portions except for electrical contacts. In one embodiment, each interconnect portion is substantially surrounded by a layer of dielectric material, with a gap between each adjacent layer of dielectric material. In another embodiment, an electrically conductive material layer is preferably formed on the enclosed dielectric layer so as to fill in the gaps between adjacently enclosed dielectric material layers. The electrically conductive material layer acts as a ground plate and heat sink.

Description

High Performance Interconnect System for Integrated Circuits

1 is a cross-sectional view schematically showing the manufacturing steps of a preferred method of manufacturing a device according to the invention.

2 is a cross-sectional view schematically illustrating the formation of a coaxial interconnect line in accordance with the present invention.

3 is a cross-sectional view schematically showing the manufacturing steps of a preferred method of alternatively manufacturing a device according to the invention.

4 is a cross-sectional view schematically showing a manufacturing step involved in a preferred method of alternatively manufacturing a device according to the invention.

[Field of Invention]

TECHNICAL FIELD The present invention generally relates to semiconductor integrated circuit devices, and more particularly, to a system for interconnecting devices constituting integrated circuits.

[Description of Prior Art]

As the device integration of Very Large Scaled Integrated (hereinafter referred to as "VLSI") circuits increases, many problems related to the fabrication and functionality of the interconnects will increase. This trend not only necessitates a dramatic decrease in the inclination of the metal on either level, but also a need to increase the number of inclined metal levels matched in this way. The design of this feature requires high speed bipolar and MOS logic elements to form a gate array and main frame computer with tens of thousands to hundreds of thousands of gates. In the next decade, it will be common to have three to four levels of highly integrated interconnects on metal gradients approaching 2 microns. A chip with an area of one square centimeter can potentially have tens to hundreds of meters of interconnects to effectively use all the logic elements on the die.

In a more complex problem, this entire clock cycle is in some cases well extended to the gigahertz range generated in such microwave integrated circuits. This will be especially true for bipolar ECL devices made with already developed technology. In many cases, the signal wavelengths propagating along the interconnects approach the edge dimensions of the die, which makes high speed interconnect coupling a problem with current printed circuit board level shifts on a chip.

This necessity raises several interrelated problems. For example, the actual cross section of the interconnect will decrease unless the ratio of height to width is increased. If the part of the current density is not reduced equivalently or if the metal cross section is reduced without using a physically rigid conductor, the probability of failure due to electron transfer will increase. In addition, the thermal dissipation of energy generated by such a large device in operation will also adversely affect the electron transfer shielding of the interconnects. This also increases capacitive and inductive coupling between adjacent interconnects in the same plate if the height of the interconnects is increased in the mated inclined structure unless more effective device cooling is used. This coupling effect causes increased system noise and other pseudo-electrical effects that are critical to integrated circuit performance.

In addition, as the device operating speed increases, it is necessary to match the overall circuit impedance with the impedance of the external power supply for optimum device efficiency using less reflected power. This is especially true of VISL microwave circuits. Another problem arises when the cross section of the interconnect is reduced. If the length of the interconnect movement on the chip is very long (about 1 centimeter), the resistance per unit length increases as the large signal attenuates.

In general, the ratio of inductance per unit length to capacitance per unit length is more important from the designer's point of view than just the overall inductance or capacitance. In practice, this ratio determines the impedance characteristics of the interconnects. Based on this situation, it is desirable to be able to adjust the circuit to impedance mismatches caused by the L / C ratios realized through the design. This can be done, for example, by using a stub to match the circuit impedance with a power source connected from the outside world. However, the problems of attenuation and crosstalk continue to play a more important role in limiting the operation of ultrafast circuits and must be solved as different problems.

In view of the above, the height / width ratio of the interconnect level is vertically increased to maintain low resistance and attenuation, and coaxial shielding solutions are used to effectively eliminate undesirable interconnect coupling between interconnect parts. In addition, it will be necessary to match the impedance characteristics of the device and the power supply by using a stub adjustment technique on a chip as a final manufacturing step of the device manufacturing method.

Although the foregoing description has focused on the electrical needs of interconnect systems, it is necessary to recognize other physical manufacturing needs. As the device and interconnect lines approach each other, mechanical defects in the interconnect material can cause short circuits between adjacent metal lines. This effect provides device failure and reduced die yield. Heallocking is a mechanical defect that can cause a short circuit. This phenomenon is caused by the differential stress due to heat generation present between the interconnecting portions and the supporting material having substantially different coefficients of thermal expansion. The defect is manifested by random local deformation of the conductor material in the form of a bump projecting from the conductor surface. In some cases, these bumps are large enough to cause device failure by shorting the connectable adjacent levels to each other. Since the interconnect lines move closely to each other, such a deformation can be recognized as causing further short circuits of adjacent interconnect lines. This can be a serious problem, especially when no sealing material is used that can limit this deformation.

Thus, there is a need for an interconnect system in which unwanted electrical coupling between interconnect lines can be minimized. Second, there is a need to keep the resistance of the interconnect portion small by using a larger line cross-sectional area, where attenuation loss cannot be recognized and the effects of electron transfer are prevented. It is also desirable to seek a better way to remove thermal energy from large high power devices in operation by using interconnections as possible. Finally, in addition to meeting the needs described above, there is a need for interconnect systems with better mechanical strength in the required manufacturing steps and device operating temperatures.

[Summary of invention]

It is therefore a first object of the present invention to provide a semiconductor integrated circuit having a high performance, high speed interconnect system.

It is a second object of the present invention to provide an interconnect system for semiconductor integrated circuits that can be used to extract thermal energy from a device during operation.

It is a third object of the present invention to provide an interconnect system for a semiconductor integrated circuit that can be used to extract thermal energy from a device during operation.

It is a fourth object of the present invention to provide an interconnect system for a semiconductor integrated circuit that can be used to reduce unwanted electrical coupling between interconnect lines in close proximity to each other.

A fifth object of the present invention is to provide an interconnect system for a semiconductor integrated circuit in which the interconnect system forms a coaxial line.

A sixth object of the present invention is to provide an interconnect system for a semiconductor integrated circuit capable of optimizing impedance characteristics of the semiconductor integrated circuit.

It is a seventh object of the present invention to provide an interconnect system for semiconductor integrated circuits which exhibits better mechanical strength and hillock resistance.

It is an eighth object of the present invention to provide an interconnect system for a semiconductor integrated circuit which provides a common ground plate adjacent to all interconnect portions of the device.

These and other objects, as will be seen below, are achieved in accordance with the present invention by providing an interconnection system for integrated circuits using air as the dielectric between the passivation layers of the metal interconnects at various levels. In one preferred method of manufacturing such a system, a first dielectric layer comprising a first dielectric material is formed on a completed semiconductor structure, the completed semiconductor structure having a device formed within the semiconductor structure. Contact holes are etched in the first dielectric layer using a first etchant to expose device contact effects. The contact hole is defined as a conduit for electrically connecting the metal interconnect layer to the semiconductor material. The first metal layer is formed in the contact hole on the structure so as to be in contact with the device contact area. After such extension, the metal layer is patterned and then etched using a second etch that is substantially unreacted with the material of the underlying first dielectric layer to form a first level interconnect portion. A second dielectric layer comprising a second dielectric material is formed on the first level interconnection portion. After such extension, the upper surface of the second dielectric is made flat.

Via holes are opened in the second dielectric layer using a third etchant that reacts with the second dielectric material but does not substantially react with the underlying metal. The via hole is defined as a conduit for electrically connecting two interconnect levels. After such extension, a second metal level is formed in the via hole on the second dielectric layer, creating a direct electrical contact to the first interconnect level. The second metal layer is then patterned and then etched using a second etching solution to form a second interconnect level. Only at this point can the interconnect fabrication step be interrupted if a second interconnect level is necessary to complete the interconnect system. If a third or more interconnect level is required, a third dielectric layer is formed on the second interconnect level, the third dielectric layer being used for subsequent via hole formation, metal deposition and patterning. It is typically the same material used in the second dielectric layer. This manufacturing step is repeated to create several levels of interconnect structure with the required number of interconnect levels.

After the fabrication steps of the interconnect portions have been completed, this completed device structure is placed in a third etchant that reacts with the second dielectric material but does not react with the first dielectric material or metal used for the interconnect. As a result, all of the second dielectric material is removed from around the interconnects forming the multilevel interconnect structure, leaving the interconnected lines supported empty to the air gap between these interconnect lines.

If desired, an entirely separate interconnect structure including coaxial interconnect lines may be provided in a chemical vapor deposition system in which a dielectric is deposited around the supported line in an empty state without filling the gaps inherent between the interconnect lines. It is formed by leaving the structure. The manufacturing step can be stopped at this time, leaving a very small air gap between the lines built up by the thick dielectric. Such a structure greatly reduces the overall capacitance of the interconnect and, if necessary by design, increases the impedance characteristics of the interconnect. However, there may still be crosstalk between lines. Such crosstalk is preferably caused by a ground plate and heat sink around the totally separated interconnect structure by depositing a metal in the gap between the dielectric coated interconnect lines by chemical vapor deposition (CVD). Minimized by the structure of the present invention to form a continuous metal seal that acts as a.

In a variant embodiment of the invention, a first metal layer is formed in the contact hole formed on the structure and formed according to the above-described procedure, wherein the first metal layer is brought into contact with the device contact area exposed by the contact hole. . Then, the second metal layer is deposited on the first metal layer. At this time, the second metal layer is patterned and then etched using a second etching solution that has not substantially reacted with the underlying first metal layer to form a plurality of posts disposed at predetermined positions on the structure. Allow a first post array to be formed. After such extension, the first metal layer is patterned and then etched using a third etchant that does not substantially react with the second metal layer and the underlying first dielectric material so that the interconnection of the first level is formed. To form.

A thick second dielectric layer is formed on the posts, first level interconnects, and first dielectric layers that make up the first post array. The lower surface of the structure is planarized, for example, by forming a third dielectric layer on the second dielectric layer. The third and second dielectric layers are then etched back using a third etchant to expose the top of the post. Then, the third and fourth metal layers are deposited on the substantially flat top surface of the second dielectric layer to be in contact with the exposed post top. At this time, the third and fourth metal layers are formed in the second interconnect level and the second post array, respectively, according to the procedure described above. This procedure may be repeated to create multiple interconnect levels. Thus, the insulating layer between the interconnect lines is removed as described above. Then, the coaxial interconnect line can also be manufactured according to the procedure described above.

The present invention, in another embodiment, allows contact holes to be formed in the first dielectric layer as described above. After such opening, the contact hole can be selectively filled with the first metal using chemical vapor deposition, which makes the upper metal surface of the contact hole flat with the top of the first dielectric surface. This manufacturing step is referred to as plug contact technology, and optionally deposited material is referred to as plug. The plug makes contact with the device contact area exposed by the contact hole. A second metal layer is then formed on the first dielectric layer to make contact with the top surface of the plug. The second metal layer is then patterned and then etched using a second etchant that does not substantially react with the first metal layer forming the plug and the underlying dielectric to form a first level interconnection portion. To be. A second dielectric material is made to form on the interconnection portion of the first level. After such extension, the top surface of the interconnect is made flat.

The via is opened in the second dielectric layer using a third etchant that reacts with the second dielectric material but does not substantially react with the underlying second metal layer or the material of the first dielectric layer. The second plug array comprising a first metal layer selectively deposits the first metal layer into the via until the top surface of the deposited post is planarized to substantially the same height as the top surface of the second dielectric layer. To be formed in the via hole of the second dielectric layer. After such extension, a second metal layer is formed on the second dielectric layer to make contact with the post top surface of the second plugged via array. The second metal is then patterned and then etched using the second etch solution to form interconnections of a second level. This procedure can be repeated to create several levels of interconnect structure with the required number of interconnect levels. After that, the insulating layer between the interconnect lines is allowed to be removed as described above. Thus, the coaxial interconnect line can also be manufactured according to the procedure described above.

Alternatively, the interconnect level can be made using a first metal layer, which is the same metal layer used to form the post or plugged via array. In this case, the first metal layer is patterned into interconnects that form caps or nests on the underlying posts or plugs to prevent their etching. After that, the patterned first metal layer is etched using an etchant that does not substantially react with the underlying dielectric layer, thereby forming interconnect portions.

In another preferred variant, the interconnect can be formed into a sandwich structure comprising at least one titanium layer sandwiched between two layers of aluminum-silicon material. The first aluminum-silicon layer is formed on the underlying dielectric layer to make contact with the top surface of the underlying post array. The upper aluminum-silicon layer is preferably covered by a protective tungsten layer. This sandwich structure is then patterned and then etched using an etchant that has not substantially reacted with the underlying post metal and dielectric layers to form interconnects. When an etchant is used that reacts with the underlying post metal, a cap or nest is patterned into the interconnect portion to prevent etching of the underlying metal layer.

Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiments of the present invention, the appended claims and the drawings.

Detailed Description of the Preferred Embodiments of the Invention

Although specific forms of the invention have been chosen to be illustrated in the accompanying drawings and the following description is set forth in certain terms to describe such aspects of the invention, these descriptions are intended to limit the scope of the invention as defined by the appended claims. It is not intended to limit the scope.

Referring now to FIG. 1, in particular to FIG. 1 (a), there is shown in schematic cross-sectional form a completed semiconductor structure 10 comprising a silicon substrate on which devices such as transistors and diodes are formed. . Such a device is shown schematically and identified by reference numeral 12. The first dielectric layer 14 is formed on the completed semiconductor 10. In a preferred embodiment, dielectric layer 14 comprises silicon dioxide formed during a low pressure chemical vapor deposition process (LPCVD). The reaction mixture of HiH ₄ + PH ₃ + O ₂ is used to produce a glass thickness of 2000 kPa to 6000 kPa. An etch stop dielectric layer 16 unaffected by the first etchant (described later) is allowed to form on the first dielectric layer 14. In a preferred embodiment, the edge stop dielectric layer 16 comprises silicon nitride, which is substantially unaffected by the first etchant comprising dilute or buffered hydrogen fluoride (HF) solution. The edge stop dielectric layer 16 is preferably formed to a thickness of approximately 4000 kPa by low pressure chemical vapor deposition. This layer allows the first metal layer to adhere well to the substrate during wet etching of long exposures used to partially shield other metal levels in free space, as described later.

Referring now to FIG. 1 (b), the contact holes 18 are etched into the etch stop dielectric layer 16 and the first dielectric layer 14 such that there is a predetermined spatial relationship for the device service 12. The contact area is exposed to the area 12 lying in the. In a preferred embodiment, the hole 18 is etched using a plasma RIE process which is treated with a second etchant, preferably CHF ₃ and oxygen. In a preferred embodiment, the first electrically conductive adhesion layer 20 is formed on the substrate to be in contact with the device contact region and in the contact hole 18. The first adhesion layer 20 includes a thin (50-100 μs) titanium layer that is formed by physical vapor deposition (PVD) or sputtering and provides good contact and adhesion to the semiconductor structure 10. The use of such layers can be applied to high temperature interconnects such as tungsten and is not necessary for lower temperature structures, which will be described later. This layer is allowed to partially coalesce after high temperature treatment to ensure good adhesion to the dielectric. It should be noted that it is possible to remove the titanium adhesion layer when a process for good adhesion of tungsten is used. The first electrically conductive barrier layer 22 is formed on the first adhesion layer 20. The first barrier layer 22 preferably comprises tantalum nitride (TaN) formed by sputtering tantalum to a thickness of approximately 500 kPa, for example in a reaction environment of 70% Ar (g) + 30% N ₂ (g). In a preferred variant, the barrier layer 22 comprises zirconium boride (ZrB ₂ ) formed by the reaction deposition of Zr and B. In a preferred embodiment, the first metal layer 24 comprises tungsten formed to a thickness of approximately 0.75 microns by chemical vapor deposition (CVD).

The first metal layer 24 is patterned with a photoresist according to a predetermined first level interconnection pattern, and then SF ₆ is anisotropically etched using a plasma RIE process in which a third etchant is desired. d) stop at etch stop dielectric layer 16 as shown in FIG. The third etchant SF ₆ reacts with the adhesion, barrier, and materials of the first metal layers 20, 22, 24, respectively, but erodes the etch stop dielectric layer 16 more slowly. However, even if erosion may occur, the dielectric layer 16 is thick enough so that erosion is slow enough that the layer 16 will continue to flatten after overetching. At this time, all surfaces of the silicon dioxide material including the first dielectric layer 14 and the interconnect portion 26 of the first level are formed by the material of the edge stop layer dielectric 16 or the contact hole 18. To be.

After that, the structure of FIG. 1 (d) is covered with the first protective dielectric layer 28 as shown in FIG. 1 (e). In a preferred embodiment, the first protective dielectric layer 28 is a thin crystal layer sputtered to protect the underlying tungsten from oxidation during formation of the dielectric layer 30 overlying it, having a thickness of approximately 500 microns. The second dielectric layer 30 is formed of 1, such as germanophosphosilicate, formed on the protective dielectric layer 28 by depositing from a mixture of SiH ₄ + PH ₃ + GeH ₄ + O ₂ by atmospheric CVD. It is desirable to include a reflow glass film of micron thickness. After formed in that way, the glass is reflowed at 950 ° C. to form a substantially flat upper surface. Other glasses treated with low reflow temperatures may also be used, such as Borofoss posigate glass that reflows at 850 ° C. In processes where a high temperature reflow planarization step is unacceptable, a low temperature oxide and etch back planarization step may be used as a variant. Such modifications are deemed to be within the scope and spirit of the present invention as described herein and may be used whenever the method claimed herein requires the creation of a flat dielectric. Such a system gives stability to the silicon region of the contact region because the TaN barrier layer 22 inhibits silicon and dopant diffusion from this region.

As shown in FIG. 1 (f), the via 32 is opened in the planarized dielectric layer 30, preferably using photolithographic techniques to define an etch mask, and then with CHF ₃ and oxygen The opening portion is etched using the plasma RIE method to be treated. The via opening 32 is formed such that there is a spatial relationship to the underlying first-level interconnect 26, thereby exposing a predetermined contact area on the interconnect 26. Since the tungsten metallization treatment of the first level interconnect 26 does not form a stabilized oxide, it is necessary to dilute a solution of water: peroxide (H ₂ O: H ₂ O ₂ ) (e.g., before depositing the metal). Can be soaked in 100: 1). This substantially improves the reliability of the contact, since it is not a stabilized oxide that inhibits good electrical interconnection between metal layers.

As shown in FIG. 1 (g), deposits are made in the via opening 32 on the second dielectric layer 30 of the second adhesion layer 34 and are on the first level of interconnection level. Make contact with the contact area. In a preferred embodiment, the second adhesion layer 34 includes titanium, which is formed to a thickness of about 50 to about 100 mm by physical vapor deposition (PVD). Then, the second metal layer 36 is deposited on the second adhesion layer 34. The second metal layer 36 preferably includes tungsten formed to a thickness of about 7500 kPa by chemical vapor deposition (CVD). Again, it is preferable to include tungsten that adheres tungsten well. Again, it should be noted that when the process of attaching tungsten well is used, it is possible to remove the tungsten adhesion layer 34. The via opening 32 can be filled with metal using the method described later to fill the contacts.

After that, the second metal layer 36 and underlying second attachment layer 34 are patterned using photolithographic masking techniques and then etched using a plasma RIE method treated with SF ₆ . As shown in FIG. 1 (h), a second level interconnect 38 is formed. This structure is then covered with a second protective dielectric layer 40 and a third dielectric layer 42, as shown in FIG. 1 (i). Since the second protective dielectric layer 40 has a thickness of approximately 500 μs, the second protective dielectric layer 40 is a thin crystal layer sputtered to protect the underlying tungsten material from oxidation during deposition of the upper third dielectric layer 42. desirable. The third dielectric layer 42 is preferably a thick film having a reflow glass having a thickness of approximately 1.2 μm, such as germanophosphosilicate formed by CVD with an atmosphere of SiH ₄ + PH ₃ + GeH ₄ + O ₂ . . After such opening, the glass is reflowed at 950 ° C. to provide a substantially flat top surface. Other glasses treated with low reflow temperatures may be used, such as borophosphosigate glass that reflows at 850 ° C. In processes where high temperature reflow planarization is unacceptable, the low temperature oxide and etch back planarization described above may be used.

The second group of vias 44 then has a third dielectric layer 42 and a third in a predetermined spatial relationship with the underlying second level interconnect 38 as shown in FIG. 1 (j). 2 to be formed in the protective dielectric layer 40. In a preferred embodiment, the second group of via opening portions 44 are formed in accordance with the method described above for the first group of via opening portions 32. The second group of via openings 44 allows the contact area to be exposed at a predetermined position on the underlying second level interconnection 38.

As shown in FIG. 1 (k), a second level interconnection portion is formed in the second group of via opening portions 44 on the third dielectric layer 42 of the third attachment layer 46. Contact with the contact area exposed on (36). In a preferred embodiment, the third adhesion layer 46 comprises titanium having a thickness of about 50 to about 100 microns by physical vapor deposition (PVD) sputtering. Then, the third metal layer 48 is formed on the third adhesion layer 46. Preferably, the third metal layer is tungsten formed to a thickness of approximately 7500 kPa by chemical vapor deposition (CVD). As described above, it is possible to remove the titanium adhesion layer when a process for attaching tungsten that adheres well to tungsten is used. After such extension, the third attachment layer 46 and the third metal layer 48 are allowed to cause the second level interconnects 38 to be patterned and then etched using the process described previously for formation. As shown in FIG. 1 (l), a third level of interconnect 50 is formed. As such, the process of forming additional interconnect levels can be repeated as needed to create multiple levels of interconnect structure.

After the desired number of interconnect levels have been produced, the wafer is submerged in the first etchant to erode the insulating layer material between the interconnect levels. In the embodiment shown in FIG. 1 (l), the insulating layer material is layers 30 and 42. As described above, this first etchant is a solution containing hydrogen fluoride (HF) and is removed in Fig. 1 (m) by removing the sputtered SiO ₂ insulating material and germanophosphosilicate glass between all metal layers. The illustrated structure is made. Preferred etchant consists of a mixture of 3: 3: 2 parts ammonium fluoride: acetic acid: water.

In forming the coaxial interconnect lines, an insulating layer 52 is formed around the vacated support interconnect lines of the structure shown in FIG. 1 (m) without filling the gaps present between the coaxial interconnect lines. . The insulating layer 52 is considerably thick as necessary to ensure that gaps are retained between interconnect levels. In a preferred embodiment, the insulating layer 52 comprises silicon dioxide deposited to a thickness of 3000 kPa using a chemical vapor deposition (CVD) system. After the insulating layer 52 is formed, an electrically conductive material layer 54 such as tungsten is formed on the insulating layer 52. This conductive material layer 54 is formed by depositing tungsten by CVD method around the gap on the insulating layer 52 such that a continuous metal inclusion is formed around the totally separated interconnect structure. It is preferable. There may be gaps between portions of the conductive material layer 54 surrounding adjacent interconnects, but all such gaps are filled with metal to improve the mechanical strength of the structure. 2 shows the completed structure described above.

This metal layer 54 acts as a ground plane around all interconnect lines, in which case it greatly reduces cross-talk of the interconnect lines by sinking field lines from adjacent interconnect lines. . The metal layer 54 can also function as a heat sink. At this time, the contact pads are removed from the metal and dielectric to allow the wafer to die. One connection to the metal layer 54 provides a ground portion close to all interconnections of the semiconductor structure. Another physical connection portion to the top surface of the device can be used to dissipate heat upward in the chip through the interconnect layer.

In a preferred variant of the invention, the contact hole 18 is associated with the first (a) and the first (b) views, as described above, on the contact area of the device 12 of the semiconductor structure 10. In the first etch stop dielectric layer 16 and the first dielectric layer 14 at. After forming the contact hole 18, the first electrically conductive layer 102 comprising the first metal layer is formed in the contact hole 18 on the structure as shown in FIG. 3 (a). . In a preferred embodiment, the first electrically conductive layer 102 is formed to a thickness of approximately 4500 kPa by physical sputtering. Thereafter, a second electrically conductive layer 104 comprising a second metal layer is formed on the first electrically conductive layer 102. In a preferred embodiment, the electrically conductive layer 104 comprises tungsten formed to a thickness of approximately 7500 kPa by physical vapor deposition (PVD) or sputtering.

Referring now to FIG. 3 (b), the second electrically conductive layer 104 may be formed using a first photoresist technique and an etchant that reacts with the second metal layer but does not substantially react with the first metal layer. Patterned into an array of posts 106. The post 106 is a metal feature that substantially protrudes over the electrically conductive layer 102 and provides electrical connections for the next metal level. The etching process used in the preferred embodiment is a plasma RIE method which is treated with SF ₆ . Thus, the first post 106 array is formed on the first electrically conductive layer 102 by an etch stop process. After that, the first electrically conductive layer 102 uses an etching solution that reacts with conventional photoresist techniques and the first metal layer but does not substantially react with the second metal layer and the first etch stop dielectric layer 16. Patterned into the first-level interconnect 108. Thus, the first level interconnect 108 prevents the etchant from stopping at the first etch stop dielectric layer 16 and etching the first metal region underlying the post 16 of the first post array. To act as a mask. As a result, the post 106 is directed to the underlying first level interconnect 108 as shown in the underlying first level interconnect as shown in FIG. 3 (c). Make it self align.

Referring to FIG. 3D, a thick second dielectric layer 110 is formed on the post 106 and the first level interconnect 108, as well as the first etch stop dielectric layer 16. In a preferred embodiment, the second dielectric layer 110 comprises an oxide of low temperature treatment deposited to a thickness of approximately 2 microns using low pressure chemical vapor deposition (LPCVD) of SiH ₄ , PH ₃ and oxygen. As shown in FIG. 3 (e), the planarizing dielectric layer 112 is preferably an organic resin that is a photoresist that is made on the second dielectric layer 110 to form a substantially flat upper surface 114. . The planarizing dielectric layer 112 and the second dielectric layer 110 are then whitened using a plasma RIE method, preferably treated with CHF ₃ + O ₂ , so that the top of the post 106 is exposed. As shown in FIG. 3 (f), a substantially flat upper surface is maintained. The structure then removes the exposed top surface of the original oxide posts 106 which may be immersed in a dilute solution of hydrogen peroxide: water (1:20) that may degrade the electrical contact to the posts 106.

As shown in FIG. 3 (g), a third electrically conductive layer 116 comprising a first metal, which is aluminum in a preferred embodiment, is formed on the planarized top surface of the second insulating layer 110. In contact with the exposed top of the post 106. After that, a fourth electrically conductive layer 118 comprising a second metal, which is tungsten in a preferred embodiment, is allowed to form on the third electrically conductive layer 116. The third and fourth electrically conductive layers are allowed to be formed in accordance with the procedure described above for forming the first electrically conductive layer 102 and the second electrically conductive layer 104. After that, the third electrically conductive layer 116 and the fourth electrically conductive layer 118 are described above for forming the first level interconnect 108 and the first post 106 array. According to the described procedure, it is formed into a second level interconnection part and a second via post array, respectively.

The third insulating layer is then formed on the second level of interconnects and the second post array in accordance with the procedure described above in connection with FIGS. 3 (d) to 3 (f) and then planarized. To be etched back to expose the post top in the second spot array. This manufacturing step may be repeated until the desired number of interconnect levels has been formed. Next, the insulating material between the interconnect lines is removed in accordance with the procedure described above in association with the first (m) degree. After such opening, the contact hole 18 is first etch stop on the contact area of the device 12 of the semiconductor structure 10 as described above in connection with the first (a) and the first (b) degrees. It is formed in the dielectric layer 16 and the first dielectric layer 14. After forming the contact hole 18, a plug 202 comprising tungsten-preferred first metal is allowed to form in the contact hole 18 as shown in FIG. 4 (a). The plug 202 is preferably formed by selectively depositing a first metal into the contact hole 18 using chemical vapor deposition (CVD). In a preferred embodiment, tungsten is used as the first metal and allowed to deposit in a closed wall reactor. The substrate temperature of the wafer is maintained between 300 and 600 ° C., while the tungsten is selectively deposited by using a WF ₆ : H ₂ ratio of approximately 1: 100. The deposition process continues until the top surface of the deposited post 202 is planarized to substantially the same height as the top surface of the first etch stop dielectric layer 16 as shown in FIG. 4 (a). can do. The first metal layer 204 is then formed on the first etch stop dielectric layer 16 to be in contact with the top surface of the post 202. The first metal layer 204 will be described later, but preferably comprises a tungsten or aluminum-silicon-titanium sandwich alloy structure.

The first metal layer 204 is a first-level interconnect portion 205 (fourth) using conventional photoresist technology and etching solution that does not substantially react with the material of the underlying first etch stop dielectric layer 16. (see also c)). As shown in FIG. 4 (d), the first protective layer 206 includes the first etch stop dielectric layer as well as the first level interconnect 205 as described above in connection with the first (e). 16) to form. The planarized dielectric material layer 207 also allows it to be formed on the first protective layer as described above with respect to FIG. 1 (e). However, since the aluminum alloy is used in this preferred embodiment of the present invention, the above-described low temperature oxide and etch back planarization strain should be used to planarize. The second group of vias 208 are preferably opened in the planarized dielectric layer 207 and underlying protective layer 206 according to the procedure described above with respect to FIG. 1 (f). The second post 210 array comprising the first metal is allowed to form in the via 208 according to the procedure described above with respect to FIG. 4 (a).

The second metal layer is then formed on the second dielectric layer 207 to be in contact with the top surface of the post 210 of the second post array. After such extension, the second metal layer is patterned and then etched to form second level interconnects using a second etchant. This procedure can be repeated to create multiple levels of interconnect structure with the number of interconnect levels required. The insulating layer between the interconnect lines is then allowed to be removed as described above for the first (m) diagram. Thus, the coaxial interconnect lines can be formed according to the procedure described above with respect to FIG.

In applying lower temperatures where the treatment process and the actual treatment temperature does not exceed 500 ° C., the interconnects described above can be replaced with aluminum-silicon / titanium sandwich structures. Since aluminum is used in the sandwich structure, the above-described low temperature oxide and etch back planarization variants should be used to achieve the necessary planarization steps according to this preferred variant of the present invention. The sandwich structure comprises a first layer of aluminum-silicon material in which 1 to 1.5% silicon by weight is preferred. Preferably, the first aluminum-silicon layer is approximately 2500 kPa thick. The first titanium layer is preferably formed on the first aluminum-silicon layer in a thickness ranging from approximately 50 kPa to 200 kPa. At least a second aluminum-silicon layer is preferably formed on the first titanium layer to a thickness of approximately 2500 kPa.

Although the sandwich structure comprises at least a first titanium layer sandwiched between at least the first and second aluminum-silicon layers, in a preferred embodiment the second titanium layer preferably spans a range of approximately 50 kPa to 200 kPa. To form on the second aluminum-silicon layer. In addition, a third aluminum-silicon layer is preferably formed on the second titanium layer to a thickness of approximately 2500 kPa. Preferably from 1 to 1.5% silicon per composition weight of the second and third aluminum-silicon layers. Finally, the protective layer preferably comprising tungsten is preferably formed on the third aluminum-silicon layer to a thickness of approximately 100 mm 3. This sandwich structure is then patterned and then etched to form the necessary interconnects using methods available to one of ordinary skill in the art.

The use of the sandwich structure described above substantially reduces the problem of electrical short circuits between interconnections caused by interconnect deformations such as heel locking, because the silicon of the aluminum-silicon material is ternary ( This is because it moves to the titanium interface to form a phase. Because of the good mechanical strength properties on standard aluminum alloys containing pure aluminum or Cu, this sandwich structure can use aluminum as the base material for the interconnects. This is desirable due to the fact that such resistance is substantially lower than the resistance of other materials that do not exhibit heeling, such as tungsten. Furthermore, due to the relatively low electrical resistance properties, aluminum can be seen to have a lesser effect on the switching level of the device compared to other high strength materials such as tungsten. Since aluminum is the sandwich material, in particular the base material of the top layer, the protective aluminum layer preferably prevents the formation of the native oxide on the top surface of the aluminum-silicon layer. When such native oxides are present, coarse electrical contacts are formed between any plug and interconnect formed on the sandwich interconnect.

As can be seen from the description of the preferred variant embodiment of the present invention, the interconnects and insulating materials of conventional semiconductor structures have been replaced by coaxial conductor systems. For greater structural strength, the metal forming the coaxial sheath may be thick enough to completely fill the gaps between the interconnect lines. Compared with the prior structure, which uses silicon dioxide only as the line-to-line insulation material, there is a distinct electrical advantage in that when forming coaxial interconnections with ground plates, all lines have almost the same impedance characteristics per unit length. . This is due to the development of means to wrap the shielding material closely around each individual wire. Likewise, although not critical, the formation of a coaxial interconnect with a ground plate can be used to electrically shield the local interconnect from crosstalk and to remove thermal energy from the chip.

Various changes in details, materials, and arrangements of components that have been described and exemplified for describing the characteristics of the present invention are common knowledge in the art without departing from the spirit and scope of the invention as described in the appended claims. It should be understood that this can be done by anyone with.

Claims (9)

A semiconductor integrated circuit comprising an interconnect structure for electrically connecting a region inherent to a semiconductor substrate, wherein the interconnect structure is formed from another interconnect portion except for an interconnect portion where each interconnect portion is at an electrical contact. A plurality of interconnecting portions that are structurally separate, each of the plurality of interconnecting portions being substantially enclosed in each dielectric layer disposed around the interconnecting portions other than the interconnecting portions at the electrical contacts. Each of said dielectric layers has an outer surface enclosed, the outer surface of each dielectric layer of each of said interconnecting portions being otherwise interconnected by an air gap except for the interconnecting portions at said electrical contacts. Water in all directions from each dielectric layer of the connection part The semiconductor integrated circuit device, which is ever separated. The semiconductor integrated circuit device of claim 1, further comprising a layer of electrically conductive material disposed around each layer of dielectric material. 3. The semiconductor integrated circuit device of claim 2, wherein any gaps between adjacently surrounding dielectric materials are substantially filled with the electrically conductive material. 4. The semiconductor integrated circuit device of claim 3, wherein the enclosing dielectric material comprises silicon dioxide. The semiconductor integrated circuit device of claim 4, wherein each layer of electrically conductive material comprises tungsten. The semiconductor integrated circuit device of claim 1, comprising a titanium layer disposed between two layers of aluminum-silicon material of each of the interconnect portions. The method of claim 1, wherein the interconnect portion comprises: (a) a first titanium layer disposed between the first aluminum-silicon material layer and the second aluminum-silicon material layer, and (b) the second aluminum- A second titanium layer formed between the silicon material layer and the third aluminum-silicon mixture layer, and (c) a protective layer disposed on the third aluminum-silicon material. 8. The semiconductor integrated circuit device of claim 7, wherein the protective layer comprises tungsten. The semiconductor integrated circuit device of claim 8, wherein the aluminum-silicon material comprises 1 to 1.5% silicon by weight.