KR100190021B1 - Non-volatile memory cell array - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, comprising: a plurality of word lines extending in an active region extending in a first direction and extending in a second direction perpendicular to the first direction, each of which is disposed at a constant interval and arranged in parallel In the nonvolatile memory cell array comprising a line width of a specific word line of the plurality of word lines is different from the line width of the remaining word lines.

Description

Nonvolatile Memory Cell Array

1 shows a layout of a conventional NAND type flash memory cell array.

FIG. 2 shows threshold voltage distributions of the cells of FIG.

3 is a cross-sectional view of Z-Z of FIG.

4 is a layout of a NAND type flash memory cell array according to the present invention.

5 shows the threshold voltage distribution of the cell of FIG.

The present invention relates to a nonvolatile memory, and more particularly to a nonvolatile memory having a word line having a uniform line width.

When a memory device for storing information in a data processing system is classified from the viewpoint of storage and retention, it can be divided into a volatile memory and a nonvolatile memory. In the volatile memory, the memory contents are destroyed when the power supply is interrupted, whereas in the volatile memory, the memory contents are maintained without being destroyed even when the power supply is interrupted.

The nonvolatile memory may be classified into a read only memory (ROM), a programmable ROM (PROM), an erasing PROM (EPROM), and an electrically EPROM (EEPROM). Currently, there is an increasing demand for EEPROMs that can program and erase data using electrical methods. The memory with batch erasing function in EEPROM is called flash memory.

EEPROM is a NOR type in which each cell transistor is connected in parallel between a bit line and a ground line, and n cell transistors are connected in series to form a unit string. The unit strings can be divided into NAND type in which the unit strings are connected in parallel between the bit line and the ground line. The NAND type is advantageous for high integration of a large capacity memory cell. The basic NAND cell structure is described in detail in the 1988 Symposium on VLSI Technology paper (pp. 33-34).

The information of the NAND-type flash EEPROM is defined according to the state of the memory cell (erse and program states), and the state of this memory cell is determined by the threshold voltage of the cell transistor. That is, by changing the amount of charge stored in the floating gate of the memory cell transistor so that the threshold voltage of the cell transistor is changed, the state 1 or 0 is displayed. Normally, the threshold voltage of the cell transistor is lowered to the erase state (0 state), and the threshold voltage of the cell transistor is higher to be called the program state (1 state).

1 is a layout diagram of an EEPROM cell according to the prior art.

Reference numeral 10 denotes an active region, 20 denotes a field region, 30 denotes a tunneling area, 70 denotes a bit line contact, reference numerals WL1, WL2, ... WLn denote wordlines, and SSL denotes a string selection transistor. GSL denotes a ground select transistor, CS denotes a source region, a denotes a string select transistor, a plurality of word lines, and a line width of each of the ground select transistors, and b denotes a string select transistor or a ground select transistor with an adjacent word line. The interval c represents the interval between the word line and the word line, A represents the line width of each word line, and a and A are designed to be the same size.

The active region 10 is arranged in the column direction, and the field region 20 in the column direction is disposed between the active regions 10. Each active region 10 is connected to a bit line (not shown) formed in a column direction above the active region 10 through a bit line contact 70. The plurality of word lines WL1, WL2,... WLn are orthogonal to the bit lines and extend in the row direction. N cell transistors are formed at left and right sides of one bit line contact, and each cell transistor is connected in series while sharing a source region and a drain region with an adjacent transistor. N transistors on one side and two selection transistors connected to both ends thereof and extending in a row direction form one string. Thus, two strings are formed around one bit line contact. Among the selection transistors, the selection transistors adjacent to the bit line contacts are called string selection transistors SSL, and the selection transistors adjacent to the source region 60 are called ground selection transistors GSL.

FIG. 2 is a graph showing the distribution of threshold voltages of the cells of FIG. The X axis represents the threshold voltage value, the Y axis represents the number of bits in angstrom units, Vte represents an ideal erase threshold voltage, and Vtp represents an ideal program threshold voltage.

The threshold voltage represents a Gaussian distribution. In the erasing process, the Gaussian distribution does not represent an ideal Gaussian distribution, but forms a tail. In the program, as in the erasing process, the gaussian distribution has a tail. Therefore, the window E, which is the interval between the erasing operation and the program operation, becomes narrow, which increases the possibility that the cell transistor malfunctions.

The number of bits corresponding to 0.01 to 0.001% of all cell transistors corresponds to the tail portion D of the Gaussian distribution.

3 is a cross-sectional view of Z-Z of FIG.

A tunneling oxide film 300 is formed on a portion of the upper surface of the substrate 100 where a cell transistor is to be formed, and a thick oxide film 310 is formed on the portion where the string select transistor SSL is to be formed to have a breakdown voltage resistance against a high electric field. It is. A floating gate electrode has a first electrode 400 formed on the tunneling oxide film 300 and the thick oxide film 310, and a dielectric layer 350 and a second electrode 500, which is a control gate electrode, are formed on the first electrode. It is formed sequentially.

However, in the layout diagram, all word lines have the same line width, but in the implemented nonvolatile EEPROM flash memory cell, the first word line WL1 adjacent to the string select transistor SSL or the ground select transistor GSL, or The line width of the nth word line WLn is different from the line width of each of the word lines between the first word line and the nth word line. A thin tunneling oxide film 300 having a uniform thickness is formed at a portion where the cell transistor is formed. However, as shown in reference numerals 30 and 3 of FIG. 1, the thin film for tunneling is formed between the selected transistor and the cell transistor. Since both the oxide film and the thick oxide film having the withstand voltage resistance to high voltage are formed, the distance (B) between the first word line and the string selection transistor or the nth word line and the ground selection transistor is equal to the first word line. It is required to be larger than the adjacent interval c between the nth word lines.

Therefore, when the photolithography process is performed after forming the oxide layer, the first electrode, the dielectric layer, and the second electrode for forming the cell transistor and the selective transistor, the etching is performed at b rather than c because the step of b portion and b are larger than c. This happens vigorously. As a result, the line width of the word line adjacent to the selection transistor is smaller than the line width of the remaining word lines.

However, since the threshold voltage is determined by the amount of charge injected into the first electrode layer, which is the floating gate electrode, and the size of the cell transistor is determined when the word line is formed, the erase and program operations of the cell transistors formed on the first word line are prevented. Terminating faster than other cells. That is, the threshold voltages of the cells of the first word line adjacent to the string select transistor and the cells of the nth word line adjacent to the ground select transistor form part D of FIG. 2, thereby misleading the nonvolatile EEPROM flush memory cell. The possibilities are great.

Accordingly, an object of the present invention is to provide a layout of a nonvolatile memory cell array capable of solving the above-described problem.

In order to achieve the object of the present invention, there is provided an active region extending in a first direction, a plurality of word lines extending in a second direction perpendicular to the first direction, each of which is arranged in parallel at a constant interval In the nonvolatile memory cell array, the line width of a specific word line among the plurality of word lines is designed to be different from the line width of the remaining word lines.

The specific word line is adjacent to the selection transistor, and the distance between the specific word line and the selection transistor is greater than between the remaining word lines.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

4 shows a layout of a NAND type EEPROM flash memory cell array according to the present invention.

Like reference numerals in FIG. 1 denote like parts. The line width A 'of the first word line WL1 or the nth word line WLn adjacent to the string select transistor SSL or the ground select transistor GSL is each word between the first word line and the nth word line. It is designed wider than line width a. The size of the line width A of the first word line or the nth word line on the layout is adjusted so that the line widths of all word lines become constant after the photolithography process in consideration of the effect of the etching process of the cell transistor. Therefore, since the size of the gate electrode of the finally formed cell transistor is constant, the amount of tunneling electrons in the cell transistor is constant, so that the operation of all cell transistors is uniform.

FIG. 5 shows a distribution chart of threshold voltages of cells in the nonvolatile EEPROM flash memory formed by the layout of FIG.

Similarly to FIG. 2, the X-axis represents the threshold voltage value and the Y-axis represents the number of bits in angstrom units. It can be seen that the tail portion is not formed in the Gaussian distribution of the threshold voltages of the erase process and the program process. Thus, the window E 'for erasing the memory or distinguishing the program is significantly increased compared to the conventional one. Therefore, the erase state and the program state can be more clearly distinguished, and the cell transistor can be prevented from malfunctioning.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (3)

A nonvolatile memory cell array comprising a plurality of word lines arranged in parallel with a constant spacing, the active region extending in a first direction, and extending in a second direction perpendicular to the first direction. And a line width of a specific word line of the plurality of word lines is different from that of the remaining word lines. The nonvolatile memory cell array of claim 1, further comprising a selection transistor adjacent to the specific word line. 3. The nonvolatile memory cell array of claim 2, wherein a distance between the specific word line and the selection transistor is greater than between the remaining word lines.