KR0157436B1 - Adaptive selection circuit of hdtv signals - Google Patents

Abstract

A data compression system of a digital signal processing system. An adaptive selection circuit of a high-definition TV signal for compressing a data divided by a frequency component by an energy distribution by a filtering or transformation into an energy distribution while compressing the data into a transmission target amount has an adaptive variable. Limit value calculation means is provided.

Description

Adaptive Selection Circuit of High Definition TV Signal

1 is an overall block diagram of the present invention.

2 is a view showing an embodiment of the input buffer circuit 10 in the first diagram.

3 is a view showing an embodiment of the absolute match calculation circuit 20 in FIG.

4 shows an embodiment of the comparison circuit 30 in FIG.

5 shows an embodiment of the limit calculation circuit 40 in FIG.

FIG. 6 shows an embodiment of the selection circuit 50 in FIG.

FIG. 7 shows an embodiment of the output buffer circuit 60 in FIG.

8 shows an embodiment of the restoration circuit 70 in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data compression in a digital signal processing system. In particular, when a high-definition television signal is transmitted in a limited frequency band, the threshold is adaptively changed to filter or transform. The present invention relates to an adaptive selection circuit of a high-definition TV signal that can be compressed while selecting data divided by frequency components by energy distribution.

In general, when any signal is transmitted in a limited frequency band within the same time, compression of the data amount is necessary when the amount of data for a signal to be transmitted requires a frequency band wider than the limited frequency band.

Several prior arts have been developed to compress the above data amounts. One of these technologies uses a quadrature mirror filter (QMF) or discrete cosine transform (DCT) to transmit an A-TV (Advanced TV) signal to an existing National Television system committee (NTSC) channel. There is a method of dividing each component and then selecting relatively high energy components by the amount of data that can be transmitted, and various coding techniques are disclosed for compressing the amount of data.

Here, the method of selecting the data includes bit allocation or zone sampling, and these methods fix the selected frequency components and limit the data values selected. Although the amount can be adjusted, there was a problem that the energy distribution could not be accurately selected.

Therefore, when the data signal is restored after the data transmission, a reproduction signal that is different from the original video signal is restored, resulting in a deterioration of image quality.

Therefore, an object of the present invention is to adaptively change the threshold value in consideration of the above problems, adaptive selection circuit of a high-definition TV signal that can be compressed while selecting the data divided for each frequency component by the energy distribution by filtering or conversion In providing.

The present invention for achieving the above object is an input buffer means for adaptively selecting data continuously input by a selection signal of a predetermined period, and the absolute value for each block is input by inputting the data selected by the input buffer means. An absolute value calculation means for calculating, a comparison means for comparing an absolute value for each block of the absolute value calculation means with a preset limit difference, and a threshold value for varying the threshold value step by step by inputting a comparison output of the comparison means; And means for selecting data for each block in accordance with a selection signal of said comparing means, and an output buffer means for transmitting and outputting the selected data of said selection means by a transmission target amount.

In order to explain the operation of the present invention, a high-definition TV signal is used as an input signal, and the data amount is set as follows for convenience (the color signal is not included in the present invention because it is not wide for each frequency band).

Horizontal axis-1600 samples / line

Vertical axis-800 lines / frame

Time base-60 frames / sec, 1: 1 (sequential scan)

If the input data amount = 1600 × 800 × 60 = 76,800,000 samples / sec (38.4 MHz) and the transmittable data amount (hereinafter referred to as the transmission target amount) are also set to 9,600,000 samples / sec (4.8 MHz) for convenience, the data compression rate is Same as

Data Compression Ratio = 100 × 9,600,000 / 76,800,000 = 12.5%

The data obtained by filtering or converting the aforementioned input signal into 8 bands on the horizontal axis, 8 bands on the vertical axis, and 4 bands on the time axis is set as the input data of the present invention for convenience. The input data processed in this way is composed of 256 (= 8x8x4) subbands for an input signal of four frames (15 ms). The size of each subband is as follows.

Horizontal axis-200 samples / line ← 1600 ÷ 8

Vertical axis-100 lines / frame ← 800 ÷ 8

Time base-15 frames / sec ← 60 ÷ 4

Since 256 subbands are continuously input every four frames (15 ms), the input data is limited to 256 sub bands (15 ms) for convenience, and is regarded as three-dimensional data of the X, Y, and Z axes as follows. X-axis 200, Y-axis 100, Z-axis 256 256 Therefore, the input data amount and the transferable data amount based on only 4 frames (15 ms) are calculated as follows.

Input data amount = 5,120,000 ← 200 × 100 × 256

Transmission target amount = 640,000 ← 200 × 100 × 32

In the end, the goal is to select data corresponding to an average of 32 subbands out of 256 subbands in order of increasing energy. On the other hand, a selection signal indicating whether each sample is selected is required, and this selection signal is used when selecting and restoring data. However, when the selection is made in units of samples, the amount of the selection signal is the same as the amount of input data, so the data compression effect is lost. In the present invention, the selection signal is selected in units of blocks to reduce the amount of the selection signal, and the size of the block is set to 20 (X axis) × 10 (Y axis) for convenience. The input data amount and the transmission target amount are shown in block units as follows (since it is simple to handle the data amount in block units, so the data amount is handled in the future).

Input data amount = 51,200 ← 20 (X axis) × 10 (Y axis) × 256 (Z axis)

Transmission target amount = 6,400 ← 20 (X axis) × 10 (Y axis) × 32 (Z axis)

Since one selection signal is generated for each block, the selection signal amount is 51,200 samples, and the selection signal has a value of 1 or 0 by comparing the absolute sum of the block and the threshold, and the sum is greater than or equal to the threshold. If it is equal, it is 1; If the selection signal is 1, the block is selected and transmitted. If 0, the block is not selected. The threshold is then set by the following procedure.

First, the selection sequence proceeds in the order of Z-axis, X-axis, and Y-axis.

The second is to select 256 blocks on the Z-axis of dust, repeat it 20 times on the X-axis, then modify the limits before proceeding to the Y-axis. The initial value of the limit is 100 (limit value 100 means an average pixel value of 1).

Next Step Limit = Limit + Proportional Factor × Error / Step Target

Error = quantity selected in previous stage-target quantity

Here, the step means a step in the Y-axis direction and is divided into 10 steps. The proportional coefficient can be set from 1 to any large number (approximately 20) .The larger the proportional coefficient is, the more data can be selected closer to the transmission target, but the larger the variation in the threshold is, the more difficult it is to select the energy distribution. Lose. In the present invention, the proportional coefficient is set to 8 (the hardware design is simple since the error only needs to be 3-bit shift lift without multiplying 8) and the minimum value of the threshold is set to 50 to reduce the variation of the threshold. .

Third, the step target quantity is calculated as follows.

Step target amount = target transfer amount-the number of steps selected / up to the previous step

The initial value of the step target is 6400 ÷ 10 = 640.

Fourthly, if the selection is completed on the Y-axis, the same process is continued for the next input data.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIGS. 1A and 1B show the entire selection part on the transmitting side and the restoration part on the receiving side in blocks. As follows.

The input buffer circuit 10 adaptively selects and outputs data continuously input by a selection signal of a predetermined period. The absolute value calculating means 20 inputs the data selected by the input buffer circuit 10 to calculate the absolute value sum for each block. The comparison means 30 compares the absolute value sum for each block of the absolute value calculation circuit 20 with a preset limit value. The threshold calculation circuit 40 inputs the comparison output of the comparison means 30 to vary the threshold step by step. The selection circuit 50 selects the data for each block output from the input buffer circuit 10 according to the selection signal of the comparison means 30. The output buffer circuit 60 transmits and outputs the selected data of the selection means by the transmission target amount.

2 to 7 are detailed views of the components of FIG. 1 and will be described in detail with reference to the drawings.

FIG. 2 is a detailed circuit of the input buffer circuit 10 of FIG. 1, which is composed of two four-frame memories 11 and 12. The memory 2 (12) is written while the input data is written to the memory 1 (11). When the input data already stored in the memory is read and adaptively selected, and writing of the memory 1 11 is completed, the writing of the memory 2 12 is started and the memory 1 11 is read at the same time. With this configuration, it is possible to make adaptive selection in three dimensions and to continuously process data that is continuously input. 3 shows the absolute value calculation circuit 20, which is composed of a MUX 1 (21), a comparator 22, an adder 1 (23), and a register 1 (24). The MUX 1 (21) and the comparator 1 (22) function to change the input data to an absolute value, and this absolute value is input to the adder 1 (23), and the output of the adder 1 (23) is further added to the adder 1 (23). Feeded back to another input, the absolute values continue to accumulate and register 1 (24) is cleared every 100 samples, thereby preventing the output of adder 1 (23) from adding the absolute value of the same sample between different blocks. 4 is a comparison circuit 30 that compares the absolute value of the absolute block value with the threshold value so that the selection signal becomes 1 when the absolute block absolute value is greater than or equal to the threshold value. When the clock input of register 2 (31) occurs every 100 sample periods, the comparison circuit 30 adds the absolute value sum to the register 2 (when the output of adder 1 (23) in FIG. 31). Register 3 (32) loads a variable limit value every time it advances to the Y axis (every 100 samples × Z axis 256 × X axis 20 = 512,000 samples). The selection signal generated by the comparison circuit 30 is input to the counter 40a of FIG. 5, which is the threshold calculation circuit 40, and increments the counter by one each time the selection signal is one. The counter 40a is cleared at the start of each Y-axis step, thereby outputting the data amount selected in each Y-axis step. Register 5 (40b) loads the counter output, i.e., the amount of data selected in stages, immediately before the counter (40a) is cleared. Adder 2 (40h) is also a feedback input using register 4 (40c), like adder 1 (23) of FIG. 3, to accumulate the data amounts selected in stages. The adder 3 (40 i) serves as a subtractor for subtracting one selected cumulative data amount from a transmission target amount of 6,400 blocks (= 640,000 samples). The output of this adder 3 40i is the remaining amount of data that can be selected in the future. The down counter 40k is first loaded with the number of Y-axis steps 10, and then decremented by one expression each time one step proceeds to the Y-axis step, thereby outputting the remaining number of steps on the Y-axis. By dividing the output of the adder 3 40i, that is, the selectable remaining data amount by the down counter output, that is, the number of remaining steps, the next step target amount can be obtained. However, in order to obtain the error, the current target amount before the change is required, so a first-in-first-out (FIFO) memory (40m) that provides a one-step delay function is used. In this way, the error between the data amount (the register of the register) and the current step target amount (FIFO output) selected in the current step can be obtained by subtracting the adder 4 (40o). This error is then multiplied by the proportional factor 8 and divided by the current target amount to become the threshold change amount. The proportional coefficient 8 means that if the error exceeds 12.5% of the step target amount, the threshold is increased by 1, and if it is not reached, the value is decreased by 1, and in practice, the error is simply 3 bits without the need for a multiplier to multiply 8. Just shift left.

As a proportional coefficient, in addition to 8, 2, 4, and 16, which are multiples of 2, can be used, and simulation shows that 8 can be used without any problem. Register 9 (40g) was used to set the initial limit to 100. Adder 5 (40j) adds the threshold change amount obtained above to the current threshold value each time the stage is progressed, thereby changing the threshold value. MUX 2 (40s) and Comparator 2 (40R) prevented the threshold from decreasing below 50. The reason for doing this is to prevent the threshold from being unnecessarily lowered since the threshold of 50 or less means an average value of 0.5 of 100 samples in the block. The selection circuit of FIG. 6 loads two blocks of 100 samples from shift register 1 61 to shift register 2 62 whenever the selection signal generated by the FIG. 5 comparison circuit is one.

In this manner, data is selected for each block and output to the output buffer circuit 60 of FIG. The output buffer circuit 60 is composed of two half frame memories 71 and 72, as shown in FIG. 7. The operation is the same as the input buffer circuit 10 of FIG. The output buffer circuit 60 stores the randomly selected data in the memory once and then continuously transmits the data after four frame periods. Here, 1/2 frame is equal to 640,000 samples. During transmission, the clock reading data is lowered to one eighth of the original sample clock to match the read / write time with the input buffer circuit. Therefore, it is very simple to restore the selected and transmitted data to the original position at the receiving side.

8 is a recovery circuit. The four memories are the same as those on the transmission side, and only MUX3 (85) and register 11 (84) are added to read data from the half frame memory every time the selection signal is 1, and 4 Send to frame memory, and 0 if the selection signal is zero. In this way, the original position of the data is restored.

As described above, the present invention has the advantage of adaptively varying the threshold value when transmitting a high-definition TV signal in a limited frequency band, thereby compressing while selecting data according to an energy distribution, thereby improving the image quality upon reception. .

Claims (2)

An input buffer means for adaptively selecting data continuously input by a selection signal of a predetermined period in a selection circuit adaptive to high definition TV signals for compressing image data when transmitting a high definition TV signal in a limited frequency band. And absolute value calculation means for calculating the absolute value sum for each block by inputting the data selected by the input buffer means, comparison means for comparing the absolute value sum for each block of the absolute value calculation means with a preset limit value; A threshold calculation means for inputting the comparison output of the comparison means to vary the threshold step by step, selection means for selecting the data for each block according to the selection signal of the comparison means, and transmission data of the selected means. As an output buffer means for transmitting and outputting as much as Adaptive selection circuit of a high-definition TV signal. The high-definition television set as claimed in claim 1, wherein the threshold value calculation means adds the previous threshold value change amount as the step progresses so that the data divided by the frequency components can be selected and compressed according to the energy distribution. Adaptive selection circuit of the signal.

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