KR0149617B1 - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device, comprising: a plurality of memory cells and control circuits for carrying out self-regeneration at a period shorter than the information holding time of a memory cell and sufficiently achieving low power consumption in the self-regeneration mode, wherein the device has a first magnetic field. In the regeneration mode, the control circuit executes a regeneration operation for each of the plurality of memory cells every first regeneration period, and when the device is in the second magnetic regeneration mode, the control circuit has a period longer than the first regeneration period for the plurality of memory cells. A regeneration operation is executed every second regeneration period.

As a result, an optimal regeneration period can be selected according to the environment of the semiconductor memory device to achieve low power consumption in the self regeneration mode. Instead of sacrificing low power consumption in the self regeneration mode, There is an effect that the information retention characteristics can be improved.

Description

Semiconductor memory

1 to 3 are block diagrams showing one embodiment of a pseudostatic RAM to which the present invention is applied.

4 is a layout view showing one embodiment of a pseudostatic RAM to which the present invention is applied.

5 to 11 are timing diagrams showing one embodiment of each operation cycle of the pseudostatic RAM to which the present invention is applied.

12 to 38 are diagrams showing specific configurations of each part of the pseudostatic RAM to which the present invention is applied.

39 to 41 are signal waveform diagrams showing one embodiment of a pseudostatic RAM to which the present invention is applied.

42 to 59 are conceptual, layout, signal waveform, and modified circuit diagrams for explaining the invention in each part of the pseudostatic RAM to which the present invention is applied.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device, and more particularly, to a technique particularly effective for a pseudostatic RAM (Random Access Memory).

The basic configuration is a dynamic RAM capable of high integration, and there is also a pseudo-static RAM designed to have an interface compatible with conventional static RAM. In addition to the normal write and read mode, the pseudo-static RAM performs address regeneration and automatic regeneration mode in which the regeneration operation is executed by external control in a single step, and for example, periodically and autonomously executes regeneration operation at the time of battery backup. It has a self regeneration mode. The pseudo-static RAM includes a reproducing counter for sequentially specifying word lines to be executed in the automatic regeneration and self regeneration modes, and a regeneration timer circuit for periodically starting the regeneration operation in the self regeneration mode.

For example, a pseudostatic RAM having an automatic regeneration mode and a self-regeneration mode is described in pages 229 to 234 of the Hitachi IC memory data book issued by Hitachi Corporation in March 1987.

The conventional magnetic regeneration mode is to perform regeneration in a predetermined regeneration period. Therefore, in consideration of fluctuations in the power supply voltage, influences of various external noises, fluctuations in the chip ambient temperature, and the like, regeneration is performed at a relatively short period in which the maintenance information of the memory cells is not lost.

Therefore, it is clear by the inventors that the self-regeneration is performed at a period shorter than the information holding time of the memory cell even in an ideal environment such as a fluctuation in power supply voltage, and the low power consumption in the self-regeneration mode is not sufficiently achieved by the inventors. Was done.

An outline of typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the semiconductor memory device of the present invention has a plurality of memory cells and control circuits, and when the device is in the first magnetic regeneration mode, the control circuit executes a regeneration operation for each of the plurality of memory cells every first regeneration period. When the device is in the first magnetic mode, the control circuit executes a regeneration operation for each of the plurality of memory cells every second regeneration period, which is longer than the first regeneration period.

According to the above means, since the semiconductor memory device has two playback modes with different playback periods, it is possible to select an optimal playback period in accordance with the environment of the semiconductor memory device. In other words, when the semiconductor memory device is in an ideal environment such as with a small change in power supply voltage, the regeneration operation is performed in a second regeneration period with a relatively long cycle, thereby making it possible to achieve low power consumption in the self regeneration mode. do.

In the case where the semiconductor memory device is in a strict environment such as a large fluctuation in power supply voltage or the like, instead of sacrificing low power consumption in the self regeneration mode, the regeneration operation is performed at a relatively short first regeneration period. It is possible to improve the information retention characteristic of the memory cell.

EMBODIMENT OF THE INVENTION Hereinafter, the structure of this invention is demonstrated with an Example.

In addition, in all the drawings for demonstrating an embodiment, the thing which has the same function attaches | subjects the same code | symbol, and the repeated description is abbreviate | omitted.

1 shows a block diagram of an embodiment of a selection circuit, a timing generating circuit, and a voltage generating circuit of a pseudostatic RAM to which the present invention is applied. 2 and 3 show block diagrams of one embodiment of the memory array of the pseudostatic RAM, the direct peripheral circuit, and the data input / output circuit, respectively. Further, the circuit elements constituting the blocks shown in Figs. 1 to 3 are not particularly limited, but are formed on one semiconductor substrate made of P-type single crystal silicon. In Figs. 1 to 3 and the following circuit diagrams, the signal lines relating to the input or output signals are shown starting from the bonding pads formed on the semiconductor substrate surface. Specific circuit configurations, operations and features of each block will be described in detail later.

The pseudostatic RAM of this embodiment has a dynamic RAM as a basic configuration, and the memory array is constituted by a so-called one-element type dynamic memory cell, thereby achieving high integration and low power consumption of the circuit. Further, the X address signals X0 to X10 and the Y address signals Y11 to T18 are input via separate address input terminals A0 to A10 and A11 to A18, respectively, and as a control signal, a chip enable signal. , Light enable signal And output enable signals Is provided to have an input / output interface compatible with a normal static RAM. In addition, the pseudo-static RAM designates an address reproducing mode that performs a single reproducing operation while specifying a reproducing address externally (herein, a type of method such as a reproducing operation or a test operation is referred to as a mode. In addition, the actual memory access in each mode is called an operation cycle, for example, the address playback cycle) and the playback counter RFC incorporating the playback address is used to perform the playback operation once. By using the regeneration counter RFC, the regeneration timer circuit TMR and the regeneration timer counter circuit SRC, which have an automatic regeneration mode, the self regeneration is performed autonomously and intermittently in a predetermined period for all word lines. Has a mode.

In this embodiment, the output enable signal Is not particularly limited, but the playback control signal Combined with this output enable signal And light enable signal By this operation mode of the pseudo-static RAM is selectively set.

Chip enable signal supplied from the outside as a start control signal in FIG. , Writer enable signal And output enable signals Ie playback control signal Is supplied to the timing generation circuit TG via the corresponding input buffers CEB, WEB, and OEB. The timing generator circuit TG has a 3-bit complementary internal address signal in the X address buffer XAB. (E.g., non-inverting internal address signal And reverse internal address signal Complementary internal address signal It is represented as The same applies to the complementary signal below). Timing generation circuit TG is the chip enable signal as described below. And light enable signal And output enable signals And complementary internal address signal Based on this, various timing signals necessary for the operation of each circuit block of the pseudostatic RAM are formed.

On the other hand, the 11-bit X address signals X0 to X10 supplied via the corresponding address input terminals A0 to A10 from the outside are not particularly limited, but are supplied to one input terminal of the X address buffer XAB and the 8-bit Y address signals Y11 to Y18 is supplied to the Y address buffer YAB. The other input terminal of the X address buffer XAB is supplied with 11-bit reproduction address signals AR0 to AR10 by the reproduction counter RFC.

The X address buffer XAB has an inverted timing signal from the timing generator circuit TG. And Is supplied, and the inversion timing signal is supplied to the Y address buffer YAB. Is supplied. Here, the inversion timing signal As described below, the pseudostatic RAM selectively goes to a low level when the pseudo-state RAM is selected in the auto-play and self-play modes, and the timing signal And Is selectively low when the level of the X address signals X0 to X10 or the reproduction address signals AR0 to AR10 or the Y address signals Y11 to X18 is determined when the pseudo-static RAM is in the selected state.

X address buffer XAB is a reverse timing signal because pseudo-static RAM is selected in the normal write or read mode. When the high level is reached, the inverted timing signal is converted from the X address signals X0 to X10 supplied via the external terminal. Keep entering by following. In addition, the pseudo-statistic RAM is selected in the regeneration mode, and the reverse timing signal The timing signal at which the reproduction address signals AR0 to AR10 supplied from the reproduction address counter RFC are reversed when Keep entering by following. The X address buffer XAB is also a complementary internal address signal based on these X address signals X0 to X10 or reproduction address signals AR0 to AR10. To form. Dual, lower 2-bit complementary internal address signal Is supplied to the timing generating circuit TG as described above, and the 3-bit complementary internal address signal is Is supplied to the word line select drive signal generation circuit PWD. 6-bit complementary internal address signal Is supplied to the X predecoder PXD. Complementary internal address signal Is also supplied to the X redundant circuits XR.

Each memory array of the pseudostatic RAM is provided with four redundant word lines and eight sets of redundant complementary data lines as described below. X redundant circuits XR (XRU, XRD) are complementary internal address signals supplied through the bad address assigned to each redundant word line and the X address buffer XAB during memory access. Compare by bit. As a result, if these addresses match all the bits, the corresponding inversion word line selection signal Selectively low level. Reverse redundant word line selection signal Is supplied to the redundant word line selection drive signal generation circuit PRWD which is provided in the word line selection drive signal generation circuit PWD.

Word line selection drive signal generation circuit PWD is the complementary internal address signal. And word line select drive signals X00U to X11U and X00D to X11D are selectively formed on the basis of the word line drive signal Фx supplied from the word line drive signal generation circuit ФxG. In addition, the redundant word line selection drive signal generation circuit PRWD includes the word line drive signal Фx and an inverted redundant word line selection signal. And complementary internal address signals The redundancy word line selection drive signals XR0U to XR3U or XR0D to XR3D are formed selectively.

Here, the word line driving signal Фx is at a predetermined boost level exceeding the power supply voltage of the circuit, and the word line selecting driving signals X00U to X11U (X00D to X11D) and redundant word line selecting driving signals XR0U to XR3U (XR0D to XR3D). ) Is also boost level.

X predecoder PXD is complementary internal address signal By sequentially decoding the two bits by bit, the corresponding predecode signals AX450 to AX453, AX670 to AX673, and AX890 to AX893 are alternatively formed. These predecode signals are commonly supplied to each X decoder.

Similarly, the Y address buffer YAB inverts the Y address signals Y11 to X18 supplied via an external terminal when the pseudostatic RAM is selected in the normal write or read mode. Keep typing by following. Also, the complementary internal address signals are based on these Y address signals. To form. Complementary internal address signals Is supplied to the Y predecoder PYD and the Y redundant circuit YRAC.

The Y redundant circuits YRAC are complementary internal address signals supplied through the Y address buffer YAB when a bad address assigned to each redundant data line and memory accesses. Is compared with a bit.

As a result, when these addresses coincide with all the bits, the corresponding redundant data line selection signals YR0 to YR7 are selectively set to a high level. The redundant data line selection signals YR0 to YR7 are supplied to the respective Y decoders via the Y predecoder PYD.

Y predecoder PYD is complementary internal address signal Are sequentially decoded by two bits, so that the predecode signals AY120 to AY123, AY340 to AY343, AY560 to AY563, and AY780 to AY783 are alternatively formed. These predecode signals are commonly supplied to the respective Y decoders through corresponding signal lines. In this embodiment, signal lines for transmitting the predecoder signals AY560 to AY563 and AY780 to AY783 to the respective Y decoders are shared as signal lines for transmitting the redundant data line selection signals YR0 to YR7. For this reason, the Y predecoder PYD is a complementary internal control signal supplied from Y redundant circuits YRAC. The predecode signals AY560 to AY563 and AY780 to AY783 or redundant data line selection signals YR0 to YR7 are selectively transmitted to the signal lines.

The pseudo-static RAM also has a substrate back bias voltage generation circuit VBBG that forms a negative substrate back bias voltage V _BB based on the power supply voltage of the circuit as shown in FIG. A voltage generating circuit HVCG is formed, which forms an internal voltage HVC of 2 voltage. In addition, the inversion timing signal supplied from the timing generation circuit TG. On the basis of this, a word line driving signal generating circuit ФxG for forming the word line driving signal Фx is provided.

In FIG. 2, this pseudo-static RAM is provided with eight memory arrays MARY0L and MARY0R to MARY3L and MARY3R which are substantially divided in the extending direction of the data line. These memory arrays are arranged symmetrically with the corresponding sense amplifiers SA0L and SA0R to SA3L and SA3R and the column switches CS0L and CS0R to CS3L and CS3R sandwiching corresponding Y address decoders YD0 to YD3, respectively. Incidentally, the sense amplifiers, column switches, and Y decoders corresponding to these memory arrays are arranged by dividing the corresponding X address decoders XD0L, XD0R to XD3L, and XD3R up and down, respectively, and corresponding to the arrangement position (U). Or the symbol (D) is added. In the following description, in order to avoid confusion, the symbols of (U) or (D) are omitted except where necessary. In addition, what is arrange | positioned above the X decoder among each memory array is called an upper side array, and what is arrange | positioned below is called a lower side array.

By the way, the memory arrays MARY0L to MARY3L and MARY0R to MARY3R are selectively put into an operational state by alternatively selecting the designated word lines. In this embodiment, when the pseudo-static RAM enters the normal write or read mode or the auto play mode, the eight memory arrays are MARY0L and MARY2L (or MARY0R and MARY2R) or MARY1L and MARY3L (or MARY1R and MARY3R). In combination, two are operated simultaneously. At this time, in each memory array, the upper side array or the lower side array is the complementary internal address signal of the most significant bit. According to the present invention, four sets of data lines are simultaneously selected from two memory arrays which become the operating states, respectively. The corresponding main amplifiers MALL and MALR or MARL and MARR or write circuits DILL and DILR or DIRL and DIRR It is connected to the corresponding unit circuit. As a result, this pseudostatic RAM is a RAM of a so-called 8-bit configuration for simultaneously inputting 8-bit storage data.

On the other hand, in the case where the pseudo-static RAM enters the self regeneration mode, although not particularly limited, the eight memory arrays are brought into an operating state at the same time. At this time, in each memory array, the upper side array or the lower side array is the complementary internal address signal of the most significant bit. In response to this, a regeneration operation for a total of eight word lines, which are selectively put into an operating state and alternatively selected from these memory arrays, is simultaneously executed. These regeneration operations are carried out periodically and autonomously at the same time as four times the normal regeneration period, and the regeneration address counter RFC is sequentially updated each time. As a result, the number of regenerations per unit time is substantially 1/4 in the self regeneration mode, thereby reducing the average current consumption of the memory array.

In FIG. 3, this pseudostatic RAM provides eight data input / output terminals IO0 to IO7 provided corresponding to eight bits of input or output data, and includes eight unit circuits corresponding to these data input / output terminals, respectively. A data input buffer DIB and a data output buffer DOB are provided. The data input / output terminals IO0 to IO7 are coupled to the unit circuit input terminals corresponding to the data input buffer DIB, and the data output buffer is coupled to the output terminals of the corresponding unit circuit. The timing signal Фdic is supplied to the data input buffer DIB from the timing generator circuit TG, and the timing signal Фdoc is supplied to the data output buffer DOB.

Here, the timing signal? Dic is not particularly limited, but it is selectively high level when the level of input data supplied via the data input / output terminals IO0 to IO7 is determined when the pseudostatic RAM is selected in the normal write mode. The timing signal FIdoc is selectively raised to a high level when the read signal levels of the eight selected memory cells are determined when the pseudo-static RAM is selected in the normal read mode.

The output terminals of the lower four unit circuits of the data input buffer DIB are coupled to the input terminals of the unit circuits corresponding to the write circuits DILL and DIRL, respectively, and the output terminals of the upper four unit circuits of the data input buffer DIB are the write circuits DILR and DIRR. Respectively coupled to the input terminal of the corresponding unit circuit. Similarly, the input terminals of the lower four unit circuits of the data output buffer DOB are respectively coupled to the output terminals of the unit circuits corresponding to the main amplifiers MALL and MARL, and the input terminals of the upper four unit circuits of the data output buffer DOB are the main amplifier. MALR and MARR are respectively coupled to the output terminals of the corresponding unit circuit. The timing signals Фma0 are supplied to the main amplifiers MALL and MALR, and the timing signals Фma1 are supplied to the main amplifiers MARL and MARR.

The data input buffer DIB inputs the input data supplied via the data input / output terminals IO0 to IO7 in accordance with the timing signal Фdic when the pseudo-static RAM is selected in the write cycle of the write system. Via the corresponding unit circuit, the eight memory cells that are simultaneously in the selected state are written to.

The data output buffer DOB inputs an 8-bit read signal amplified by the main amplifiers MALL to MARR in accordance with the timing signal Фdoc when the pseudo-static RAM is selected in the operation cycle of the read system. The data is sent to the outside via the data input / output terminals IO0 to IO7. When the timing signal Фdoc becomes low level, the output of the data output buffer DOB becomes a high impedance state.

Table 1 shows the operation cycles of the pseudostatic RAM to which the present invention is applied. 5 to 11 show timing charts of one embodiment of each operation cycle shown in Table 1. As shown in FIG. Based on these diagrams, an outline of each operation cycle of the pseudostatic RAM of this embodiment and its features will be described.

(1) lead cycle

The pseudostatic RAM has a chip enable signal, as shown in FIG. Enable signal at falling edge of And output enable signals Ie playback control signal The lead cycle is performed on the condition that is simultaneously at the high level. Output enable signal Is temporarily lowered at a predetermined timing which does not delay the output operation of the read data. Chip enable signal at address input terminals A0 to A10 and A11 to A18 In synchronization with the falling edge of, an 11-bit X address signal and an 8-bit Y address signal are supplied. The data input / output terminals IO0 to IO7 are normally in a high impedance state, and 8-bit read data output from eight memory cells which are simultaneously selected at the time when a predetermined access time has elapsed is sent out.

(2) The pseudo-static RAM has a chip enable signal as shown in FIG. Enable signal at falling edge of Becomes high level and the write enable signal is Chip enable signal Low level before the chip enable signal The light cycle is performed on the condition that it is delayed with respect to the low level temporarily at a predetermined timing.

X and Y address signals are input to the address input terminals A0 to A10 and A11 to A18, and 8-bit write data is supplied to the data input / output terminals IO0 to IO7 at predetermined timings which do not delay the write operation.

(3) lead verification light cycle

This operation cycle is an operation cycle combining the read cycle and the write cycle, that is, the pseudo-static RAM has a chip enable signal, as shown in FIG. Enable signal at falling edge of And write enable signal Since the high level, the lead cycle is started first. After the read data of the designated address is sent from the data input / output terminals IO0 to IO7, the write enable signal is output. 8-bit write data supplied from the data input / output terminals IO0 to IO7 is written to the above address at the time when the level becomes low level temporarily.

(4) address playback cycle

The pseudo-static RAM has a chip enable signal as shown in FIG. Enable signal at falling edge of And output enable signals Is executed at a high level and continues to be fixed at a high level thereafter. Chip enable signal at address input terminals A0 to A10 Is supplied with an 11-bit X address signal that specifies a word line to be reproduced in synchronization with.

In the pseudostatic RAM, two memory arrays are selected at the same time as in the read cycle, and one word line and two word lines in total are selected at the same time in each memory array. The storage data of 1024 and 2048 memory cells respectively coupled to these word lines are simultaneously output to the corresponding complementary data lines to be reproduced by the unit amplifier circuits corresponding to the respective sense amplifiers.

(5) Auto Play Cycle

The pseudo-static RAM has a chip enable signal as shown in FIG. Enable signal with high level fixed Ie playback control signal The auto regeneration cycle is executed on the condition that is temporarily low level in a relatively short time. At this time, a reproduction address for designating a word line to be reproduced is supplied from a reproduction counter RFC embedded in the pseudostatic RAM.

In the pseudostatic RAM, a total of two word lines designated by the reproduction counter RFC are selected at the same time, and the reproduction operation for the corresponding total 2048 memory cells is simultaneously performed. The reproduction counter RFC is automatically updated at the time after the output signal, that is, the reproduction address is input to the X address buffer.

(6) self-renewing cycle

The pseudo-static RAM has a chip enable signal as shown in FIG. Enable signal with high level fixed Ie playback control signal The self regeneration mode is provided on the condition that the low level continues for a relatively long time.

In the pseudostatic RAM, the regeneration timer counter circuit SRC is started, and at the same time, one self regeneration cycle in the self regeneration mode is executed. Then, the self regeneration cycle is repeated in a period corresponding to that the regeneration start signal of a predetermined frequency is output from the regeneration timer counter circuit SRC. At this time, the reproduction addresses are sequentially designated by the reproduction counter RFC.

By the way, in this self-regeneration cycle, in the pseudo-static RAM, eight memory arrays are operated at the same time and a total of eight word lines are selected. As a result, the reproducing operation for the 8192 memory cells coupled to these word lines is simultaneously performed, thereby reducing the average operating current of the memory array.

(7) test cycle

The pseudostatic RAM has an output enable signal as shown in Figs. 11 (a), (b) and (c). , Light enable signal Or chip enable signal The test cycles according to the three types of test modes are selectively executed provided that the predetermined high voltage exceeds the power supply voltage of the circuit.

The pseudostatic RAM starts a corresponding test cycle at the same time as determining the type of test mode by which one of the start control signals becomes the high voltage.

The details of each test mode and the operation of the pseudostatic RAM of each test cycle will be described in detail later.

This pseudostatic RAM has three test modes, which are not particularly limited but can be carried out via external terminals after product completion, as shown in Table 2.

ECRF: Extra Control Refresh

RCC: Refresh Counter Check

STIC: Self Timer Check

(1) ECRF test mode

The pseudo-static RAM has a chip enable signal as shown in Fig. 11A. Is fixed at a high level and the output enable signal The test cycle according to the ECRF test mode is performed by setting the predetermined high voltage exceeding the power supply voltage of the circuit. At this time, a predetermined test control signal is supplied to the address input terminal ALL of the pseudostatic RAM. That is, output enable signal At the rising edge of the test control signal at the high level, the pseudo-static RAM enters the self-regeneration mode, and at the low level the auto-regeneration mode is entered. In these self regeneration and auto regeneration modes, the reproduction address is supplied to the pseudo-static RAM via the address input terminals A0 to A10. These regeneration cycles are repeated by repeatedly changing the test control signal from a low level to a high level, and a reproducing address supplied to the address input terminals A0 to A10 is input for each rise of the test control signal.

As a result, the address dependence and the like in the reproducing operation of the pseudostatic RAM can be verified and the regeneration period can be arbitrarily set by the test control signal, so that the information holding characteristic and the like of the pseudostatic RAM can be tested and confirmed.

(2) RCC test mode

The pseudo-static RAM has a chip enable signal as shown in FIG. 11 (b). Is fixed at high level and output enable signal Becomes the normal low level, and the output enable signal Enable signal before and after the falling edge of The test cycle according to the RCC test mode is selectively performed by setting the predetermined high voltage beyond the power supply voltage of the circuit. That is, the write enable signal Output enable signal When a high voltage is delayed with respect to the falling edge of P, the pseudo-static RAM enters the self-regeneration mode and outputs an enable signal. In the case of high voltage prior to the descent, the auto regeneration mode is activated. At this time, the reproduction address is designated by the reproduction counter RFC, and the reproduction counter RFC is updated at the falling edge of the test control signal supplied through the address input terminal A11. Further, in these reproduction cycles, in the pseudo-static RAM, all of the write operations are performed for the memory cells of a specific column address while the word lines are sequentially selected.

As a result, it is possible to test-check the counting function of the reproducing counter incorporated in the pseudo-statistic RAM by sequentially reading and writing data written to a specific address of each word line by a normal read cycle.

(3) STIC test mode

The pseudo-static RAM has a chip enable signal as shown in Fig. 11C. Becomes a predetermined high voltage exceeding the power supply voltage of the circuit, and the output enable signal The test cycle for the STIC test mode is performed by slightly delaying to the low level. At this time, the pseudostatic RAM enters the self-regeneration mode. And the output signal of the regeneration timer circuit TRM, that is, the inversion timing signal counted by the regeneration timer counter circuit SRC. An inversion timing circuit which is output via the data input / output terminal IO6 and determines the output signal of the regeneration timer counter circuit SRC, that is, the regeneration period of the self regeneration mode. Is output via the data input / output terminal IO7.

As a result, it is possible to test-test the regeneration cycle in the self regeneration mode of the pseudostatic RAM.

As described above, in the pseudostatic RAM, the chip enable signal is , Light enable signal And output enable signals The type of the test mode is determined by setting the start control signal such as the high voltage selectively above the power supply voltage of the circuit, and the start condition of the test cycle.

As a result, the setting of the test mode and the start of the test cycle are realized simultaneously, and the test operation of the pseudostatic RAM can be simplified.

By the way, the regeneration timer counter circuit SRC incorporated in the pseudo-statistic RAM is constituted by an 8-bit binary counter, and the fuse initial value corresponding to each bit is selectively cut so that the count initial value, that is, the townter. Modulo is optionally set. Therefore, although not employed in the pseudostatic RAM of this embodiment, the method as shown in FIG. 50 is considered as a method for effectively testing the characteristics of the regeneration timer counter circuit SRC.

That is, in Fig. 50, the pseudo initial RAM is supplied with the count initial value of the regeneration timer counter circuit SRC via the address input terminals A0 to A7, for example. Initial values of these coefficients, i.e. inverted internal signals Is an inverted timing signal Is inputted to the corresponding bit of the regeneration timer counter circuit SRC at the low level, whereby the count initial value of the regeneration timer counter circuit SRC is set. As a result, the characteristics of the regeneration timer circuit TMR and the regeneration timer counter circuit SRC according to the count initial value can be tested and confirmed, and the operation characteristics can be tested and confirmed while the pseudo-statistic RAM switches the regeneration period.

The pseudostatic RAM takes a non-address multiplex method as described above, and provides a total of 19 address input terminals A0 to A18. In addition, a total of 16 memory arrays are arranged in pairs, which are substantially divided up and down, and each memory array is selectively selected as described below, and 64 groups divided into four groups in total, 256 in total. And 1024 sets of complementary data lines each of which is selectively selected at the same time by four word lines and four sets. As a result, each memory array has an address space of substantially 262144, so-called 256K bits, whereby the pseudostatic RAM has a so-called 4M bit storage capacity.

When the pseudostatic RAM is selected in the normal operation mode, the sixteen memory arrays are so-called pairs selected at substantially the same time. Then, four memory cells in total and eight memory cells in total are selected from two memory arrays which are operated at the same time, and are connected to the corresponding common I / O lines. These memory cells are also connected to corresponding unit circuits of the data input buffer DIB or data output buffer DOB via corresponding write circuits or main amplifiers.

In this pseudostatic RAM, the address signals input via the nineteen address input terminals A0 to A18 are not particularly limited, but are classified as shown in Table 3 and used for corresponding applications, respectively.

That is, the 11 bits first inputted through the address input terminals A0 to A10 become X address signals, and the lower two bits of the address signals A0 and A1 and the most significant bit of the address signal A10 are supplied to the timing generating circuit TG. In the timing generating circuit TG, the selection of the memory array pair is performed by the address signals A0 and A1, and the selection of the upper or lower side array is performed by the address signal A10. As a result, 16 memory arrays are selected by one-eighth, and two of them are operated at the same time. As described above, when the pseudo-static RAM enters the self-regeneration mode, the address signals A0 and A1 are meaningless, and eight upper or lower sides of the array are in an operating state.

Next, the 6-bit address signals A4 to A9 are supplied to the X predecoder PXD and decoded in combination of two bits each. As a result, the corresponding predecode AX450 to AX453 to AX890 to AX893 are alternatively at a high level. These predecode signals are supplied to the X decoder and used to selectively select the word line group of each memory array. The two-bit address signals A2 and A3 are supplied to the word line selection drive signal generation circuit PWD and are combined with the word line drive signal øx outputted from the word line drive signal generation circuit øxG. The word line selection drive signals X00 and X01 , X10, X11 are used to alternatively form. As described above, the word line drive signal? X and the word line select drive signals X00 to X11 become a predetermined boost level exceeding the power supply voltage of the circuit. As a result, one of 256 word lines constituting the two memory arrays specified by the address signals A0, A1, and A10 in accordance with the 8-bit address signals A2 to A9 is alternatively selected.

Similarly, the 8-bit address signals A11 to A18 input via the address input terminals A11 to A18 become Y address signals and are used for selecting the data line. That is, the address signals A11 to A18 are supplied to the Y predecoder PYD, and are decoded by 2 bits each by a combination of A11 and A12, A13 and A14, A15 and A16, A17 and A18 as shown in Table 3. As a result, the corresponding predecode signals AY120 to AY123, AY340 to AY343, AY560 to AY563, and AY780 to AY783 are alternatively at a high level. These pre-decode signals are further combined by the decoder-free decoder of the Y decoder, and as a result, four sets of eight complementary data lines are selected from the two memory arrays to be operated and connected to the corresponding common I / O lines. .

As a result, eight memory cells are selected from the so-called 4M bit memory cells, and the input / output operation of the 8-bit storage data passing through the data input / output terminals IO0 to IO7 is executed.

As described above, the pseudo-static RAMs each have a total of 16 memory arrays, which are paired up and down and divided into two substantially, and each memory array is not particularly limited, but four redundant word lines and 32 redundant complementary data lines, respectively. Prepare. These redundant word lines and redundant reward lines are not particularly limited, but are switched at the same time in the above 16 memory arrays and for a common defective element, and one or four respectively instead of the corresponding combined word lines or combined complementary data lines. Selectively selects by step. Therefore, the pseudo-static RAM is not particularly limited, but four X redundant circuits XR0 to XR3 provided in common corresponding to redundant word lines of all memory arrays and eight correspondingly provided for four sets of redundant complementary data lines. Y system long circuits YRAC0 to YRAC7 are provided.

Of these, the X-based redundant circuits XR0 to XR3 are 8-bit address signals A2 to A9 except that they are used for address selection, that is, complementary internal address signals. And compare and compare the bad addresses assigned to the corresponding redundant word lines. As a result, if both addresses coincide with all the bits, the output signal, that is, the corresponding reverse long word line selection signal. To low level. These inversion long word line selection signals are subjected to the word line drive signal? X and the complementary internal address signal by the word line selection drive signal generation circuit PWD as described above. And redundant word line selection drive signals XR0U to XR3U or XR0D to XR3D corresponding to the upper or lower side arrays. These redundant word line selection drive signals are supplied to each X decoder to be used for the selection operation of the redundant word line. Of course, when the redundant word line is selected, the selection operation of the combined word line specified by the address signals A2 to A9 is stopped.

By the way, the X-based redundant circuits XR0 to XR3 of this pseudo-static RAM are four-bit X address signals, i.e., complementary address signals, as illustrated in FIG. X-based long-circuit circuits XR0U to XR3U and the remaining four bits of X address signals disposed on the upper side of the semiconductor substrate surface. And and Is further divided into X-based long circuits XR0D to XR3D arranged on the lower side of the semiconductor substrate surface. These X-based redundant circuits include two fuse means, which are redundant ROM (lead-only memory), and are substantially complementary internal address signals corresponding to bad addresses held by these fuse means. Four redundant address comparison circuits and a matching detection node N9 and N10 for determining that the circuits are matched, and a subordinate MOSFET (metal oxide semiconductor) receiving the output signal of the redundant address comparison circuit corresponding to the gate in series form. Type field effect transistors, each of which includes a temporary detection circuit in which a MOSFET is referred to collectively as an insulated gate field effect transistor. The coincidence detection nodes N9 and N10 are also coupled to corresponding input terminals of a two-input NOR gate circuit that substantially constitutes a negative logic circuit.

As a result, the output signals of the respective X-based redundant circuits, i.e., the inverted redundant word line selection signals, provided that the coincidence detection nodes N9 and N10 both have a low level and the output signal of the corresponding redundant enable circuit XRE is at a high level. This selectively becomes low level.

In this way, the subordinate MOSFETs constituting the coincidence detection circuit of the redundant circuit are divided into a plurality of address input pads or address buffers arranged on the upper side or the lower side of the semiconductor substrate surface, and each output signal is logically multiplied by a logic circuit. Combining substantially speeds up the operation of the redundant circuit, and therefore, the access time of the pseudostatic RAM can be speeded up.

Meanwhile, the redundant enable signal XRE provides first and second fuse logic gate circuits each including fuse means F1 and F2, as shown in FIG. 44B. The fuse logic gate circuit is a P-channel type (first conductive type) MOSFET QP16 or QP18 (18th) provided between an internal node N7 or N8 (fourth internal node) and a power supply voltage (first power supply voltage) of the circuit. MOSFET) and an N-channel type (second conductive type) MOSFET QN21 provided in series with the fuse means F1 or F2 corresponding to the internal node N7 or N8 and the ground potential (second power supply voltage) of the circuit. Or QN22 (19th MOSFET).

The MOSFETs QP16 and QN21 and QP18 and QN22 act as one CMOS inverter provided that the corresponding fuse means are not cut. At this time, the levels of the internal nodes N7 and N8 are inverted timing signals. Becomes low level on condition that the low level becomes high or the timing signal XDP becomes high level. If the corresponding fuse means F1 or F2 is cut by, for example, a laser beam or the like, the levels of the internal nodes N7 and N8 become the inversion timing signal. And high level regardless of the timing signal XDP.

The output signal of each fuse logic gate circuit, i.e., the levels of the internal nodes N7 and N8, are intact or inverted and then supplied to an exclusive logic circuit consisting of the NAND gate circuits NAG7 to NAG9. The output signal of the NAND gate circuit NAG9 becomes the output signal XRE of the redundant enable circuit XRE.

In this way, the output signal XRE of the redundant enable circuit XRE is an inverted timing signal. Becomes high level and at the same time becomes low level irrespective of the cutting state of the corresponding fuse means when the timing signal XDP becomes low level.

The inversion timing signal When the low level or the timing signal XRE becomes the high level, the high level is provided on the condition that either of the corresponding fuse means F1 or F2 is cut. At this time, when both of the fuse means F1 and F2 are cut or not cut, the output signal XRE of the redundant enable circuit XRE remains low.

In this way, the fuse circuit included in the redundant enable circuit XRE or the like is configured based on a so-called fuse logic gate circuit in which a fuse means is provided between the N-channel or P-channel MOSFET of the CMOS logic gate circuit and the output node. The circuit can be simplified and the cost can be reduced. Also, by providing two fuse logic gate circuits in the fuse circuit and performing an exclusive OR operation on the output signal of the fuse logic gate circuit, the X-based redundant circuit to which the bad address has been assigned once is equivalently returned to its original initial state. It is possible to turn. As a result, flexibility in redundancy allocation of pseudostatic RAM can be increased.

Of course, the fuse circuit can be used for each redundant address comparison circuit of the X based redundant circuit and the Y based redundant circuit, and can also be used in various fuse circuits such as a preset fuse circuit of the regeneration timer counter circuit SRC described below.

Next, the Y redundant circuits YRAC0 to YRAC3 of the pseudo-statistic RAM have 8-bit address signals A11 to A18, that is, complementary internal address signals. And compare and compare the bad addresses assigned to the four redundant redundant data lines. As a result, when all bits of both addresses coincide, the output signal, that is, the corresponding redundant data line selection signals YR0 to YR7 is selectively set to a high level. These redundant data line selection signals are transferred to each Y predecoder PYD via the Y predecoder PYD as described above, and used for the selection operation of the redundant complementary data line.

Of course, when the redundant complementary data lines are selected, the selection operation of the combined complementary data lines specified by the address signals A11 to A18 is stopped.

However, the redundant data line selection signals YR0 to YR7 supplied to the Y decoder YD through the predecoder PYD share eight signal lines for supplying the predecode signals AY560 to AY563 and AY780 to AY783 as shown in FIG. Delivered. For this reason, the inversion timing signal that becomes low when any redundant complementary data line is selected for the Y predecoder PYD. In accordance with this, a multiplexer for selectively transmitting the predecoder signals AY560 to AY563 and AY780 to AY783 or the redundant data line selection signals YR0 to YR7 is provided. Y decoder YD is the reverse timing signal. When the signal is high level, the signal transmitted via the signal line is received as the predecode signals AY560 to AY563 and AY780 to AY783, and the reverse timing signal is obtained. When the signal reaches the low level, the signal transmitted via the signal line is received as the redundant data line selection signals YR0 to YR7. As a result, the arrangement around the array portion where the signal lines are relatively crowded can be made efficient, and the arrangement area can be reduced.

On the other hand, the 32 sets of redundant complementary data lines provided in each memory array are selected at the same time, each of 4 sets as described above, and substantially constitute the eight redundant data line groups RY0 to RY7. The pseudostatic RAMs are provided with 16 memory arrays, which are paired as upper and lower arrays, respectively, and the redundant data line group is switched at the same time for these defective memory elements. For this reason, in the pseudo-static RAM of this embodiment, redundant redundancy data line groups RY0 to RY7 of two pairs of memory arrays are arranged in line symmetry with respect to the center line of the semiconductor substrate surface as shown in FIG. . As is well known, the incidence rate of failure of each element increases as it approaches each side of the semiconductor substrate surface. By arranging the redundant complimentary data fleet RY0 to RY7 in the order of linear symmetry in this way, the incidence of failure on the RYO side of the redundant complimentary data fleet is deliberately increased, and the incidence of failure of the other redundant complimentary data fleet is low. As a result, the average incidence of failure as a whole redundant redundant data line is suppressed and the efficiency of the pseudostatic RAM is increased.

Of course, the above arrangement method of redundant redundant data line can achieve the same effect with redundant word line. This pseudostatic RAM has three types of reproduction modes as described above, namely, address reproduction, automatic reproduction, and magnetic reproduction mode. The reproduction address for specifying the word line to be reproduced is supplied from, for example, a memory control unit provided externally in the address reproduction mode, and from a reproduction counter RFC embedded in the case of automatic reproduction and magnetic reproduction.

On the other hand, the period for executing the reproducing operation, that is, the reproducing period is set by the information holding capability of the memory cell as described above, and is defined as a product standard.

This regeneration period is managed by an external memory control unit that accesses the pseudo-static RAM in the address regeneration and automatic regeneration mode, as can be seen from the description of the operation cycle described above, and in the self regeneration mode, the timing generation circuit TG. It is managed by the regeneration timer circuit TMR and the regeneration timer counter circuit SRC.

The regenerative timer circuit TMR includes a ring oscillator formed by serially combining seven inverter circuits of which operation current is limited in a ring shape, as shown in FIG. 15, and forms an output signal, that is, a timing signal? Tmr at a predetermined period. do. As shown in Fig. 14, the timing signal? Tmr becomes the timing signal? C1 through the two-input NOR gate circuit and the inverter circuit, and is used as the counting pulse of the regeneration timer counter circuit SRC.

The regenerative timer counter circuit SRC has a binary counter structure of 8 bits, and the unit circuit corresponding to each bit has a pair of main latches and slave latches and their initial values, respectively, as shown in FIG. A fuse circuit for selectively setting to 1 is included. In the regeneration timer counter circuit SRC, the count initial value is set by selectively cutting the fuse means of each unit circuit, thereby setting the count period, that is, the counter modulo. The output signal of the regeneration timer counter circuit SRC, i.e., the output carry signal SCA7, is combined with the timing signal? C1 and is an inversion timing signal for determining the regeneration period in the self regeneration mode. Used to form

The timing signal? C1 and the inverted timing signal when the pseudostatic RAM enters the STIC rest mode. Is monitored via the tape type output terminal IO6 or IO7 as described in the above test method.

However, in the self-regeneration mode in the pseudo-statistic RAM, as in this embodiment, the so-called PS (pseudo) regeneration mode used when the battery is in a non-selection state over a relatively long time, for example, during battery backup, etc. For example, there is a VS (virtual) reproducing mode which is intermittently executed by using a gap in memory access.

As is well known, the regeneration period of the VS regeneration mode executed by using the gap in which the pseudo-statistic RAM becomes active becomes shorter than the regeneration period of the PS regeneration mode executed when it is almost inactive.

For this reason, as shown in FIGS. 51 and 52, it is possible to set different regeneration periods in the VS and PS regeneration modes, respectively, so that they are applied to both regeneration modes based on one common semiconductor substrate (base chip). It can provide pseudostatic RAM.

That is, in FIG. 51, the inversion timing signal for starting the self regeneration cycle in the PS regeneration mode is shown. Is formed by combining the carry signal SCAj +2 of the most significant bit of the regeneration timer counter circuit SRC and the output signal of the regeneration timer circuit TMR, that is, the timing signal? C1. And a reverse timing signal for starting the self regeneration cycle in the VS regeneration mode. Is formed by combining the carry signal SCAj + 1 of the next bit of the regeneration timer counter circuit SRC with the timing signal? C1. As a result, the inversion timing signal in the VS reproduction mode. The period of is inverted timing signal in PS playback mode as shown in FIG. 1/2 of.

4 is a layout view of one embodiment on the semiconductor substrate surface of the pseudostatic RAM to which the present invention is applied. Based on Fig. 4, the basic arrangement of the pseudostatic RAM of this embodiment will be described.

That is, in FIG. 4, since the semiconductor substrate is shown sideways on the surface of the paper, in the following description, the left side of the same drawing is called the upper side of the semiconductor substrate surface.

As described above, the pseudostatic RAM is provided with eight (substantially 16) memory arrays MARY0L to MARY3L and MARY0R to MARY3R divided into respective upper and lower sides, and an X address provided corresponding to these memory arrays. Corresponding to the decoders XD0L to XD3L and XD0R to XD3R and two memory arrays, four Y address decoders YD0 to YD3 are respectively provided, which are divided into upper and lower sides.

In FIG. 4, X address decoders XD0L to XD3L and XD0R to XD3R are disposed in the center portion of the semiconductor substrate surface, and corresponding word line driver circuits WD0LU to WD3LU (WD0LD to WD3LD) and WD0RU to WD3RU (WD0RD to WD3RD) on the upper and lower sides thereof. Are arranged respectively. Then, the memory arrays MARY0L to MARY3L and MARY0R to MARY3R corresponding to each of the X-based selection circuits have Y decoders YD0 to YD3 corresponding to them, and the word lines extend in the vertical direction. Is placed. Although not shown, corresponding sense amplifiers SA0L to SA3L and SA0R to SA3R and column switches CS0L to CS3L and CS0R to CS3R are disposed close to the Y address decoders YD0 to YD3, respectively.

At the top of the memory arrays MARY0L to MARY3L and MARY0R to MARY3R, a pre Y address decoder PYD and a Y address redundancy control circuit YRAC are disposed. In addition, the main amplifiers MALL to MARR and the write circuits DILL to DIRR are disposed below these memory arrays.

Bonding pads are disposed on each side of the semiconductor substrate surface to avoid positions near each corner of the semiconductor substrate surface and positions near the centers of the side portions of the left and right sides. In addition, corresponding unit circuits of the X address buffers XAB and Y address buffers YAB, and the data input buffer DIB and the data output buffer DOB are arranged in close proximity to these pads.

12 to 38 show a circuit diagram of one embodiment of each part of the pseudostatic RAM to which the present invention is applied. 39 to 41 show signal waveforms of one embodiment of the pseudostatic RAM. According to the circuit diagrams of FIG. 12 and FIG. 38, the specific configuration and arrangement of each part of the pseudostatic RAM of this embodiment, the operation and features thereof will be described. The signal waveform diagrams of Figs. 39 to 41 are referred to as necessary.

As described above, the pseudostatic RAM of this embodiment is provided with a total of 16 memory arrays MARY0L to MARY3L and MARY0R to MARY3R which are each paired. Two pairs of memory arrays are arranged symmetrically with an X-based selection circuit disposed at the center of the semiconductor substrate surface, and the corresponding four sets of common I / O lines and one pair of common source lines are the memory arrays. It is arranged to penetrate through.

The upper and lower side arrays of the memory arrays MARY0L to MARY3L and MARY0R to MARY3R are 256 word lines W0 to W255 arranged in parallel with the vertical direction of the same drawing as shown in FIG. 38 and four redundant word lines RW0 not shown. 1024 sets of complementary data lines provided with RW3 and arranged in parallel with the horizontal direction And 32 chartered redundancy data ship, not shown. To prepare. At the intersections of these word lines and complementary data lines, an information storage capacitor and a dynamic memory cell serving as an address selection MOSFET are combined with a predetermined regularity.

The word lines constituting each memory array are coupled to the corresponding X decoders XD0L to XD3L or XD0R to XD3R on either side, and are alternatively selected. The other side is coupled to the ground potential of the circuit via an N-channel MOSFET that receives an inverted signal such as word line clear signals WC0U to WC3U corresponding to the gate. These word line clear signals are usually at a low level, and a 3-bit complementary internal address signal when the pseudostatic RAM is selected. It is selectively raised to a high level accordingly. As a result, the word lines of the respective memory arrays are usually in a low level clear state, and are selectively released from the clear state provided that at least the corresponding word lines are in the select state when the pseudostatic RAM is in the select state.

On the other hand, although the complementary data lines constituting each memory array are not particularly limited, corresponding units are provided via corresponding unit charge circuits UPC0 to UPC3 of the corresponding sense amplifiers SA0L to SA3L to SA0R to SA3R, as shown in FIG. Four sets of common I / O lines coupled to amplifying circuits USA0 to USA3 and through corresponding switch MOSFETs of column switches CS0L to CS3L to CS0R to CS3R. or To or 4 pairs of connections are selectively connected.

The sense amplifiers SA0L to SA3L to SA0R to SA3R are not particularly limited, but each 1056 units are provided corresponding to each complementary data line and redundant complementary data line of the corresponding memory array as shown by the sense amplifier SA0L in FIG. Precharge circuits UPC0 to UPC3 and unit amplifier circuits USA0 to USA3 are included.

The dual unit precharge circuits UPC0 to UPC3 are not particularly limited, but include three N-channel MOSFETs each provided in series and parallel form between non-inverting and inverting signal lines of corresponding complementary data lines. The gates of these MOSFETs are all commonly coupled, and an inverted timing signal in the timing generation circuit TG. And the like are commonly supplied. Here, the inversion timing signal The back is usually at a high level, and the complementary internal address signal when the pseudostatic RAM is selected. It is selectively lowered accordingly.

As a result, the three MOSFETs constituting each unit precharge circuit are normally in an ON state, and the half precharge level at which the non-inverting and inverting signal lines of the corresponding complementary data lines are shorted to be half the level of the power supply voltage of the circuit. It is called HVC. Pseudo-static RAM is selected and the inverted timing signal When the lamp is at a low level, the three MOSFETs are turned off, whereby corresponding complementary data lines selectively cancel the short circuit state.

On the other hand, the unit amplifier circuit of each sense amplifier is not particularly limited, but as shown in FIG. 18, a latch is formed in which two CMOS inverter circuits are cross-connected, respectively. The source of the P-channel MOSFET constituting each unit amplifier circuit is commonly coupled to the common source line SP, and is coupled to the power supply voltage of the circuit via four P-channel driving MOSFETs in parallel. Inverting timing signals corresponding to the sense amplifier driving circuits SP0L to SP3L or SP0R to SP3R are provided on the gates of these driving MOSFETs. And the like are supplied respectively. Similarly, the source of the N-channel MOSFETs constituting each unit amplification circuit is commonly coupled to the common source line SN and coupled to the ground potential of the circuit via two N-channel drive MOSFETs in parallel. The gates of these drive MOSFETs are supplied with corresponding timing signals P1OUL, P2OUL and the like in the corresponding sense amplifier drive circuits SN0L to SN3L or SN0R to SN3R, respectively.

Each of the sense amplifiers is not particularly limited, and each of the sense amplifiers includes three N-channels each provided in series and parallel form between the common source line SP and the SN.

The gates of these MOSFETs are commonly coupled and inverted timing signals Etc. are supplied. 2 reverse timing signal Etc., the inversion timing signal It becomes high level or low level on the same timing conditions as these. As a result, when the pseudo-static RAM becomes non-selected, the common source lines SP and SN are shorted to become the half precharge level HVC. When the pseudostatic RAM is selected, the precharge operation of the common source lines SP and SN is selectively stopped.

The unit amplifier circuit of each sense amplifier has a corresponding inversion timing signal. The lamps are at a low level, and the corresponding timing signals P1OUL to P2OUL and the like are at a high level, thereby selectively operating. In this operation state, each unit amplification circuit amplifies the micro read signal outputted through the corresponding complementary data line in the memory cell in which the corresponding memory array is coupled to the selected word line, thereby producing a high level or low level binary lead signal. . These binary read signals are transmitted to the main amplifier via the corresponding common I / O line when the pseudostatic RAM is in a normal read cycle, and rewritten to the corresponding memory cell when the pseudostatic RAM is in any regeneration cycle. do.

By the way, the pseudostatic RAM of this embodiment is characterized by the arrangement of the sense amplifiers. That is, as shown in FIG. 43, a pair of P-channel MOSFETs QP23 (18th MOSFET) and QP24 (19th MOSFET) or N-channel MOSFET QN25 (20th MOSFET) constituting each unit amplifier circuit of the sense amplifier. ) And QN26 (21st MOSFET) each have a source S formed by a common diffusion layer L and extend in a direction perpendicular to the complementary data line of the source S, drain D and gate G. Is formed. The source S of each pair of MOSFETs formed by the common diffusion layer L is a common source line SP (first common source line) formed on the upper layer via a corresponding contact, for example, using aluminum or its alloy, or At the same time as the SN (second common source line), the diffusion layer L is extended as it is, as shown in FIG. 43, so as to be commonly coupled to the source S similar to the pair of adjacent MOSFETs. As a result, as compared with the conventional pseudostatic RAM and the like in which the diffusion layer L does not extend, the incidence rate such as a failure in which the characteristics of the unit amplification circuit decrease due to contact failure or the like, for example, can be reduced, and the efficiency of the pseudostatic RAM can be improved.

The sense amplifier driving circuits SP and SN are timing signals P1 to P4 and P1a to P4c or P1D to P2D and P1Da to P1Dc and internal address signals AX0U and AX1U or AX0D supplied from the timing generation circuit TG as shown in FIG. And the inversion timing signal based on AX1D and AX10. And P1OUL, P2OUL and the like are selectively formed.

The column switches CS0L to CS3L and CS0R to CS3R include a total of 1056 pairs of switch MOSFETs provided corresponding to each complementary data line of the corresponding memory array. One of these switch MOSFETs is coupled to a corresponding complementary data line via a unit circuit of the corresponding sense amplifier, and the other of the corresponding four sets of common I / O lines. And To or In order sequentially and intersections are combined in common. The gates of the respective switch MOSFETs are commonly coupled in sequence by four sets, and corresponding data line selection signals YS0 and the like are supplied from the corresponding Y address decoders YD0 to YD3, respectively.

Each of the four pairs of switch MOSFETs constituting the column switches CS0L to CS3L and CS0R to CS3R is selectively turned on at the same time as the corresponding data line selection signal YS0 or the like is at a high level. As a result, four sets of common I / O lines to which four sets of complementary data lines of corresponding memory arrays correspond. or To or It is optionally connected to.

However, the common I / O line in pseudostatic RAM And To And As described above, each of the memory arrays penetrates through the pair of memory arrays disposed on the upper and lower sides of the semiconductor substrate.

At this time, the non-inverting and inverting signal lines of each common I / O line intersect at the middle of the upper side and the lower side array as shown in FIG. Therefore, in the manufacturing process of the pseudostatic RAM, for example, a photomask for forming a polysilicon layer serving as the gate G of the switch MOSFET of the corresponding column switch has caused a misalignment with respect to the diffusion layer L serving as the source and drain thereof. Even if non-inverted signal IO and inverted signal line of common I / O line The change in parasitic capacity bound to is offset in the upper and lower arrays. As a result, the level difference in each common I / O line is eliminated, and the read operation of the pseudostatic RAM is stabilized.

In addition, these common I / O lines And To And Although not shown in FIG. 38, when the pseudo-static RAM becomes non-selected, the non-inverting and inverting signal lines are short-circuited at the middle of each of the upper and lower sides of the corresponding upper and lower side arrays, and also half precharged. The so-called equalization process of level HVC is performed. Then, the pseudostatic RAM is placed in the selected state, and the equalization process is selectively stopped by the corresponding memory array being placed in the selected state. As a result, the equalization processing of the common I / O line is reliably executed at the same time and at high speed, so that the signal transmission delay time of the common I / O line is reduced and the pseudostatic RAM can be increased.

As shown in FIG. 18, the X address buffer XAB has eleven unit circuits provided corresponding to the address input terminals A0 to A10. These unit circuits include a multiplexer for selectively transferring X address signals X0 to X10 or corresponding reproduction address signals AR0 to AR10 supplied via the address input terminal corresponding to the inversion timing signal _ supplied from the timing generation circuit TG. And a latch circuit for inputting and holding an address signal transferred through the multiplexer in accordance with the timing signal? X1s. The output signal of each latch circuit is also gate-controlled in accordance with the timing signal? X1s, and then the corresponding complementary internal address signal. Becomes

The reproduction counter RFC provides eleven counter unit circuits CNTR provided corresponding to the reproduction address signals AR0 to AR10 as shown in FIG. These counter unit circuits each include a main latch and a slave latch that are coupled in series in a ring shape as shown in FIG. The carry input terminal and carry output terminal are substantially coupled in series by sequentially combining, and constitutes one binary counter to invert the counter pulse. Executes the forward operation according to the

Here, the inversion counter pulse The inversion timing signal is determined by a pseudostatic RAM being used for automatic regeneration or self regeneration cycle. Is at a low level and the pseudo-statistic RAM is in a selected state, thereby inverting the timing signal. Becomes low level and then becomes low level temporarily until timing signal P1 becomes high level. As a result, the reproduction address signals AR0 to AR10 are initially inputted to the corresponding unit circuit of the X address buffer XAB after the pseudo-static RAM is selected, and then updated to the next advanced state.

The X predecoder PXD is a complementary internal address signal of two bits, respectively, as shown in FIG. A total of twelve decoder unit circuits are provided, each of which receives a predetermined combination. The output signals of these decoder unit circuits are supplied to the respective X decoders as the predecode signals AX450 to AX453, AX670 to AX673, and AX890 to AX893.

Although not particularly limited, the complementary internal address signal for array selection is included in the X predecoder PXD shown in FIG. Several decoder unit circuits for forming various array selection signals based on these are included. Dual Inverted Array Selection Signal Is used to selectively operate the X decoders XD0L and XD0R to XD3R and XD3R, and the array selection signals AXD0L, AXD1L and AXD0R, AXD1R are supplied to the array selection circuit, for example, for the switching process of the common I / O line. Is used.

Array selection circuit ASL is an inverted selection timing signal for common I / O line equalization based on the array selection signals AXD0L, AXD1L and AXD0R, AXD1R and timing signals CE3D supplied from the X predecoder PXD as shown in FIG. And or And or And or And Is optionally formed. In addition, an inverted array selection signal for selectively connecting a common I / O line and a memory amplifier based on the array selection signal and the timing signal CE3D and a timing signal? We that is selectively at a high level in a write system operation cycle. And or And or And or And Is optionally formed.

The array selection circuit ASL is also provided with timing signals IOU0L and IOU2L or IOU0R and IOU2R for presetting common I / O lines by applying a logic condition of the timing signal øiou, which is temporarily high, just before the main amplifier becomes operational. Optionally form IOU1L and IOU3L or IOU1R and IOU3R.

As described above, the pseudo-static RAM provides four X-based redundant circuits XR0 to XR3 provided corresponding to redundant word lines RWL0 to RWL3 of the memory array. These X-based redundant circuits include an X-based redundant circuit SRU disposed on the upper side of the semiconductor substrate surface as shown in FIG. 20, an X-based redundant circuit XRD and a redundant enable circuit XRE disposed on the lower side, respectively.

The dual redundant enable circuit XRE includes two fuse logic gate circuits whose output signals are coupled exclusively as described above.

The output signals XRE0 to XRE3 of these redundant enable circuits are inverted timing signals. When the low level or the timing signal XDP becomes high, the high level is selectively provided provided that only the fuse means included in one of the fuse logic gate circuits is disconnected. As a result, these output signals XRE0 to XRE3 indicate that a bad address is written to the corresponding X-based redundant circuit and that the corresponding redundant word line is in use.

On the other hand, the X redundant circuits XRU and XRD each include four redundant circuits each including a pair of fuse means selectively cut by the corresponding bit of the bad address assigned to the corresponding redundant word line being logical 0 or logic 1. It has an address comparison circuit. The redundant address comparison circuit selectively enters an operating state when the output signals XRE0 to XRE3 of the corresponding redundant enable circuit XRE become high levels. At this time, each redundant enable circuit has a corresponding complementary internal address signal. , And , or It acts as one kind of address comparison circuit by being selectively delivered on the condition that the corresponding fuse means is not disconnected. The output signals of these redundant address comparison circuits are supplied to the gates of the slave MOSFETs provided in series between the corresponding coincidence detection node and the ground potential of the circuit as described above.

The pair of coincidence detection nodes of the X-based redundant circuit are also coupled to the input terminals of the corresponding NOR gate circuit. The output terminal of the NOR gate circuit is inverted and then the corresponding redundancy word line selection signal It becomes

Reverse long word line selection signal Is supplied to the redundant word line selection drive signal generation circuit PRWD and simultaneously supplied to the corresponding input terminal of the four-input NAND gate circuit to form the internal control signal XR. The internal control signal XR is any redundant word line selection signal. Becomes low level, i.e., when any redundant word line is selected, the high level is selectively selected. For example, formation of word line selection drive signals X00 to X11 in the word line selection drive signal generation circuit PWD is selectively selected. Used to stop.

On the other hand, the output signals XRE0 to XRE3 of the redundant enable circuit XRE of each X-based redundant circuit are not particularly limited, but are also supplied to corresponding input terminals of the four-input NOR gate circuit to be used to form the internal control signal SIGX. This internal control signal SIGX is inverted internal control signal as shown in FIG. Is output from the address input terminal A5 as a so-called symbol signal indicating which redundant word line is in use, provided that the high level is supplied to the address input terminal A4.

The X series redundant circuits XR0 to XR3 are inverted internal control signals. Has a so-called fuse inspection function for testing the disconnection of fuse means, etc., provided in each redundant address bridge when it is at a low level.

The word line drive signal generation circuit? XG includes a boost capacitor CB for forming a drive signal of boost level as shown in FIG.

This boost amount CB is precharged so that when the pseudostatic RAM is in the non-selected state, the electrode on the right thereof is at the high level as the power supply voltage of the circuit, and at the same time, the electrode on the left is at the low level as the ground potential of the circuit.

And an inverted timing signal when the pseudostatic RAM is selected. And The electrode on the left becomes high level at the timing when both of them become low level. As a result, the electrode on the right rises to a boost level higher than the power supply voltage of the circuit, whereby the word line drive signal? X of the boost level is selectively formed.

The word line drive signal øx is supplied to the word line select drive signal generation circuit PWD and the redundant word line select drive signal generation circuit PRWD, and is selectively transmitted as a word line select drive signal X00 to X11 or a redundant word line select drive signal XR0 to XR3. do.

By the way, the number of memory arrays which are simultaneously operated in the memory access of the pseudostatic RAM of this embodiment becomes two in the normal operation mode as described above, and eight in the self regeneration mode.

Therefore, in these operating modes, the number of simultaneous selection of word lines is different, and the magnitude of the load capacity for the word line driving signal? X is different, and as a result, the boost level fluctuates. For this reason, in this pseudo-statistic RAM, the pseudo-statistic RAM is selected in the self-regeneration mode between the output terminal of the word line drive signal generation circuit øXG and the ground potential of the circuit. Is provided with a level correction capacitor Cw that is selectively coupled when the low level becomes low. This capacitor Cw is designed to have a capacitance corresponding to the difference in the number of simultaneous selection of word lines in the normal operation mode and the self-reproducing mode, that is, the load capacity for six word lines.

As shown in Fig. 21, the word line selection drive signal generation circuit PWD includes a timing signal XDP and a 3-bit complementary internal address signal for performing crowd word line selection of the upper side or the lower side array. , And By selectively transmitting the word line driving signal? X in accordance with this, a word line selection driving signal X00U, X01U, X10U or X11U or X00D, X01D, X10D or X11D of a boost level is alternatively formed. As described above, the word line selection drive signal generation circuit PWD is supplied with an internal control signal XR which is selectively at a high level when an address supplied during memory access in the X-based redundant circuit matches a bad address assigned to a redundant word line. . When this internal control signal is XR and becomes level, the operation of the word line selection drive signal generation circuit PWD is substantially stopped and the word line selection drive signal is not formed.

On the other hand, the redundant word line selection drive signal generation circuit PRDW is a reverse redundant word line selection signal corresponding to the timing signal XDP. By selectively transmitting the word line driving signal? X accordingly, redundant word line selection driving signals XR0 to XR3 of boost level are selectively formed.

As described above, the address supplied during memory access coincides with a bad address assigned to a redundant word line, so that the reverse redundant word line selection signal When any one of the low level, i.e., the redundant word line selection drive signal generation circuit PRWD becomes substantially in operation, the operation of the word line selection drive signal generation circuit PWD is substantially stopped.

The X decoders XD0L and XD0R to XD3L and XD3R each have 64 unit circuits provided corresponding to each word line group of the corresponding memory array and another unit circuit provided corresponding to four redundant word lines. These unit circuits each include four word line driving MOSFETs provided corresponding to the four word lines constituting each word line group as shown in FIG. The source of the word line driving MOSFET is coupled to the corresponding word line, and the corresponding word line selection drive signals X00 to X11 or redundant word line selection drive signals XR0 to XR3 are supplied to the drains thereof. The gate of the word line driving MOSFET is commonly coupled to the internal node N12, i.e., the output terminal of the inverter circuit N9, via a corresponding cut MOSFET.

The input terminal of the inverter circuit N9 receives the predecode signals AX450 to AX453, AX670 to AX673 and AX89 to AX893 at its gate, and is coupled to the output terminal of the inverter circuit N10 via three series MOSFETs forming a so-called decoder tree. do. The input terminal of the inverter circuit N10 has an inverted array selection signal corresponding to the X predecoder PXD. And And Is supplied. As a result, the internal note N12 corresponds to the corresponding inverted array selection signal. And the like become at the zero level, and selectively become the high level when the predecode signals are all at the high level in a corresponding combination. As a result, word selection drive signals X00 to X11, which are alternatively boost levels, are transmitted to one word line specified in the corresponding word line group, and the word lines are alternatively selected.

Although not shown in FIG. 36, when a bad address assigned to a redundant word line is specified, the redundant level of the redundant word line selection drive signals XR0 to XR3 corresponds to the redundant word line WR0 regardless of the predecode signal. To WR3.

The Y address buffer YAB has eight unit circuits provided corresponding to the address input terminals A11 to A18 as shown in FIG.

These unit circuits convert the Y address signals Y11 to Y18 transmitted through the corresponding address input terminals to invert timing signals. And And a latch circuit to be input and held in accordance with each. The output signal of each latch circuit is an inversion timing signal. Complementary internal address signal after gate control according to Is supplied to the Y predecoder PYD.

The Y predecoder PYD is a complementary internal address signal of two bits, respectively, as shown in Figs. And , And , And or And A total of 16 decoder unit circuits for receiving non-inverting and inverting signals in a predetermined combination are provided. The output signals of these decoder unit circuits are supplied to the respective Y decoders as the predecode signals AY120 to AY123, AY340 to AY343, AY560 to AY563, or AY780 to AY783.

However, the 16 signal lines which transmit the predecode signals AY120 to AY123, AY340 to AY343, AY560 to AY563, and AY780 to AY783 have relatively narrow places according to the Y decoders YD0 to YD3 arranged between the two memory arrays forming the pair. It is arranged over a relatively long distance. In these areas, eight signal lines for transmitting redundant word line selection signals YR0 to YR7 output from the Y redundant circuit YRAC to each Y decoder need to be arranged. However, there is no reason for the arrangement.

For this reason, in the pseudo-static RAM of this embodiment, eight signal lines for transmitting the predecode signals AY560 to AY563 and AY780 to AY783 as shown in Figs. 24 and 25 are shared as signal lines for the redundant data line selection signal. Doing. That is, the eight decoder unit circuits corresponding to these predecode signals are inverted timing signals. Multiplexers are respectively provided as the gate control signal.

Inverted timing signal here As described below, when the bad addresses allocated to the Y address signals Y11 to Y18 supplied at the time of memory access and any one of the eight redundant data line groups match, the low level is selectively lowered. At this time, the multiplexer of each decoder unit circuit selects the corresponding redundant data line selection signals YR0 to YR7 and transfers them to each decoder. On the other hand, these addresses do not match and the inversion timing signal When the high level is reached, the multiplexer of each decoder unit circuit selects the corresponding predecode signals AY560 to AY563 and AY780 to AY783 and transfers them to the Y decoder. As a result, by simply adding one signal line for transmitting the timing signal? Yr for gate control to each Y decoder, eight signal lines can be realized equivalently and the chip area of the pseudostatic RAM can be reduced.

On the other hand, the predecode signals AY120 to AY123, AY340 to AY343, AY560 to AY563, and AY780 to AY783 are gate-controlled by a selection signal shown by a * mark in Figs. 23 to 25, i.e., AX1U or AX1UY, and then to the drive circuit. It is transferred to the corresponding Y decoder via three actuating inverter circuits. In this embodiment, the NAND gate circuit and the three-stage inverter circuit for executing the gate control are disposed close to the corresponding Y decoder as shown in FIG. As a result, the delay time of the signal transmission circuit related to the predecode signal is shortened.

As described above, the pseudostatic RAM has 32 sets of redundant complementary data lines for each memory array. And four sets of these redundant complementary data ships, that is, eight Y redundant circuits YRAC0 to YRAC7 correspondingly provided for each redundant redundant data line group. These Y redundant circuits include one redundant enable circuit YRE and a complementary internal address signal as shown in FIG. And eight redundant address comparison circuits provided corresponding to each bit. These redundant enable circuits and redundant address comparison circuits work similarly to the X-based redundant circuits described above to selectively set the output signals, that is, redundant data line selection signals YR0 to YR7, to a high level.

That is, the redundant enable circuit YRE of each Y-based redundant circuit includes fuse means selectively cut off when the corresponding Y-based redundant circuit becomes valid, that is, when a bad address is assigned to the corresponding redundant data line group. By cutting off the fuse means, the output signals YRE0 to YRE7 are set to high level. On the other hand, the eight redundant address comparison circuits of each Y-based redundant circuit include two fuse means selectively cut by the corresponding bit of the bad address assigned to the corresponding redundant data line group being logical 0 or logical 1; The corresponding bits of the defective address are stored by cutting these fuse means. Further, the output signal YRE0 to YRE7 of the corresponding redundant enable circuit is selectively operated on the condition that the output signal is high level, and the Y address signals Y11 to Y18 supplied during the defective address and memory access, that is, the complementary internal address signal. Compare and match the corresponding bits in. As a result, the output signal is selectively set to a high level when both bits coincide.

The output signal of the redundant address comparison circuit is supplied to the gates of the eight subordinate MOSFETs provided in series between the predetermined detection node and the ground potential of the circuit. Then, provided that the output signals of the eight redundant address comparison circuits are all at a high level, that is, the defective addresses held in each Y redundant circuit and the Y address signals Y11 to Y18 supplied during memory access coincide with all bits. The detection node is optionally at a low level. The level of the detection node is the redundancy data line selection signal YR0 to YR7 and the inversion redundancy data line selection signal through the inverter circuit. It becomes

That is, the Y redundant circuit YRAC0 to YRAC7 acts as a bad address ROM which holds a bad address assigned to the corresponding redundant data line group and a Y address signal Y11 supplied at the time of accessing these bad addresses and memory. Y18, i.e., complementary internal address signal It acts as a redundancy address comparison church that compares bit by bit. And, corresponding bad address and complementary internal address signal The output signal, that is, the redundant data line selection signal YR0 to YR7 is selectively set to a high level on the condition that all bits match, and the reverse redundant data line selection signal is selected. Selectively low level.

The redundant data line selection signals YR0 to YR7 are supplied to the respective Y decoders via the Y predecoder PYD as described above. In addition, the reverse redundant data line selection signal Is substantially supplied to the corresponding input terminal of the eight-input negative logic circuit to supply the inversion timing signal. Used to form. Of course inversion timing signal Which redundant data line selection signal Becomes low level selectively, i.e., when a redundant data group is selected. Reverse timing signal After the gate is controlled by the timing signal? Yed, the signal becomes the timing signal? Yr. As described above, the non-inverting and inverting timing signals? Yr are used as the multiplexer control signals of the Y predecoder PYD, and at the same time, are the switching control signals of the complementary data line or redundant complementary data line selection operation in the Y predecoder PYD.

On the other hand, the output signals YRE0 to YRE7 of the redundant enable circuit YRE of each Y redundant circuit are not particularly limited, but are also supplied to corresponding input terminals of the logical sum circuit of eight inputs to be used to form the internal control signal SIGY. Of course, the internal control signal SIGY is selectively at a high level when the output signals YRE0 to YRE7 of the redundant enable circuit YRE are at a high level, that is, when a bad address is assigned to any redundant data line group. Like the above internal control signal SIGX, the internal control signal SIGY is output from the address input terminal A5 as a so-called symbol signal when a predetermined high voltage is supplied to the address input terminal A4.

Y-based redundant circuits YRAC0 to YRAC7 are inverted internal control signals. Has a so-called fuse inspection function for testing the partial disconnection of the fuse means provided in each redundant address comparison circuit. Y decoders YD0 to YD3 are 256 unit circuits corresponding to four sets of complementary data lines of corresponding left and right pairs of memory arrays and four sets of redundant complementary data lines, that is, eight units provided corresponding to redundant redundant data groups. Each has a circuit. As shown in FIG. 37, the unit circuit provided corresponding to the four sets of complementary data lines includes a power supply voltage of a detection node and a circuit or a corresponding inverted Y decoder control signal. or , In other words or It includes several P-channel and N-channel MOSFETs each provided in parallel or in series. These MOSFETs constitute one NAND gate circuit by supplying predecode signals AY120 to AY123, AY340 to AY343, AY560 to AY563, and AY780 to AY783 to their gates in corresponding combinations. Therefore, the detection node of each unit circuit is selectively low level provided that the corresponding inverted Y decoder control signal becomes low level and at the same time all the corresponding predecode signals become high level. As a result, the corresponding data line selection signals YS0 to YS255 are alternatively at a high level, and the corresponding four sets of complementary data lines are brought into a selection state. Further, when the redundant data line selection signals YR0 to YR7 are transmitted through the predecode signal lines AY560 to AY563 and AY780 to AY783, the predecode signals AY340 to AY343 are all at a low level. For this reason, the data line selection signals for selecting normal complementary data lines are all at a low level.

On the other hand, the four unit circuits provided corresponding to each redundant data line group are not particularly limited, but the predecode signals AY560 to AY563 or AY780 to AY783 corresponding to the timing signal? Yr as shown in FIG. And two input NAND gate circuits receiving selection signals YR0 to YR7, respectively. The output signals of these NAND gate circuits are selectively at a low level when the corresponding inverted Y decoder control signal is at a low level and at the same time when the timing signal? Yr and the corresponding redundant data line selection signals YR0 to YR7 are at a high level. As a result, the corresponding redundant data line selection signals RYS0 to RYS7 are alternatively at a high level, and the corresponding four redundant redundant table lines are selected.

The data input buffer DIB has eight unit circuits provided corresponding to the data input / output terminals IO0 to IO7. The input terminals of these unit circuits are coupled to the corresponding data input / output terminals IO0 to IO7 as shown in FIG. On the other hand, the output terminals of the first to fourth unit circuits corresponding to the data input / output terminals IO0 to IO3 of the data input buffer DIB are commonly coupled to the corresponding unit circuits of the adjacent write circuits DILL and DIRL, respectively, and the data input / output terminals IO4 to The output terminals of the fifth to eighth unit circuits corresponding to IO7 are commonly coupled to the input terminals of the corresponding unit circuits of DILR and DIRR, respectively.

As shown in FIG. 29, each unit circuit of the data input buffer DIB has an inverted timing signal that becomes low at a predetermined timing when the pseudo-static RAM becomes an operation cycle of the write system. In accordance with this, the write data supplied via the corresponding data input / output terminals IO0 to IO7 is inputted and transferred to the corresponding unit circuits of the corresponding write circuits DILL and DIRL or DILR and DIRR.

As shown in FIG. 29, the write circuit DILL has four unit circuits which are commonly provided corresponding to the common I / O lines of the two memory arrays MARY0L and MARY0R. These unit circuits are complementary light signals based on the light signals transmitted from the first to fourth unit circuits of the data input buffer DIB. , In other words Form each. These complementary write signals are selected by the write selection circuit WS, provided that the corresponding write select signal WS0L or WSOR is at a high level, as shown in FIG. 30, to four sets of common I / O lines of the memory array MARY0L or MARY0R. Delivered.

Similarly, the write circuit DIRL has four unit circuits which are provided in common corresponding to each common I / O line of the memory arrays MARY1L and MARY1R. These unit circuits form complementary light signals DI10B to DI13B based on the light signals transmitted from the unit circuits of the first to fourth unit circuits of the data input buffer DIB.

These complementary light signals are selectively transmitted to four sets of common I / O lines of the memory array MARY0L or MARY0R, provided that the corresponding write selection signal WS1L or WS1R is at a high level.

On the other hand, the write circuit DILR has four unit circuits which are provided in common corresponding to each common I / O line of the memory arrays MARY2L and MARY2R. These unit circuits are complementary light signals based on the light signals transmitted from the fifth to eighth unit circuits of the data input buffer DIB. Form each. These complementary light signals are selectively transmitted to four sets of common I / O lines of the memory array MARY2L or MARY2R provided that the corresponding light selection signal WS2L or WS2R is at a high level.

Similarly, the write circuit DIRR has four unit circuits which are provided in common corresponding to each common I / O line of the memory arrays MARY3L and MARY3R. These unit circuits are complementary based on the light signals transmitted from the fifth to eighth unit circuits of the data input buffer DIB. Form each. These complementary light signals are selectively transmitted to four sets of common I / O lines of the memory array MARY3L or MARY3R, provided that the corresponding light selection signal WS3L or WS3R becomes high level.

As shown in FIG. 27, the main amplifier MALL includes four unit circuits provided corresponding to the common I / O lines of the memory arrays MARY0L and MARYOR. These unit circuits each have two sets of input terminals and one set of output terminals. One of the input terminals of each unit circuit is the corresponding common I / O line of the memory array MARY0L. , In other words Respectively coupled to the corresponding common I / O line of the memory array MARY0R. , In other words Are coupled to each.

These input terminals have corresponding inverted array selection signals. or Complementary internal node of the corresponding unit circuit by _ becoming low level , In other words Is optionally coupled to. The output terminal of each unit circuit of the main amplifier MALL is coupled to the input terminals of the first to fourth unit circuits of the data output buffer DOB via the output selection circuit OSL. The main amplifier MALL is the complementary inner node And two pairs of static amplifier circuits provided substantially in series between the output terminal and the output terminal thereof, and are selectively operated in accordance with the corresponding timing symbol? Ma0.

Similarly, the main amplifier MARL includes four unit circuits provided corresponding to each common I / O line of the memory arrays MARY1L and MARY1R. Four pairs of input terminals of these unit circuits have corresponding common I / O lines of the memory array MARY1L or MARY1R. or The output terminal is coupled to the input terminal of the first to fourth unit circuits of the data output buffer DOB via the output selection circuit OSL. The main amplifier MARY is selectively put into operation according to the corresponding timing signal? Ma1.

On the other hand, the main amplifier MALR includes four unit circuits provided corresponding to the common I / O lines of the memory arrays MARY2L and MARY2R. Four pairs of input terminals of these unit circuits have corresponding common I / O lines of the memory array MARY2L or MARY2R. , In other words or , In other words Are respectively coupled to the input terminals of the fifth to eighth unit circuits of the data output buffer DOB via the output selection circuit OSL.

The main amplifier MARY is selectively put into operation according to the corresponding timing signal? Ma0.

Similarly, the main amplifier MARR includes four unit circuits provided corresponding to each common I / O line of the memory arrays MARY3L and MARY3R. Four pairs of input terminals of these unit circuits have corresponding common I / O lines of the memory arrays MARY3L and MARY3R. or Respectively coupled to the input terminals of the fifth to eighth unit circuits of the data output buffer DOB via the output selection circuit OSL. The main amplifier MARY is selectively put into operation according to the corresponding timing signal? Ma0.

Hereinafter, the outline and characteristics of the main amplifier of this pseudostatic RAM will be described by taking the main amplifier MALL as an example.

Each main amplifier unit circuit has two sets of common I / O lines. And Each of the three equalization MODFETs is provided between the non-inverting and inverting signal lines of the lamp. These equalizing MOSFETs are selectively turned ON when the corresponding internal control signals IOS0L, IOS0R, etc. become low level, and the non-inverting and inverting signal lines of the corresponding common I / O lines are made half-charge level HVC.

The unit circuit of each main amplifier has a corresponding common I / O line as shown in FIG. Non-inverted signal I00iL, etc. And a pair of preset MOSFETs QN23 and QN24 respectively provided between the power supply voltage of the circuit and the like. These preset MOSFETs are selectively turned ON due to the high level of the corresponding internal control signal IOU0L, so that the non-inverting and inverting signal lines of the corresponding common I / O lines are lowered by their threshold voltages from the power supply voltage of the circuit. Preset to the level. As a result, the DC level of the non-inverting and inverting signal lines of each common I / O line has a predetermined bias voltage that maximizes the sensitivity of the static amplifier circuit.

By the way, in this pseudo-static RAM, the internal control signal IOU0L is temporarily raised to a high level immediately before each main amplifier is in an operating state as shown in FIG. 48, i.e., just before the timing signal? Ma0 or the like becomes high level. As a result, the preset MOSFETs QN23, QN24, and the like are temporarily turned ON. As a result, the power consumption of the main amplifier can be reduced compared to the conventional dynamic RAM or the like in which the preset MOSFET is continuously turned on while the main amplifier is in the operating state.

As shown in FIG. 32, the output selection circuit OSL selects the 4-bit read data output from the main amplifiers MALL, MARL, MALR, and MARR in accordance with the timing signals øma0 and øma1 to correspond to the unit circuits of the data output buffer DOB. Optionally pass in

That is, the output selection circuit OSL transfers the read data output from each unit circuit of the main amplifier MALL to the first to fourth unit circuits D00 to D03 of the data output buffer DOB when the timing signal øma0 becomes high level. The read data output from each unit circuit of the main amplifier MARL is transferred to the fifth to eighth unit circuits D04 to D07 of the data output buffer DOB, respectively.

When the timing signal øma1 reaches a high level, the read data output from each unit circuit of the main amplifier MARL is transmitted to the first to fourth unit circuits D00 to D03 of the data output buffer DOB, respectively, and each unit of the main amplifier MARR. The read data output from the circuit is transferred to the fifth to eighth unit circuits D04 to D07 of the data output buffer DOB, respectively.

The data output buffer DOB has eight unit circuits D00 to D07 provided corresponding to the data input and output terminals I00 to I07. As shown in FIG. 31, the unit circuit includes a latch circuit in which input and output terminals of a pair of NAND gate circuits are cross-connected, and a timing signal? Mad provided between non-inverting and inverting input terminals of the latch circuit. A pair of precharge MOSFETs which are selectively turned ON according to the second timing signal, and an inverted timing signal for output control inverting the inverted signal of the complementary output signal of the latch circuit. And a pair of N-channel output MOSFETs each having an inverted signal of an output signal of the NAND gate circuit via a pair of CMOS NAND gate circuits for selectively transferring in accordance with the corresponding resistor. The complementary input terminal of the latch circuit has a complementary internal output signal, i.e., a lead, of the corresponding main amplifier via two pairs of MOSFETs (switch means) which are selectively turned ON according to the timing signal? Ma0 or? Ma1 (first timing signal). The data is passed. In addition, nodes in which the pair of MOSFETs are commonly coupled are respectively coupled to corresponding data input / output terminals I00 to I07.

Each unit circuit of the data output buffer DOB includes the inversion timing signal. The low level becomes substantially the operating state, and the read data transmitted from the corresponding memory amplifier via the output selection circuit OSL is sent to the corresponding data input / output terminals I00 to I07. The inversion timing signal Is high level, the output of each unit circuit of the data output buffer DOB becomes high impedance.

By the way, the data output buffer DOB of this pseudo-static RAM is a pair of N-channel MOSFETs QN3 and QN4 provided in series between the power supply voltage and the ground potential of the circuit as shown in Figs. 29 and 49 and a and b. Is the output MOSFET. Therefore, when read data is sent to the high level from the corresponding unit circuit, as the level of the corresponding data input / output terminals I00 to I07 increases, the voltage between the gate and the source of the output MOSFET QN3 decreases, and the output operation is equivalent. Late.

In order to cope with this, in this embodiment, as shown in Fig. 49A, the timing signal CE3D (at the third input terminal of the NAND gate circuit NAG2 (second CMOS is a regate circuit) constituting the latch circuit. The latch circuit is preset by inputting a third timing signal). That is, the timing signal CE3D is normally at a low level as shown in Fig. 49C, and the inverted timing signal when the pseudostatic RAM is in the selected state. It is temporarily raised to include a high level. For this reason, when the pseudo-statistic RAM becomes non-selected and the timing signal CE3D becomes low level, the latch circuit is preset to logic 1, that is, a high level output state, and the timing signal CE3D becomes low level to read data. The latch state is accordingly.

As a result, the data output buffer DOB enters the high level output state once regardless of the read data at the start of the output operation, and subsequently executes the output operation according to the read data. As a result, the high level output operation of the data output buffer DOB is equivalently increased.

The timing generating circuit TG is not particularly limited. System timing generation circuit CE, System timing generation circuit WE, System timing generation circuit OE, word line clear circuit WC, and precharge control circuit PC. double The system timing generation circuit OE It also acts as a timing generating circuit for the system, i.e., for playback control. Hereinafter, the outline and characteristics of each part of the timing generation circuit TG of the pseudostatic RAM will be described.

The system timing generation circuit CE has a chip enable signal as shown in FIG. Pad to enter And an input circuit provided correspondingly. Chip enable signal input through this input circuit First, the inverted timing signal To one input terminal of the two-input NAND gate circuit. An inverted timing signal is provided to the other input terminal of the NAND gate circuit. The output signal is supplied with a plurality of inverted timing signals for which the pseudostatic RAM advances through a predetermined number of logic gate circuits. , And Etc. are formed sequentially.

Here, the inversion timing signal Is an inverted timing signal When any one of them becomes low level, it is selectively low level, and the inversion timing signal Returns to the high level as it becomes the low level. The inversion timing signal As described below, the pseudo-static RAM temporarily goes to the low level at the beginning of the self-regeneration mode, and the reverse timing signal After the pseudostatic RAM enters the self-regeneration mode, each time a predetermined regeneration period has elapsed, the level becomes temporarily low. In addition, the inversion timing signal Becomes low level temporarily at the beginning of the pseudostatic RAM in the automatic regeneration mode. This allows the pseudo-static RAM to use the chip enable signal. The low level causes the pseudo-static RAM to be selected, or when the pseudo-static RAM is automatically or self-regenerating and the pseudo-static RAM is in the self-renewal mode, and each time a predetermined regeneration period has elapsed. The inversion timing signal A series of operations controlled by the above is started. Reverse timing signal And Substantially forms timing signals? X1s and? Y1s for inputting the X address signal and the Y address signal through a two-input NAND gate circuit constituting the negative logic circuit and a predetermined number of inverter circuits.

Inverse timing signal Is inverted and supplied to one input terminal of the two-input NAND gate circuit. The inverted timing signal is provided to the other input terminal of the NAND gate circuit. The inverted delay signal is supplied, and the output signal forms a plurality of timing signals P1, P2, P3, P4 and the like for controlling the sense amplifier of the pseudo-static RAM through a predetermined number of logic gate circuits. These timing signals are inverted timing signals. And After all of these low levels have elapsed, a predetermined delay time elapses, which is effective, that is, they are sequentially changed to high levels. Is returned to the high level, which is invalid, i.e., returns to the low level sequentially.

Inverse timing signal Is inverted and combined with the timing signal? X1s, and sequentially forms timing signals P1D, P2D, and the like for controlling the sense amplifier of the pseudo-static RAM through a predetermined number of logic gate circuits. In addition, the inversion timing signal And inverted timing signals Inverted timing signal for activating the data input / output circuit at a high level, i.e., the pseudo-statistic RAM is not in the regeneration mode. And timing signals? Ys and the like.

The timing signal P1 is an inversion timing signal. The timing signals P1A to P1C are sequentially formed by passing through a predetermined number of logic gate circuits, provided that this high level, i.e., the pseudo-static RAM is in the self-regeneration mode.

These timing signals P1 to P4, P1D, P2D, and P1A to P1C are supplied to the sense amplifier driving circuits SP and SN as described above, whereby a timing signal for turning on the various sense amplifier driving MOSFETs is predetermined. Formed with conditions.

The system timing generation circuit WE has a write enable signal as shown in FIG. Pad to enter And an input circuit provided correspondingly. The write enable signal input through this input circuit First, the inverted timing signal Inverted timing signal after and negative logic sum is taken To form. Further, after the logical signal P1 is taken as the logical product, the timing signal WE0 and WE for the write control and the inversion timing signal , And To form.

Wherein the inversion timing signal Is an inverted timing signal And Becomes low level at all, i.e., when the pseudo-static RAM enters the regeneration mode and when a predetermined high voltage is supplied to the pad W, i.e., when the pseudo-static RAM goes to the above-described Rcc test mode, it is selectively low level.

As such, the write enable signal The low timing when the pseudo-static RAM becomes the light cycle operation cycle or when the pseudo-static RAM enters the Rcc test mode. Becomes low level, and 8-bit write data supplied via the data input / output terminals I00 to I07 is input to the corresponding unit circuit of the data input buffer DIB. These write data are inverted timing signals. The lowering of the back light causes the light to be transmitted through the corresponding write circuit and written to all eight selected memory cells.

The system timing generation circuit OE is not particularly limited but as shown in FIG. 14, the output enable signal. Ie playback control signal And an input circuit provided correspondingly. Output enable signal input through this input circuit Becomes the timing signal OE0 and is combined with the timing signal P2D, thereby inverting the timing signal for output control. To form. 2 reverse timing signal Is supplied to the data output buffer DOB and used for output data read control. The timing signal OE0 is an inverted timing signal. Provided that this level is high, that is, the chip enable signal Is transmitted via the latch circuit provided that the signal is at a high level, thereby inverting the timing signal. This level becomes low. Reverse timing signal Are sequentially transmitted through a predetermined delay circuit, and as a result, the timing signal RF1 first becomes a high level and slightly delays the inversion timing signal. Becomes low level.

Timing signal RF1 and inverted timing signal Is the inversion timing signal. In combination with the inverse timing signal To form.

Reverse timing signal Is a chip enable signal Enable signal with high level Play enable signal Becomes low level temporarily, i.e., at the beginning of the pseudo-static RAM in the automatic regeneration mode, the level is temporarily low.

In the pseudo-statistic RAM, the internal timing signal RF1 becomes high level, so that the internal control signal ENB becomes high level and the regeneration timer circuit TMR is activated. Accordingly, the timing signal øtmr and the inversion timing signal And timing signal? C1 is formed at a predetermined cycle. Among these, the timing signal? C1 is counted by the regeneration timer counter circuit SRC, and its output signal, i.e., the internal timing signal SCA7, is an inverted timing signal. The cycle is repeated at a predetermined number of times the period of to become a high level temporarily.

On the other hand, the inversion timing signal Is an inverted timing signal And Is transmitted under the condition of being at a high level together with the inversion timing signal. Inverted timing signal at the time of reaching this low level To low level. In other words, the inversion timing signal Is the inversion timing signal Output enable signal Inverted timing signal The low level is continuously set beyond the period of to become a low level, which is an internal control signal for specifying the self regeneration mode.

Reverse timing signal Is the inversion timing signal Inverted signals, i.e., non-inverted timing signals RF0 and inverted timing signals The logical product signal and the negative logic sum are taken and transferred to the latch circuit which is gate-controlled in accordance with the timing signal? X1s. As described above, the output signal of the latch circuit is an inversion timing signal for inputting the output signal of the reproduction counter RFC in the x address buffer XAB, that is, the reproduction address signals AR0 to AR10. It becomes That is, this inversion timing signal When the pseudo-static RAM enters the automatic regeneration or self regeneration mode, the low level is reached when the timing signal? X1s becomes a high level.

Reverse timing signal The inverted timing signal is also supplied to the one short circuit in which the NAND gate circuit, the inverter circuit, and the predetermined delay circuit DL are combined. To form. Inverted timing signal Is an inverted timing signal This low level, i.e., becomes low temporarily at the beginning when the self-renewal mode of the pseudostatic RAM is identified, and thus the inversion timing signal. This is one cause of making the low level.

On the other hand, the timing signal? C1 formed by the regeneration timer circuit TMR at a predetermined period is taken as the logical product of the output signal SCA7 of the regeneration timer counter circuit SRC, and then the timing signal RF1 is at a high level, that is, the regeneration control signal. Is transmitted under the condition that the signal is at a low level, and the reverse timing signal It becomes Further, the AND signal forms an internal control signal LOAD for presetting the regeneration timer counter circuit SRC, and at the same time, the inversion timer signal. The internal control signal FSET for setting the fuse circuit is formed under the condition that the level is high. The inversion timing signal Is the inversion timing signal described above. Like the reverse timing signal This is one cause of making the low level.

The regeneration timer circuit TMR includes seven inverter circuits and a capacitor C1 substantially in series as shown in FIG.

Four of these inverter circuits act as one delay circuit DL as shown in the 53rd, and the inversion signal of the output signal is fed back to the gate of the P-channel MOSFET QP3 constituting the leading inverter circuit. It consists of two ring oscillators. Capacitor C1 is occupied by the MOSFET QP3DL being turned on, and discharged via N-channel MOSFET QN1 (first MOSFET) when MOSFET QP3 is turned off. At this time, the discharge current flowing through the MOSFET QN1 is set by the constant current source including the MOSFET QN1 and the N-channel MOSFET QN2 (second MOSFET) in the form of a current mirror.

The charge potential of the capacitor C1 is monitored by a later inverter circuit including the N-channel MOSFET QN7. This inverter circuit acts as a so-called level determination circuit, and the logic threshold level thereof, together with the MOSFET QN7, is the P-channel MOSFET QP5 constituting the level determination circuit, in the form of a current mirror with the P-channel MOSFET QP4 constituting the constant current source. This results in approximately the threshold voltage V _THN of MOSFET QN7 itself. Thus, MOSFET QN7 is turned on when the charge potential of capacitor C1 is higher than the logic threshold level, and turned off when low. As a result, the seven inverter circuits function as one ring oscillator, and the oscillation frequency is set according to the magnitude of the discharge current flowing through the MOSFET QN1.

The constant current source comprising MOSFETs QP4 and QN2 also includes a resistor R1 provided between these MOSFETs. This resistor R1 has a relatively long distance by having polysilicon on an insulating layer formed of SiO ₂ on the surface of a P-type semiconductor substrate as shown in FIG. 53B and requiring a relatively large resistance value. It is formed through. Therefore, a relatively large substrate capacitance is equivalently coupled between the polycrystalline silicon layer and the P-type semiconductor substrate, whereby the characteristics of the regenerated timer circuit TMR fluctuate under the influence of a power supply bump or the like.

In order to cope with this, in this pseudo-static RAM, as shown in Fig. 53B, the power supply voltage (first power supply voltage) of the circuit is located below the portion corresponding to 1/2 of the polysilicon layer constituting the resistor R1. ) Form a first N well region NW1 coupled to), and a second N well region NW2 coupled to the ground potential (second power supply voltage) of the circuit at a lower layer corresponding to the other half. have. Since the substrate capacitances having approximately the same capacitance are equivalently coupled between these well regions and the polysilicon layers constituting the resistor R1, the sudden fluctuation in the power supply voltage caused by the power supply pad or the like is canceled by this. As a result, the regeneration timer circuit TMR has a stable regeneration period.

On the other hand, the regeneration timer circuit TMR having the above circuit configuration has another problem regarding power supply bumps. That is, the capacitor C1 is charged to a predetermined high level based on the power supply voltage of the circuit by turning on the MOSFET QP3 as described above, and discharged through the MOSFET QN1 by turning off the MOSFET QP3. At this time, the value of the discharge current flowing through the MOSFET QN1 is also set by the constant current source with reference to the power supply voltage of the circuit. For this reason, for example, when a power supply bump or the like occurs in the power supply voltage of the circuit while the MOSFET QP3 is in the OFF state, only the reference voltage for setting the discharge current is varied, which results in the characteristics of the regenerated timer circuit TMR. This fluctuates.

In order to cope with this, for example, as shown in FIG. 54A, an N-channel MOSFET QN15 (seventh MOSFET) is provided between the MOSFET QP4 constituting the constant current source and the resistor R1, and the gate potential is defined as the above. When the MOSFET QP3 (fifth MOSFET) is turned OFF, a method of setting by the capacitor C2 (second capacitor) to be in a floating state similarly to the capacitor C1 (first capacitor) is considered.

That is, one electrode of the capacitor C2, i.e., the internal node N4 (second internal node) has the P-channel MOSFETs QP9 to QP11 and N because the P-channel MOSFET QP8 (the sixth MOSFET) is turned on at the same time as the MOSFET QP3. The output voltage V ₁ of the constant voltage source, which is the channel MOSFETs QN12 to QN14, is occupied. The charge potential of the internal node N4 is supplied to the gate of the charge potential MOSFET QN15 of the MOSFET QN15 and becomes a reference potential for setting the value of the discharge current, and is also supplied to the gate of the N-channel MOSFET QN16 to supply the charge potential of the capacitor C1. It becomes the reference potential for setting. The charge potential MOSFET QP8 of the capacitor C2 is turned off at the same time as the MOSFET QP3 to be floating with the MOSFET QP3 so that it is not affected by the power bumps generated therebetween. As a result, the characteristics of the regeneration timer TMR are stabilized, and the regeneration cycle of the pseudostatic RAM is further stabilized.

As shown in FIG. 14, the regeneration timer counter circuit SRC has an 8-bit binary counter composed of eight counter circuits, SCNTRs, in series. These unit counter circuits SCNTR are formed by cross-connecting two CMOS inverter circuits, respectively, as illustrated in FIG. 16. Substantially, the series coupling degree in a ring shape includes a pair of main latches and slave latches, respectively. Each unit counter circuit and SCNTR each include a fuse circuit similar to that included in the X-based redundant circuit or the like for setting the count initial value in accordance with the internal control signal FSET. These unit counter circuits SCNTR execute the advancing operation in accordance with the output signal of the regeneration timer circuit TMR, that is, the timing signal? C1 and the carry output signal SCA _{j_1} of the previous unit counter circuit, and perform the output signal, that is, the carry output signal SCA _j . Form. In addition, the timing signal RF1 is supplied as the start control signal of the regeneration timer counter circuit SRC to the unit counter circuit SCNTR of the first bit instead of the carry output signal of the preceding circuit.

The carry output signal SCA7 of the unit counter circuit SCNTR of the last bit becomes the output signal of the regeneration timer counter circuit SRC and is combined with the timing signal? C1 as described above to invert the timing signal for starting the self regeneration cycle. Used to form.

The word line clear circuit WC has a complementary internal address signal as shown in FIG. , And Based on this, the timing signals WC0U to WC3U or WC0D to WC3D for word line clear control are selectively formed. These timing signals become the normal level, and when the complementary internal address signals become the low level or the high level in a corresponding combination, they become the high level. As a result, the word line clear MOSFET provided between all the word lines of each memory array and the ground potential of the circuit is selectively turned OFF so that the corresponding word lines are released from the clear state. The precharge control circuit PC is a reverse timing signal. , And Various control signals for precharging each part of the pseudostatic RAM are formed on the basis of the back and the like. In addition, the inversion Y decoder control signal for selectively operating the Y decoder by combining the internal address signals AX0 and AX1 again. And the like selectively.

The pseudostatic RAM is provided with several voltage generating circuits HVC, VB and VL which form various internal voltages based on the power supply voltage V _CC of the circuit, for example, + 5V.

The voltage generating circuit HVC drops the power supply voltage V _CC of the circuit as shown in FIG. 43 to form the internal voltage HVC which becomes a potential of approximately 1/2. This internal voltage HVC is supplied to each equalization circuit as a so-called half precharge potential.

The voltage generation circuit HVC uses the inverted internal control signal described below. When the low level is reached, the operation is selectively stopped, whereby the standby current of the pseudostatic RAM is reduced.

By the way, in the voltage generation circuit HVC, as shown in FIG. 55B, the P-channel type provided substantially in series between the power supply voltage (first power supply voltage) and the ground potential (second power supply voltage) of the circuit ( The output potential, that is, the internal voltage HVC is set by the conductance ratio of the MOSFET QP12 (the tenth MOSFET) of the first conductive type and the MOSFET QN18 (the thirteenth MOSFET) of the N-channel type (second conductive type). . Then, an N-channel MOSFET QN19 (14th MOSFET) and a P-channel MOSFET QP14 (15th MOSFET) for output are provided, and the N-channel MOSFET QN17 (eleventh MOSFET) and the P-channel which are in the form of current mirrors with these MOSFETs are provided. The MOSFET QP13 (12th MOSFET) is provided between the internal node N5 (third internal node) and the MOSFET QP12 or QN18 to control the fluctuation of the internal voltage HVC according to the fluctuation of the output current. In this case, the conductances gm19 and gm14 of the output MOSFETs QN19 and QP14 correspond to the conductances gm17 and gm13 of the corresponding MOSFETs QN17 and QP13.

gm19〉 gm17

gm14〉 gm13

It is necessary to be. However, the conductance of such output MOSFETs QN19 and QP14 becomes large, and only a relatively large through current flows through these output MOSFETs. To cope with this, the threshold voltages V _THN 19 and V _THP 14 of the output MOSFETs QN19 and QP14 are compared to the thresholds V _THN 17 and V _THP 13 of the corresponding MOSFETs QN17 and QP13.

V _THN 19 + V _THP 14〉 V _THN 17 + V _THP 13

The gate length is set so that the through current is prevented.

However, the setting of the threshold voltage by the gate length is susceptible to variation by the process and cannot completely prevent the through current. In addition, as the through current is stopped, a dead band of the internal voltage HVC is generated, and the level control becomes difficult.

In order to cope with this, first, as shown in Fig. 55B, a method of commonly coupling the well region of the MOSFET QP13 to its drain is considered. That is, the MOSFET QP13 has a low substrate voltage threshold voltage V _THP13 due to the common coupling of the well region and the drain thereof.

V _THP 14〉 V _THP 13

Phosphorus relationship is easily obtained. Therefore, the above conditions can be easily realized without being subject to process variation.

On the other hand, for the dead band of the internal voltage HVC, another pair of N-channel MOSFETs QN20 (16th MOSFET) and P-channel having relatively small conductance in parallel with the output MOSFETs QN19 and QP14 as shown in Fig. 55A. A method of providing a MOSFET QP15 (17th MOSFET) and controlling the current flowing through the MOSFETs QN17, QP13, and the like is considered. That is, when these MOSFETs are added, the current I ₁ flowing through the MOSFETs QN17 and QP13 sets the conductances of the MOSFETs QN20 and QP15 to gm20 and gm15, respectively, and the current flowing through these MOSFETs to I ₂ ,

It becomes As a result, by setting the conductance ratio of these MOSFETs, the current I ₁ flowing through the MOSFETs QN17 and QP13 can be controlled relatively easily. As a result, the through-currents of the output MOSFETs QN19 and QP14 can be controlled without causing the internal voltage HVC to become deadband.

The voltage generating circuit VBBG forms, for example, a substrate back bias voltage VBB which becomes a predetermined negative voltage based on the power supply voltage Vcc of the circuit and supplies it to the semiconductor substrate of the pseudostatic RAM.

Although the voltage generating circuit VBBG is not particularly limited, as shown in FIG. 33, a predetermined substrate is formed in accordance with the oscillation circuit OSC1 formed by substantially combining five logic gate circuits in series in a ring shape and the pulse signal output from the oscillation circuit OSC1. A charge pump circuit VG1 for forming the back bias voltage VBB is provided, and a level detection circuit LVM for selectively operating the oscillation circuit OSC1 is provided by monitoring the level of the substrate back bias voltage VBB. The voltage generating circuit VBB further comprises a charge pump circuit VG2 which forms a predetermined substrate back bias voltage VBB in accordance with an oscillation circuit OSC2 formed of substantially nine inverter circuits connected in series in a ring shape and a pulse signal output from the oscillation circuit OSC2. Prepare.

The level detection circuit LVM is not particularly limited but includes four P-channel MOSFETs and three N-channel MOSFETs arranged in series between the circuit supply voltage and the substrate back bias voltage supply point VBB.

These series MOSFETs are inverted internal control circuits. And inverted timing signals The level of the substrate back bias voltage VBB is monitored under the condition that the signal is at a high level together. As a result, when the absolute value of the substrate back bias voltage VBB exceeds a predetermined value, the inversion timing signal The output signal VB1 of the level detection circuit LVM is selectively set to low level, provided that is high level.

Reverse timing signal When the low level, i.e., the pseudo-statistic RAM goes into the self-regeneration mode, the monitoring operation of the level detection circuit LVM is stopped, and the oscillation circuit OSC1 performs the inversion timing signal. The low level, i.e., the pseudo-statistic RAM is selectively operated on the condition that it becomes an operating state in the self-regeneration cycle. At this time, the oscillation circuit OSC2 is normally operated. As a result, the through current is prevented by the level detection circuit LVM in the self regeneration mode, and the power consumption of the self regeneration mode of the pseudostatic RAM is reduced.

Inverse timing signal When the low level, i.e., the pseudo-statistic RAM is selected, the oscillation circuit OSC1 enters the operating state regardless of the output of the level detection circuit LVM. As a result, the lowering of the substrate back bias voltage VBB is prevented in the operating state of the pseudostatic RAM. Inverted internal control signal When the power supply voltage of the circuit is supplied to the pad ICT at a low level, that is to be described later, the level detection request LVM and the oscillator circuit OSC1 are unconditionally stopped, and the oscillator circuit OSC2 is brought into an operating state. As a result, the standby current of the pseudo-static RAM can be reduced in a predetermined probe test or the like to confirm the leakage current or the like.

The charge pump circuit VG1 has a boost capacitor C1, and forms a predetermined substrate back bias voltage VBB by the charge pump action of the boost capacitor C1.

The charge pump circuit VG1 is designed so that the boost capacitance C1 has a relatively large capacitance, and thus has a relatively large current supply capability. Similarly, the charge pump circuit VG2 has a boost capacitor C2, and forms a predetermined substrate back bias voltage VBB by the charge pump action of the boost capacitor C2. The charge pump circuit VG2 has a relatively small current supply capability because the boost capacitance C2 is designed to have a relatively small capacitance.

However, in the voltage generating circuit VBBG of the pseudostatic RAM, the following studies have been conducted as a method of reducing the operating current of the oscillating circuit OSC2 and the charge pump circuit VG2.

That is, as shown in FIG. 56, the oscillation circuit OSC2 basically has a ring oscillator composed of substantially nine inverter circuits coupled in series in a ring shape. These inverter circuits have very small conductance of each MOSFET, and their operating current is supplied through a P-channel or N-channel MOSFET in the form of a current mirror, and is limited to a very small value.

The output signal of the inverter circuit of the third stage of the inverter circuit constituting the oscillating circuit OSC2, that is, the pulse signal ø1 is an inverted pulse signal via the inverter which becomes the P-channel MOSFET QP7 and the N-channel MOSFET QN11. The first pulse signal is supplied to the gate of the P-channel MOSFET QP6 (third MOSFET) of the charge pump circuit VG1. The output signal of the sixth stage of the inverter circuit is supplied to the gate of the N-channel MOSFET QN8 (fourth MOSFET) of the charge pump circuit VG as the pulse signal? 2 (second pulse signal). These inverted pulse signals And pulse signal As shown in FIG. 57, the level is always in a complementary state, and also has a predetermined phase relationship in which the level is not inverted and overlapped with each other, that is, no level inversion occurs with the other level inversion interposed therebetween. .

As a result, the MOSFETs QP6 and QN8 are turned ON exclusively with each other to perform the charge pump operation by the boost capacitance C2. That is, when the MOSFETs QP6 and QN8 form a conventional CMOS inverter circuit, a certain through current flows when the corresponding pulse signal is inverted. As described above, the MOSFETs QP6 and QN8 are turned ON exclusively from each other, so that the through currents caused by these MOSFETs are completely prevented, thereby reducing the power consumption of the voltage generating circuit VBB.

The voltage generating circuit VLG forms a predetermined internal voltage VL by lowering the power supply voltage Vcc of the circuit as shown in FIG.

This internal voltage VL is used as a reference potential of a clamp circuit or the like provided in the voltage generating circuit VBB.

The voltage generation circuit VLG is the inversion internal control signal. When the low level is reached, the operation is selectively stopped, whereby the standby current of the pseudostatic RAM is reduced.

The pseudostatic RAM has an external terminal as described above. , or The test mode is selectively set to be supplied with a predetermined high voltage exceeding the power supply voltage of the circuit. The high voltage as described above is supplied to the address input terminal A4, and the symbol signal relating to the redundant circuit is sent out. For this reason, the pseudostatic RAM has four high voltage detection circuits EHG provided corresponding to these external terminals.

Each high voltage detection circuit EHG includes a plurality of MOSFETs provided in series between each of the external terminals and the ground potential of the circuit as shown in FIG. And when the high voltage is supplied to a corresponding external terminal, an output signal thereof, that is, an inverted internal control signal. Selectively low level.

These inversion internal control signals Is supplied to the corresponding test circuit or symbol circuit SG.

The ICT signal generation circuit ICTG selectively outputs its output signal, i.e., the inverted internal control signal, when the power supply voltage of the circuit is supplied to the pad ICT as shown in FIG. To low level. Inverting internal control signal when upper pad ICT is open Is fixed at a high level.

Reverse internal control signal Is supplied to the voltage generating circuits HVCG, VBBG, VLG and the like as described above, and is used to reduce the standby current of the pseudostatic RAM during a predetermined probe test.

As shown in FIG. 34, the signal generating circuit FCKG selectively outputs the output signal, i.e., the inverted internal control signal, provided that the timing signal P4 is at a high level when the power supply voltage of the circuit is supplied to the pad FCK. To low level. Inverting internal control signal when the pad FCK is opened Is fixed at a high level regardless of the timing signal P4.

Reverse internal control signal Is supplied to the X-based redundant circuit and the Y-based redundant circuit and used for identification tests such as partial disconnection of fuses.

The symbol circuit SG includes one N-channel MOSFET provided between the address input terminal A5 and the ground potential of the circuit as shown in FIG. The MOSFET has a high level of the internal control signal SIGX or SIGY outputted from the X-based redundant circuit and the Y-based redundant circuit, and at the same time, the output signal of the high voltage detection circuit EHG, that is, the inverted internal control signal. Condition is set to the low level, and the address input terminal A5 is shorted to the ground potential of the circuit.

As a result, after completion of the pseudo-static RAM, the address input terminal A5 is monitored to determine whether a bad address is assigned to the redundant word line or redundant redundant data line.

As described in the present embodiment, the following effects can be obtained by applying these inventions to semiconductor memory devices such as pseudostatic RAMs. In other words,

(1) An output buffer comprising a pair of N-channel type output MOSFETs provided in a totem pole form between a power supply voltage and a ground potential of a circuit, and a latch circuit for holding corresponding output data. Alternatively, by presetting to logic 1, an effect of selectively speeding up the output buffer during low or high level output can be obtained.

(2) an oscillation circuit comprising a capacitor and resistance means for setting the discharge current thereof, the oscillating circuit forming a predetermined pulse signal by repeating the predetermined pulse signal by repeating charging and discharging of the capacitor; A first well region coupled to the power supply voltage of the circuit is formed under the portion corresponding to approximately 1/2 of the extension direction of the polysilicon layer constituting the resistance means, and below the portion corresponding to the remaining 1/2. By forming a second well region coupled to the ground potential of the circuit, it is possible to equalize the substrate capacitance between the resistance means and the power supply voltage and the ground potential of the circuit. Thereby, the effect that the characteristic by the power supply pump etc. of the oscillation circuit contained in a regeneration timer circuit etc. can suppress a fall.

(3) It is provided between an odd number of inverter circuits and an output node and a power supply voltage or ground potential of the circuit which are substantially serially coupled to an oscillation circuit included in a substrate back bias voltage generation circuit and the like, and which is different from the inverter circuit. A pair of P-channel and N-channel MOSFETs which are turned on exclusively from each other by receiving output signals of two inverter circuits of a predetermined stage are provided, and the oscillation circuit is prevented by preventing the through current caused by these MOSFETs. The effect of reducing the power consumption of the substrate back bias voltage generation circuit is obtained.

(4) a capacitor selectively occupied via the P-channel MOSFET to be turned on in accordance with a predetermined timing signal and selectively discharged via a current mirror circuit delivering a predetermined discharge current formed by a constant current source; In the oscillation circuit, oscillation included in the regeneration timer circuit or the like, by forming the charge voltage of the capacitor and the constant current source by another capacitor which is simultaneously floated when the P-channel MOSFET is turned off. The effect of suppressing the frequency fluctuation caused by the power supply bump of the circuit can be obtained.

(5) first P-channel and N-channel MOSFETs provided in series between the power supply voltage and ground potential of the circuit, second P-channel and N-channel MOSFETs provided in parallel with these MOSFETs, and the first A voltage generating circuit comprising a second P-channel and an N-channel MOSFET provided between a P-channel and an N-channel MOSFET and a third P-channel and an N-channel MOSFET each having a current mirror type, wherein the third P-channel The common coupling between the drain of the MOSFET and the well region provides an effect of reducing the power consumption of the voltage generating circuit by controlling the penetration current through the second P-channel and N-channel MOSFETs without following process variations. Lose.

(6) The fourth P-channel and N-channel MOSFET according to the above (5), wherein the fourth P-channel and N-channel MOSFETs are formed in parallel with the second P-channel and N-channel MOSFETs and in the current mirror form. By setting the conductance ratios of these MOSFETs and the third P-channel and N-channel MOSFETs properly, the second P-channel and N-channel MOSFETs do not generate dead bands. The effect that the through current can be suppressed to reduce the power consumption of the voltage generating circuit can be obtained.

(7) The fuse circuit provided in the redundant circuit is constructed based on a fuse logic gate circuit formed by providing a fuse means between the output node and the P-channel and N-channel MOSFETs to simplify the circuit configuration of the fuse circuit. The effect of reducing the redundancy circuit and the like can be obtained.

(8) The above-mentioned (7) is provided with a pair of the fuse logic gate circuits in the fuse circuit and exclusively logically combines the output signals of these fuse logic gate circuits, for example, once cut off. Since the fuse means can be invalidated, it is possible to make flexibility in the allocation process of the defective address of the redundant circuit, thereby increasing the efficiency of the pseudostatic RAM and the like.

(9) Pseudostatic type that can be applied to both the PS reproduction mode and the VS reproduction mode in which the reproduction cycle of the pseudostatic RAM or the like is selectively switched in the PS (pseudo) reproduction or the VS (virtual) reproduction mode. The effect that RAM and the like can be efficiently developed and manufactured on the basis of a common semiconductor substrate can be obtained.

(10) The number of signal lines arranged in a relatively free space by selectively transferring several signals having different meanings depending on the operation mode, for example, through a predetermined signal line provided between the Y predecoder and the Y decoder. The effect of reducing the area required for disposing a pseudostatic RAM or the like can be reduced.

(11) The main main amplifier has a bias level at which the main amplifier is at maximum sensitivity to the non-inverting and inverting signal lines of the corresponding common I / O line when the main main amplifier coupled to the common I / O line and the main amplifier are operated. In a pseudo-static RAM including a preset MOSFET, the preset MOSFET is temporarily turned on immediately before the main amplifier is put into operation, thereby reducing its operating current to lower the power consumption of the pseudo-static RAM and the like. The effect that can be obtained is obtained.

(12) A plurality of redundant address comparison circuits and predetermined predetermined circuits which maintain corresponding bits of the bad address allocated to the corresponding redundant word line or redundant data line and compare and compare the same with the corresponding bits of the address signal supplied during memory access. A redundancy circuit comprising a plurality of subordinate MOSFETs provided in series between a detection node and a ground potential of a circuit and receiving an output signal to the redundancy address non-intersection corresponding to the gate, wherein the redundancy address comparison circuit and the subordinate MOSFET are semiconductor. Corresponding to the address input pads distributed on the substrate surface and distributedly arranged at the same time, the signal transmission delay time in the redundant circuit can be reduced, and the pseudostatic RAM and the like can be speeded up.

(13) Common I / Os, each paired and simultaneously paired by a plurality of memory arrays arranged in a line symmetry, and shared by the two memory arrays in the pair, and arranged through these memory arrays. In a pseudo-static RAM having a line, the common I / O line may be crossed by non-inverting and inverting signal lines of the common I / O line in the middle of two pairs of memory arrays, for example, a common I due to misalignment of a photomask. The effect that the operation of the pseudostatic RAM and the like can be stabilized by canceling the change in the parasitic capacitance of the / O line is obtained.

(14) The equalization process of the above-mentioned (13), which makes the equalization processing of the common I / O line faster and more stable by equalizing the common I / O line at the middle of the two corresponding memory arrays and on the outside of both sides. The effect that can be obtained is obtained.

(15) A pseudo-static RAM having a plurality of sense amplifiers provided in correspondence with each complementary data line of a memory array, wherein aluminum is passed through a contact corresponding to a source of a P-channel or N-channel MOSFET constituting the sense amplifier. For example, contact is made by common coupling to a common source line, which is a metal wiring layer, or the like, and at the same time by extending the diffusion layer constituting the source region again by common coupling of the sources of adjacent P-channel or N-channel MOSFET pairs. The effect that the efficiency of the pseudostatic RAM and the like can be improved by solving the solution of the sense amplifier due to a defect or the like can be obtained.

(16) A pseudo memory having a plurality of memory arrays distributed on a semiconductor substrate surface, a plurality of decoders provided corresponding to the memory arrays, and a predecoder for forming a predecode signal in accordance with a predetermined address signal and supplying the predecode signal to each decoder. In a static RAM or the like, a driver circuit for selectively delivering the predecode signal to a corresponding decoder is distributed in close proximity to the corresponding decoder to reduce the propagation delay time of the predecoder signal, thereby reducing the pseudostatic RAM or the like. The effect of speeding up is obtained.

(17) A pseudo-state RAM or the like comprising a plurality of redundant word lines or redundant redundant data lines, each having a plurality of memory arrays arranged in line symmetry with a center line of the semiconductor substrate surface interposed therebetween. By arranging the redundant data line in the order of line symmetry with the center line as the axis, the occurrence rate of the redundant word line or redundant data line is intentionally increased, and further, the failure of the redundant word line or redundant data line disposed therein. The effect of lowering the incidence rate and suppressing the incidence rate of this fault as the redundant word line or the redundant data line as a whole can increase the efficiency of the pseudostatic RAM and the like.

(18) A test signal which is supplied through an address input terminal in a predetermined test mode in a pseudostatic RAM or the like in which a predetermined fuse means is cut and its coefficient initial value is selectively including a regeneration timer counter circuit. This makes it possible to equally set the state in which the fuse means is cut off, thereby obtaining the effect of reliably and efficiently performing the characteristic evaluation of the regeneration timer counter circuit such as pseudostatic RAM and the like.

(19) A pseudo-static RAM having a self-regeneration mode and having a regeneration timer counter circuit for starting a regeneration operation at a predetermined cycle in the self regeneration mode, wherein the regeneration timer counter circuit is formed in a predetermined test mode. The test start signal supplied via a predetermined external terminal can be used in place of the start start signal to be used. Thus, the characteristics of the characteristics can be efficiently evaluated by randomly setting the regeneration period in the self regeneration mode such as pseudostatic RAM. The effect that can be obtained is obtained.

(20) The address dependency in the reproduction operation of the pseudo-statistic RAM or the like can be efficiently obtained by setting the reproduction address in the self-reproducing mode arbitrarily, for example, via the address input terminal. The effect that it can be tested is obtained.

(21) A plurality of external terminals are supplied by selectively combining a predetermined high voltage whose absolute value exceeds the power supply voltage of the circuit so that the test mode can be selectively set and a substantial test operation can be started. This simplifies test circuits such as pseudo-static RAMs and can reduce the cost.

(22) By the above-described effective use, the effect of speeding up and lowering power consumption can be achieved while stabilizing the operation of the pseudostatic RAM and the like.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, the invention is not limited to the said Example, Of course, it can be variously changed in the range which does not deviate from the summary.

For example, the number of divisions of memory arrays and combinations of peripheral circuits is arbitrary, and the number of word lines, redundant word lines, complementary data lines, redundant complementary data lines, and common I / Os provided in each memory array is arbitrary. Further, various embodiments will be considered for the combination of the operation mode, the test mode, the type of operation cycle, and the corresponding start control signal provided in the pseudostatic RAM. The same applies to the number of start control signals, address signals, input / output data, and the like, logic levels, and combinations thereof. Incidentally, the specific circuit configuration, the specific arrangement, the logic level of the internal control signal and the timing signal, and the like, and the like of each part shown in each circuit diagram or layout diagram are not limited by this embodiment.

In the above description, the invention made mainly by the present inventors has been described in the case where the invention is applied to a pseudostatic RAM, which is the background of use, but is not limited thereto. For example, an output buffer, an oscillation circuit, a suppression generating circuit and The invention relating to the fuse circuit, the arrangement method and the test method can be applied to other various semiconductor memory devices and semiconductor integrated circuit devices. These inventions can be widely applied to a semiconductor memory device or a semiconductor integrated circuit device including at least a corresponding circuit or the like.

The effect obtained by the representative of the invention disclosed in this application is briefly described as follows.

That is, the reference potential of the MOSFET for setting the discharge current of the capacitor of the oscillation circuit included in the regenerative timer circuit of the pseudo-static RAM, etc. is supplied by another capacitor to be floated during the discharge period. In addition, a well region coupled to the power supply voltage of the circuit is formed under a portion corresponding to approximately one half of the polysilicon layer constituting the resistance of the oscillation circuit, and under the portion corresponding to the other half. A well region is formed which is coupled to the ground potential of the circuit. The initial value of the count of the regenerative timer counter circuit of the regenerative timer circuit, for example, the pseudo-mode RAM or the like can be set to the test control signal supplied from a predetermined external terminal. Prepare a test mode that can be arbitrarily set.

This stabilizes the discharge current of the capacitor of the oscillating circuit such as the regeneration timer circuit, and almost equal regeneration capacity is coupled between the polysilicon resistor and the power supply voltage and ground potential of the circuit, thereby canceling power fluctuations. This can suppress fluctuations in the oscillation frequency of the oscillation circuit due to power supply bumps and the like. In addition, it is possible to test and verify the operation dependency of the oscillation circuit and the regeneration timer counter circuit and the address dependence of the information retention characteristics of the memory cells. Can be set to one value. As a result, lower power consumption can be promoted while stabilizing the operation of the pseudostatic RAM.

Claims (32)

A semiconductor memory device having a plurality of memory cells and a control circuit, wherein when the device is in the first magnetic regeneration mode, the control circuit executes a regeneration operation for each of the plurality of memory cells at every first regeneration period, and the device And in the second magnetic regeneration mode, the control circuit executes a regeneration operation for each of the plurality of memory cells every second regeneration period that is longer than the first regeneration period. 2. The apparatus of claim 1, wherein the apparatus further comprises a plurality of word lines and a plurality of data lines, each of the plurality of memory cells coupled to a corresponding word line and a corresponding data line, and wherein the control circuit is arranged in the first circuit. A reproduction address signal for selecting a word line in which a timing signal forming means for forming at least one timing signal among a first timing signal for determining a reproduction period and a second timing signal for determining the second reproduction period and a memory cell to be reproduced are combined; And a reproducing address signal forming means for forming a reproducing address signal in response to said first timing signal when said apparatus is in said first magnetic reproducing mode, said reproducing address signal being formed. The means for forming the reproduction address signal in response to the second timing signal when the apparatus is in the second magnetic reproduction mode. The semiconductor memory device is formed. 3. The apparatus of claim 2, wherein the timing signal forming means comprises: means for forming a third timing signal having a first frequency; means for forming the first timing signal having a second frequency in accordance with the third timing signal; And means for forming said second timing signal having a third frequency in accordance with a third timing signal, said third frequency being less than said second frequency. 4. The semiconductor memory device according to claim 3, wherein said reproducing address signal forming means includes a counter circuit for forming said reproducing address signal. The semiconductor memory device according to claim 4, wherein the counter circuit includes a plurality of unit counters connected in series to form a binary counter. 6. The semiconductor memory device according to claim 5, wherein when said device is in a normal operation mode, at least one of said plurality of word lines is selected in accordance with an external address signal input from outside the device. 7. The apparatus of claim 6, wherein the normal operation mode includes a read operation mode and a write operation mode. When the device is in the read operation mode, data held in a memory cell is read in accordance with the external address signal. Is in the write operation mode, the data is written to a memory cell in accordance with the external address signal. 8. The semiconductor memory device according to claim 7, wherein when the device is in the automatic regeneration mode, the regeneration operation is performed only once for each of the plurality of memory cells in response to a control signal input from the outside of the device. 9. The semiconductor memory device according to claim 8, wherein each of the plurality of memory cells is a dynamic memory cell including an information storage capacitor and an MOSFET for address selection. The semiconductor memory device of claim 3, wherein the first frequency is greater than the second frequency and the third frequency. The semiconductor memory device of claim 10, wherein the third frequency is one half of a frequency of the second frequency. Means for forming a plurality of word lines, data lines, several memory cells, a first timing signal having a first frequency, means for forming a second timing signal having a second frequency different from the first frequency, and reproduction 10. A semiconductor memory device comprising reproducing address forming means for forming a reproducing address signal for selecting a word line to which a memory cell to be coupled is coupled, wherein each of said plurality of memory cells is coupled to a corresponding word line and a corresponding data line, When the device is in the first magnetic regeneration mode, the reproducing address forming means forms the reproducing address signal in response to the first timing signal. And a reproducing address signal in response to a second timing signal. 13. The apparatus of claim 12, wherein the apparatus further comprises means for forming a third timing signal having a third frequency, wherein the first timing signal and the second timing signal are formed in accordance with the third timing signal. And a third frequency is less than the second frequency. The semiconductor memory device according to claim 13, wherein said reproducing address signal forming means includes a counter circuit for forming said reproducing address signal. 15. The semiconductor memory device according to claim 14, wherein the counter circuit includes a plurality of unit counters connected in series to form a binary counter. 16. The semiconductor memory device according to claim 15, wherein when the device is in a normal operation mode, at least one of the plurality of word lines is selected in accordance with an external address signal input from the outside of the device. 17. The apparatus of claim 16, wherein the normal operation mode includes a read operation mode and a write operation mode. When the device is in the read operation mode, data held in a memory cell is read in accordance with the external address signal. Is in the write operation mode, the data is written to a memory cell in accordance with the external address signal. 18. The semiconductor memory device according to claim 17, wherein when the device is in the automatic regeneration mode, the regeneration operation is performed only once for each of the plurality of memory cells in response to a control signal input from the outside of the device. 19. The semiconductor memory device according to claim 18, wherein each of the plurality of memory cells is a dynamic memory cell including an information storage capacity and an address selection MOSFET. The semiconductor memory device of claim 13, wherein the first frequency is greater than the second frequency and the third frequency. 21. The semiconductor memory device according to claim 20, wherein the third frequency is a frequency of 1/2 of the second frequency. A semiconductor memory device including reproducing address forming means for forming a reproducing address signal for selecting a plurality of word lines including a first word line, a plurality of data lines, a plurality of memory cells, and a word line combined with a memory cell to be reproduced; And each of the plurality of memory cells is coupled to a corresponding word line and a corresponding data line, and when the apparatus is in the first magnetic reproduction mode, the reproducing address forming means is coupled to the first word line every first period. When the device is in the second magnetic regeneration mode, the reproducing address forming means has a memory cell coupled to the first word line every second period different from the first period. A semiconductor memory device for performing a regeneration operation. 23. The apparatus of claim 22, wherein the apparatus further comprises timing signal forming means for forming a timing signal of at least one of a first timing signal for determining the first period and a second timing signal for determining the second period, The reproducing address signal forming means forms the reproducing address signal in response to the first timing signal when the device is in the first magnetic reproducing mode, and the reproducing address signal forming means is configured such that the reproducing address signal forming means is configured by the device in the second device reproducing mode. And the reproduction address signal in response to the second timing signal. 24. The apparatus of claim 23, wherein the timing signal forming means comprises: means for forming a third timing signal having a first frequency; means for forming the first timing signal having a second frequency in accordance with the third timing signal; Means for forming said second timing signal having a third frequency in accordance with a third timing signal, said third frequency being less than said second frequency. 25. The semiconductor storage device according to claim 24, wherein said reproducing address signal forming means includes a counter circuit for forming said reproducing address signal. 26. The semiconductor memory device according to claim 25, wherein the counter circuit includes a plurality of unit counters connected in series to form a binary counter. 27. The semiconductor memory device according to claim 26, wherein when the device is in a normal operation mode, at least one of the plurality of word lines is selected in accordance with an external address signal input from the outside of the device. 28. The apparatus of claim 27, wherein the normal operation mode includes a read operation mode and a write operation mode. When the device is in the read operation mode, data held in a memory cell is read in accordance with the external address signal. And in the write operation mode, data is written to a memory cell in accordance with the external address signal. 29. The semiconductor memory device according to claim 28, wherein when the device is in the automatic regeneration mode, the regeneration operation is performed only once for each of the plurality of memory cells in response to a control signal input from the outside of the device. 25. The semiconductor memory device according to claim 24, wherein each of the plurality of memory cells is a dynamic memory cell including an information storage capacitor and an address selection MOSFET. 25. The semiconductor memory device of claim 24, wherein the first frequency is greater than the second frequency and the third frequency. 32. The semiconductor memory device according to claim 31, wherein said third frequency is a period of one half of said second frequency.