KR0144728B1 - Method of forming refractory metal silicide cap for protecting multilayer polyside structure - Google Patents

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Description

Method of forming refractory metal silicide cap for protecting multilayer polyside structure

1 is a cross-sectional view of a semiconductor substrate having a polysilicon layer and a gate oxide layer formed thereon.

FIG. 2 is a cross sectional view showing a titanium layer on the structure of FIG.

FIG. 3 is a cross sectional view showing a composite layer of tantalum silicide on the structure of FIG.

4 is a perspective view showing patterning of the polyside layer in the structure of FIG.

5 is a cross-sectional view of the conversion of titanium to silicide in the structure of FIG.

6 is a cross-sectional view of the completed transistor.

* Explanation of symbols for main parts of the drawings

10; substrate 12: surface insulating layer (or field oxide layer)

14 gate oxide layer 16 poly layer

18: titanium layer (or refractory metal layer) 20: composite layer (or tantalum silicide layer)

22: titanium silicide layer 24: source

26: drain 28: channel area

The present invention relates to the formation of polysides, and more particularly to a method of forming a capping layer that improves the chemical stability and oxidation resistance of a polyside structure.

As MOS integrated circuits become more complex, improving circuit performance to reduce the size of each circuit component has not yet been realized in the whole field.

This improvement has been limited by the RC time constant characteristics of the long internal connections required to interconnect the increased circuit components.

In order to reduce these long interconnects, integrated circuit manufacturers are looking to refractory metals, refractory metal silicides and polysilicon / refractory metal silicide composite films (also known as polysides) instead of polysilicon, which are conventionally used for gate level interconnects. I'm paying attention.

Since the interconnect sheet resistance of these materials is 1-3Ω / ㅁ, the internal interconnect sheet resistance of polysilicon is very small compared to 10Ω / ㅁ.

One advantage provided by polysides is that they can be treated with temperature after deposition in addition to low resistance.

This is necessary to serve as an insulating layer between the various metal layers which may exceed the internal connection of three to four layers when trying to form high quality interlevel oxides.

Typically such oxide layers require the use of deposited glass that flows back out at a temperature of 800-900 ° C.

Such conventional metals, such as aluminum, will dissolve at these temperatures.

Polysides can be used to provide a relatively stable material with a high melting point that will not experience phase changes during the formation of interlevel oxides.

There are many polyside films to choose during the design phase of a given process.

Such refractory metals such as titanium, tungsten, molybdenum and tantalum are usefully used to make refractory metal silicides.

The thermal and chemical stability of all these metals is good, but their resistance properties change somewhat.

Most of the refractory metal silicides required from the viewpoint of circuit operation are titanium silicides, and the electrical resistance of the silicides is very small.

In fact, titanium silicide is one of the few refractory metals with a smaller electrical resistance than that of the base metal on which the silicide is formed.

One drawback of titanium silicides is that they do not have oxidation resistance as much as the other silicides.

Therefore, after the formation of the titanium silicide, the contact resistance of the internal linkages made from the different levels to the silicide is increased due to oxidation occurring on the surface of the titanium silicide, which adversely affects most processing systems.

Of course, silicides with very high oxidation resistance and good chemical stability can be used to solve these defects, but the silicides do not have the same resistance characteristics as titanium silicides.

Therefore, it is necessary to improve the oxidation resistance of the silicide layer better than the oxidation resistance of titanium silicide without impairing the chemical safety and conducting properties of the surface of the polyside.

The present invention constitutes a method of forming a polyside structure in which an oxidation resistance cap is formed.

The method of the present invention first includes forming a polycrystalline silicon layer on a semiconductor substrate.

This is followed by the formation of a base layer of refractory metal on the polycrystalline silicon layer, and a composite layer of refractory metal silicide is formed on the base refractory metal.

The sheet resistance of the composite refractory metal layer is equal to or greater than the sheet resistance of the resulting silicide of the base refractory metal layer and its chemical stability and oxidation resistance are greater than the silicide of the base refractory metal layer.

The refractory metal layer then dissipates only some of the silicon in the polysilicon layer as opposed to the underlying polysilicon to form its silicide.

At this time, the polycide structure is made by the pattern technique and the etch technique.

In another example of the invention, the base refractory metal layer is made from titanium, the composite refractory material is tantalum silicide, and the tantalum silicide layer is disposed on the titanium silicide in the resulting structure.

Tantalum silicide layers have good chemical stability and increased oxidation resistance compared to titanium silicides.

In another example of the present invention, the gate oxide layer is disposed under the polycrystalline silicon layer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional schematic diagram illustrating one step in the process of making a semiconductor structure.

Conventionally, in manufacturing a MOS integrated circuit, a thick oxide layer is first masked on a thin wafer of a semiconductor material having a conductivity type, as indicated by 10 in FIG.

Substrate 10 is a P-type material, but may also be used having an opposite conductivity.

Oxides are removed in a pattern so that the impurities that affect conductivity can be exposed to those areas that diffuse to form a moat.

The substrate 10 undergoes the diffusion of the required impurities at a temperature suitable for diffusion, and the wafer is removed from the diffusion environment after the required penetration and concentration are achieved and the oxide is regrown on the mote.

The surface insulation layer 12, which is considered to be the same as the field oxide of silicon, arises from the diffusion phase of the process column and the growth of the oxide, so that any electric field that develops in the normal working column of the device when a thin layer of metallization is applied is applied. This creates a layer thick enough to adversely affect the layer portion and not adversely affect the thinly insulated layer.

After forming the field oxide layer 12, the silicon surface in the moat undergoes a number of conventional cleaning steps and then the thin gate oxide layer 14 is grown to a thickness of about 100-1,000 mm 3 on the mote.

This is regarded as a gate oxide layer for MOS transistors.

To provide a very complete gate oxide, the mort is exposed under pure silicon and then a gate oxide layer 14 is formed on the silicon surface.

After the gate oxide layer 14 is formed, the polycrystalline silicon (poly) layer 16 is deposited on the substrate with a thickness of about 2,000-4,000 kPa by the CVD (chemical vapor deposition) technique.

N-type impurities are diffused or implanted into the poly layer 16 to reduce its sheet resistance to about 10 < -20 >

Typically phosphorus is used as the N-type dopant.

Using a CVD process, the poly layer 16 conforms to the properties and matches the shape of the substrate 10.

In FIG. 2, after forming the poly layer 16, the surface is cleaned with dilute HF during the cleaning process and the titanium alloy 18 is deposited on the surface.

Titanium is a refractory metal which is changed to titanium silicide as described later.

Titanium silicides are widely used in industry to provide low sheet reduction in long poly runs.

Poly layer 16 is necessary to provide a very complete gate oxide thereunder.

Currently, a technique for directly depositing the refractory metal layer 18 on the gate oxide layer is not used.

Therefore, the polylayer 16 is used as a buffer so that the later made titanium silicide formed from the titanium layer 18 provides the required conductivity.

The titanium layer 18 is deposited on the substrate by a PVD (physical vapor deposition) technique.

Such a technique may use a sputtering process or a deposition process.

In a good example, titanium is sputtered with a Varian 3190 sputtering machine.

This is done at a temperature of 100 ° C. in vacuo to provide about 800 mm thick titanium.

FIG. 3 shows a composite layer 20 of tantalum silicide (TaSi ₂ ) deposited on a substrate at a thickness of about 500 GPa in a second cross section.

In a preferred example, this tantalum silicide layer is sputtered with titanium in the sage.

Substrate 10 is held in a sputtering machine in vacuum for deposition of titanium layer 18 and tantalum silicide layer 20.

In this example, the substrate is initially placed in a sputtering machine and the top layer of poly layer 16 is conventionally cleaned by back sputtering.

Two objects are placed in a sputtering machine, one of which consists of a titanium refractory metal and the other of tantalum silicide composites.

In general, composite tantalum silicide materials are silicon rich.

That is, the stoichiometry of the compound is TaSix, where x varies between 2 and 3 (ie the ratio of the two materials is slightly above 2: 1).

Titanium layer 18 is deposited by sputtering at a temperature of about 100 ° C. after vacuuming the machine.

The amount of deposited titanium is a function of the duration of the deposition process and the setting of the machine control.

Then the second object of tantalum silicide is selected and it is deposited by a similar procedure using a temperature of about 400 ° C.

It is not necessary to deposit titanium and tantalum silicides in the same way.

By way of example, titanium may be deposited by another method such as a deposition method or in a separate sputtering machine and the substrate may be placed in a sputtering machine for tantalum silicide deposition.

This, of course, requires a back sputter cleaning process before depositing tantalum silicide.

After depositing the composite layer 20 of tantalum silicide, the substrate is removed from the sputtering machine and the photoresist is rotated on the substrate.

This photoresist is patterned to make a conductive structure that is the gate of the MOS transistor in this example.

Multilayer polyside consisting of patterned composite layer 20 of tantalum silicide, patterned titanium layer 18 of titanium, patterned polylayer 16 of polysilicon and patterned gate oxide layer 140 of gate oxide Plasma etching is applied to the substrate, which can be operated without etching the unpatterned areas to create the structure.

This is shown in FIG. 4, which shows a perspective view of the gate of the MOS transistor.

Here, it can be seen that the gate of the transistor extends over the field oxide layer 12 to be connected to another circuit.

Typically, etching polysides can be accomplished by dry etching (plasma or reactive ion etching) techniques, a method that has long been used to etch polysilicon to make integrated circuit gates or to interconnect levels.

Chemistry for providing anisotropic etching of polysilicon with good and specific etching rates for this silicon oxide is well known.

In addition, methods for etching polysides are also known.

This type of etching basically makes the edges of the patterned structure vertical.

One method of etching polysides is described in US Pat. No. 4,659,426 to Fuller, issued April 21, 1987, titled Plasma Etching of Refractory Metals and Their Silicides, another technique named Process for Patterning Local. Holloway, US Patent No. 4,657,628, issued April 14, 1987, which is interconnected.

After patterning the polyside structure, the substrate is subjected to an isothermal annealing process quickly in an N 2 atmosphere.

In a preferred embodiment this is a two step process.

First, the substrate is brought to a temperature of 550-650 ° C. for about 1 minute, and then the substrate 10 with the polyside structure defined is brought to a temperature of 800-900 ° C. (typically 900 ° C.) for about 20 seconds.

The purpose of this annealing process is to consume part of the underlying poly layer 16 to convert titanium in the titanium layer 18 to titanium silicide.

During the silicidation process, the titanium layer 18 consumes about 1,500-2,000 μs of silicon in the underlying polylayer 16.

As shown in FIG. 5, this forms a titanium silicide layer 22 having a thickness of about 2,000 mm 3.

As a result, the thickness of the poly layer 16 is about 1,500 kPa.

The purpose of bringing the substrate to 550-650 ° C. for 1 minute is to minimize particle boundary diffusion during the silicidation process.

In this way, N2 passes through the grain boundary and prevents the boundary diffusion of the grain.

As a result, the silicideation process at a temperature of 900 ° C. is relatively slow and flexible compared to the normal silicideation process.

If the silicide process is relatively fast, sparks may occur at the interface between the gate oxide layer 14 and the polyside / oxide, which may result in unfavorable results.

However, the treatment at a temperature of 550-650 ℃ can alleviate the above problems somewhat. The silicide is carried out at a temperature of 900 ° C.

In a preferred embodiment, titanium silicide is formed adjacent to polycrystalline silicon after patterning and etching, but it is also possible to bring the substrate to temperatures above 850-900 ° C. prior to etching and patterning the silicide prior to patterning. .

In addition, titanium silicide may be formed before deposition of tantalum silicide.

It is important that the tantalum silicide layer 20 is formed on the titanium silicide layer 22 in the resultant product.

The tantalum silicide layer 20 differs from titanium silicide, although it is a silicided refractory material, which is very resistant to oxidation, which is an important aspect of the present invention.

However, since the resistance of titanium silicide is smaller than that of tartalum silicide, it is not as desirable to deposit the tantalum silicide layer 20 directly on the polish 16 to form a basic conductive coating as is the case with titanium silicide.

The properties of the layer change depending on the refractory metal silicide useful for the tantalum silicide layer 20 constituting the capping layer.

It is important that the layer is better oxidized than the titanium silicide layer 22.

Therefore, the titanium silicide layer 22 is selected so that the sheet resistance of the selected layer can be minimized so that the chemical stability for subsequent processing is optimal and the resistance to oxidation is the best.

If the structure of the present invention is not useful, some relationship can be made between chemical stability and oxidation resistance and electrical conductivity properties.

Refractory metal silicides in the process of the present invention can be used to provide a low resistance layer without any substantial interest in chemical stability and oxidation resistance.

In this case, the second capping layer may be selected from the refractory metal silicide for chemical stability and oxidation resistance. This provides such technical advantages that the processing step can utilize refractory metal silicide stability for such operations, such as forming interlevel oxides at temperatures above 800 ° C. and provide a high oxidation resistant surface.

This is important in forming contacts from the metallization layer to the tantalum silicide layer 20, ie cappings.

Forming an oxide in this layer is not desirable for it, as it can cause increased contact resistance.

Processing after the formation of the polyside gate structure of FIG. 5 is complete, thereby producing a transistor.

This is done by conventional techniques.

The source / drain is made by implanting such an N-type impurity, such as phosphorus or arsenic, into the surface on either side of the patterned polyside gate structure.

As a result, the source 24 and the drain 26 are formed on either side of the gate structure, and the channel region 28 is formed below the gate oxide layer 14 between the source 24 and the drain 26. You lose.

Such a structure is shown in FIG.

In FIG. 6, after forming the source 24 and the drain 26, the interlevel oxide layer 30 is deposited on the substrate to form an insulating layer.

An opening 32 is formed over the source 24, an opening 34 is formed over the drain 26 and an opening 36 is formed over the tantalum silicide layer 20 in the gate structure.

In FIG. 6 the cross sections of the openings 32 and 34 are of the same shape, and the openings 36 are typically offset from the openings 32 and 34 and on the field oxide layer 12.

After the openings 32-36 are formed, the source contact, or plaque 38, is formed in the opening 32, the drain plaque 40 is formed in the opening 34, and the gate flag 42 is in the opening 36. Formed into contact with the underlying conductive structure.

Plaques 38-42 may be formed from CVD deposition of such materials, such as polysilicon or tungsten.

Thereafter, such a metallization layer, such as aluminum, is deposited and patterned on the top surface of the interlevel oxide layer 30.

This constitutes the level of metallization.

In short, a method of forming a polyside structure comprising a titanium silicide layer over each gate oxide layer polysilicon layer is provided.

A capping layer of refractory metal silicide or tantalum silicide, which is more chemically stable than titanium silicide and has a higher oxidation resistance, is formed on the titanium silicide.

This method involves forming a titanium layer over polysilicon and then depositing tantalum silicides.

These multilayer polyside structures are patterned and etched and then annealed to make titanium silicides from titanium and the underlying polysilicon material.

The present invention may be modified in various forms within the spirit of the present invention.

Claims (15)

Forming a polycrystalline silicon layer on the substrate surface yarns, forming a uniform titanium layer on the polycrystalline silicon layer with a predetermined thickness, and having a higher oxidation resistance and a more chemically stable refractory metal silicide composite layer on the titanium layer. Forming a thinner than the predetermined thickness of the titanium, to form a titanium silicide layer forming the primary conductive path, so that a portion of the polycrystalline silicon layer remains so that the remaining portion of the polycrystalline silicon layer located below the original titanium layer remains. Reacting the polycrystalline silicon layer with titanium to remove the titanium and patterning and etching the substrate to form a polyside structure consisting of polycrystalline silicon, titanium silicide and refractory metal silicide. A method of forming a conductive structure on a semiconductor substrate having a side. The method of claim 10, wherein forming the refractory metal silicide composite layer and forming the titanium layer comprises first sputtering a titanium layer on the surface of the polycrystalline silicon layer, and then forming a substrate on the upper surface of the titanium layer. Sputtering the tantalum silicide composite layer. 11. The method of claim 10, wherein reacting the titanium in the titanium layer with the silicon in the polycrystalline silicon layer comprises annealing the structure to a temperature sufficient to cause titanium to react with the silicon to form titanium silicide. How to. 12. The method of claim 10, wherein forming the polycrystalline silicon layer comprises depositing a uniform polycrystalline silicon layer by CVD deposition at a predetermined thickness. 12. The method of claim 10, further comprising forming an oxide layer on the substrate prior to forming the polycrystalline silicon layer. Forming a gate oxide layer on a surface of the substrate, depositing a polycrystalline silicon layer on the surface of the gate oxide layer at a predetermined thickness, sputtering the titanium layer on a surface of the polycrystalline silicon layer at a predetermined thickness, Sputtering a tantalum silicide composite layer on the titanium layer to provide an oxidation resistant layer having a thickness substantially less than a predetermined thickness of the titanium layer, and forming the titanium silicide layer to form a primary conductive path. Reacting titanium with silicon in the polycrystalline silicon layer located thereunder, patterning and etching the structure obtained as described above to form a conductive structure, and forming an insulating material layer over the conductive structure; The titanium layer and the In the step of reacting the silicon layer of titanium is defined a method of forming a polycide structure on a semiconductor substrate, characterized in that for removing the polycrystalline silicon layer so that the remaining portions of the polysilicon layer is present under the obtained titanium silicide layer. 17. The method of claim 16, wherein reacting the titanium with silicon in the underlying polycrystalline silicon layer comprises applying a temperature sufficient to the titanium layer and the silicon layer to cause titanium to react with the silicon to form titanium silicide. Characterized in that. 18. The method of claim 17, further comprising limiting the temperature to a temperature lower than the reaction temperature of titanium silicide before forming the titanium silicide layer to prevent boundary diffusion of particles. 17. The method of claim 16, wherein the conductive structure is a gate of a MOS transistor. 17. The method of claim 16, further comprising forming a thick oxide pattern on the substrate to form a selectively insulated region defining an exposed portion of the substrate, wherein the patterning and etching steps are performed up to the thick oxide region. Resulting in an extended patterned polyside portion. Forming a gate oxide layer on a surface of the substrate, depositing a polycrystalline silicon layer on the surface of the gate oxide layer at a predetermined thickness, sputtering the titanium layer on a surface of the polycrystalline silicon layer at a predetermined thickness, Sputtering a tantalum silicide composite layer on the titanium layer to provide an oxide resistive layer having a thickness substantially less than the predetermined thickness of the titanium layer, using tantalum silicide, titanium, polycrystalline silicon and gate oxide to form a conductive structure. Patterning and etching the composite layer thus formed and reacting the titanium of the titanium layer with silicon of the polycrystalline silicon layer located below to form a titanium silicide layer forming a primary conductive path, wherein the titanium Layer and the polycrystalline In the step of reacting the silicon layer of titanium is a method of forming a polycide structure on a semiconductor substrate, characterized in that for removing the polycrystalline silicon layer so that the remaining portions of the polysilicon layer is present under the obtained titanium silicide layer. 22. The method of claim 21, wherein reacting the titanium with silicon in the underlying polycrystalline silicon layer comprises applying to the titanium layer and the silicon layer a temperature sufficient to cause titanium to react with the silicon to form titanium silicide. The room characterized in that the. 22. The method of claim 21, further comprising limiting the temperature to a temperature lower than the reaction temperature of titanium silicide before forming the titanium silicide layer to prevent boundary diffusion of particles. 22. The method of claim 21 wherein the conductive structure is a gate of a MOS transistor. 22. The method of claim 21, further comprising forming a thick oxide pattern on the substrate to form a selectively insulated region defining an exposed portion of the substrate, wherein the patterning and etching steps to the thick oxide region. Resulting in an extended patterned polyside portion.