KR0129786B1 - Medium value filter - Google Patents

Abstract

The present invention relates to a median filter for selecting the median value Dk from among _N input digital data D ₁ , D ₂ ,..., D _N. The median filter according to the present invention has N (N-1) / 2 comparators Cij (where N is odd and i, j, k is a positive integer), and each comparator Cij has its own Comparing the combination (Di, Dj) of the input data applied through the two input terminals (X1, X2), logic 1 is represented as its output Rij for DiDj, and logic 0 as its output Rij for DiDj. A comparator (10) for outputting and satisfying a condition of ij and i ≠ j in the comparator Cij; In the comparator output Rij, the number of 0 and 1 of the output logic when i = k and the inverted output logic when j = k is checked and the input data Dk when N-1 / 2, respectively. An intermediate value judging means 20 for outputting a judging signal Sk for judging. The N digital values D ₁ , D ₂ ,..., D _N are input, and an intermediate value Dk corresponding to the determination signal Sk provided by the intermediate value determination means 20 is selected and output. And an intermediate value selecting means (30).

Description

Median filter

1 is a schematic block diagram of a median filter in accordance with the present invention.

2 is a circuit diagram of a discriminating unit that discriminates input data D ₁ as an intermediate value when the number N of input data is five.

3 is a circuit diagram of an intermediate value judging unit for judging input data D ₃ as an intermediate value when the number N of input data is 5. FIG.

4 is a circuit diagram reconstructed according to the present invention with the configuration shown in FIG.

5 is a circuit diagram of an intermediate value judging unit for judging input data D ₁ as an intermediate value when the number N of input data is 7. FIG.

* Explanation of symbols for main parts of the drawings

10: comparison unit 20: intermediate value determination unit

30: Median selector D ₁ , D ₂ , ..., D _N : Input digital data

Dk: Median Rij: Comparator Output

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital filters and, more particularly, to median filters that allow the selection of a median value from a plurality of digital values with simple hardware.

Various filters are used to filter a digitalized signal by quantizing a video signal or a general signal digitally. The median filter is a nonlinear filter that emphasizes the edges of the signal while removing the impulse noise added to the signal components, and is used for digital signal processing in your field.

The median filter performs a function of selecting one signal having a median value from the N digital input data signals, and is usually composed of a comparator, a median value discriminator, and a median selector. When N digital input data of binary code is D ₁ , D ₂ , ..., D _N , these signals are combined (Di, Dj), that is, (D ₁ , D ₂ ) (D ₁ , D ₃ ) , ... (D ₁ , D _N ); (D ₂ , D ₃ ), ..., (D ₂ , D _N ); (D ₃ , D ₄ ), ... Are combined. According to this scheme, the number M of input combinations may have N (N-1) / 2 combinations, which are provided to the comparison unit.

The comparator has M comparators for comparing these combinations, respectively. Each comparator is an output for outputting a logic 1 by a comparison operation, and includes a first output Rij when DiDj, a second output Qij when Di = Dj, and a third output Pij when DiDj. These outputs are provided to the median value discriminator in the next stage. The intermediate value judging section receives the outputs Pij, (Qij) and (Rij) of the comparator and selects the intermediate value. The intermediate value selecting section selects the intermediate value from the N input signals according to the discrimination signal from the intermediate value judging section. Switches the N input digital signals to be selected and output.

In the prior art, a large amount of hardware is required to generate the discrimination signal required by the intermediate value selector from the N input data in the intermediate value discriminator.

That is, when the number of input data is small, the number of comparators is not large, but when the number of input data is large, the number of comparators increases exponentially according to the above-described formula (N (N-1) / 2).

In addition, as the number of comparators increases, the configuration of the intermediate value determiner determines the intermediate value by using the increased number of outputs of the comparator. In order to solve this problem, a table look-up method may be used by using a ROM or a RAM when configuring an intermediate value determiner. However, according to this method, the number of components of the intermediate value discrimination unit can be reduced, but when the entire intermediate value filter is implemented in a field programmable gate array (EPGA) or an integrated circuit (IC), a separate memory device is required. As a result, there has been a problem that a large amount of circuit board and external input / output terminals are required.

As another method of implementing the median filter, the input data D ₁ , D ₂ , ..., D _N can be divided into small groups to reduce the number of comparators in the comparator and the hardware complexity of the median discriminator. In this case, the intermediate value selector becomes large, and latches are frequently used due to delay of input data.

Accordingly, an object of the present invention is to provide a median filter having a median value discriminating section composed of simple hardware.

According to a preferred embodiment of the present invention, the median filter for selecting the median value Dk among the _N input digital data D ₁ , D ₂ , ..., D _N is: N (N-1) / 2 comparators (Cij), and each comparator (Cij) compares the combination (Di, Dj) of the input data applied through its two input terminals (X1, X2) and, in the case of DiDj, logic 1 as its output (Rij). In the case of DiDj, a logic 0 is output as its output Rij, and the comparator 10 satisfies the condition of ij and i ≠ j in the comparator Cij; and i = in the comparator output Rij. A discrimination signal for checking the number of 0 and 1 of the output logic in the case of k and the inverted output logic in the case of j = k and discriminating the input data Dk as an intermediate value when each becomes (N-1) / 2. An intermediate value judging means 20 for outputting Sk; An intermediate value selection means for inputting the N digital values D ₁ , D ₂ ,..., D _N and outputting an intermediate value corresponding to the determination signal Sk provided by the intermediate value determination means 20. (30), wherein N is odd and i, j, k is a positive integer.

Hereinafter, the median filter constructed in accordance with the present invention will be described in detail as follows with reference to the accompanying drawings.

The first turn is shown for receiving an intermediate value B consisting of N bits, a schematic block diagram of the filter (N is an odd number) of the digital values _{D 1, D 2, ...,} D N according to the present invention.

The median filter includes a comparator 10 for comparing input signals and outputting a comparison result, and a median value discriminating unit for determining whether an arbitrary input among the N input data is an intermediate value according to the output of the comparator 10 ( 20) and an intermediate value selector 30 for switching the output of the intermediate values Dk from the N digital values according to the intermediate value discrimination signal provided from the intermediate value discriminator 20 to select an intermediate value. .

N digital signals D ₁ , D ₂ ,..., D _N composed of B bits are input to the comparator 10 in the form of a combination Di, Dj. In this case, the N input data may be composed of M (= N (N-1) / 2) input combinations Di and Dj. When M combinations are input to the comparator 10, the digital values of these combinations are compared by corresponding M comparators, respectively. If each comparator is defined as Cij with two inputs (X1, X2) receiving a combination of digital signals (Di, Dj), i is applied to the input of X1 and j is the input of X2, so i = 1, 2, ..., N-1, and j = 2,3, ... Where ij and i ≠ j

For example, if the number N of median filter inputs is five, the combination of digital signals Di and Dj is (D ₁ , D ₂ ) (D ₁ , D ₃ ), (D ₁ , D ₄ ) (D ₁ , D ₅ ),; (D ₂ , D ₃ ), (D ₂ , D ₄ ), (D ₂ , D ₅ ); (D ₃ , D ₄ ), (D ₃ , D ₅ );

(D _4, D ₅₎ is configured to 10 of. At this time, the comparator compares the input combination, respectively, C ₁₂ , C ₁₃ ,

C ₁₄ , C ₁₅ , C ₂₃ , C ₂₄ , C ₂₅ , C ₃₄ , C ₃₅ , C ₄₅ , a total of 10.

Each comparator (C ₁₂ , C ₁₃ , C ₁₄ , C ₁₅ , C ₂₃ , C ₂₄ , C ₂₅ , C ₃₄ , C ₃₅ , C ₄₅ ) compares the combined inputs of the comparator (Di, Dj) to DiDj. Has the output Rij that outputs a logic high or logic 1 signal, and otherwise outputs a logic 0.

Each comparator Cij has an output Qij when Di = Dj and an output Pij when DiDj, and these outputs are not used in the present invention. The output Rij of each comparator Cij is provided to the intermediate value discriminating unit 20.

FIG. 2 is a detailed circuit diagram of the intermediate value discriminating unit 20 to which the respective comparator output Rij signals output from the comparator 10 are input. The median value discriminating unit 20 has a configuration for determining whether any k-th input data Dk among the N input data is an intermediate value when receiving the output Rij provided from the M comparators.

According to the present invention, in determining whether or not any k-th input data Dk among the N input data is an intermediate value, it is compared only when the condition corresponding to i = k or j = k in the comparator output Rij. . There are (N-1) comparator outputs Rij that satisfy these conditions, and it is determined whether any k-th data is an intermediate value from the outputs Rij of the (N-1) comparators Cij.

In the example of the present invention, assuming that the number of input data (N) is 5, i or j is equal to k (i = k, j = k) to determine whether any k th data among 10 input combinations is an intermediate value. Only four comparator outputs Rij satisfying the condition are determined.

When any k is 1, the outputs of the four comparators satisfying the above i = k or j = k conditions will be (R ₁₂ , R ₁₃ , R ₁₄ , R ₁₅ ). Therefore, k = 1, that is, in order for D _{1 to} become an intermediate value, the output Rij values of the four comparators Cij, that is, the number of logic 0 and logic 1 are (N-1) / 2 (N = 5). Logic 0 is 2 logic 1 is 2). For example, if D ₁ can be an intermediate value, the outputs of the four comparators (C ₁₂ , C ₁₃ , C ₁₄ , C ₁₅ ) (R ₁₂ , R13, R ₁₄ , R ₁₅ ) are respectively (R ₁₂ , R ₁₃ , R ₁₄ , R ₁₅ ), respectively, is equal to (0011), (0101), (0110), (1001)

In the case of (1010) and (1100), D ₁ is an intermediate value. Thus, the intermediate value discrimination circuit which satisfies the above conditions from (R ₁₂ , R ₁₃ , R ₁₄ , R ₁₅ ) is as shown in FIG. 2. 2 illustrates the intermediate value discrimination unit 20 as an exclusive OR (XOR) gate and an AND-OR gate according to the above results. When D ₁ is an intermediate value, the intermediate value discrimination unit 20 is configured as a determination signal S ₁ . Outputs 1 Implementation of the circuit shown in FIG. 2 using the above results is well known in the art, and thus a detailed description thereof will be omitted.

On the other hand, if Dk is an intermediate value, if j = k instead of i = k in the comparator output Rij, the output value of the comparator is inverted so that the number of logic 0 and 1 becomes (N-1) / 2. Should be inspected. For example, when determining whether any input data D ₃ is an intermediate value, a case where i = 3 or j = 3 appears in the comparator Cij. There will be four comparators {C ₂₃ , C ₂₃ , C ₃₄ , C ₃₅ } for comparing whether the input data D ₃ is an intermediate value, and a circuit including exclusive OR from these comparators is shown in FIG. . As shown, the output of the comparator (R _i3 , j = 3) should be inverted and used.

FIG. 4 shows a discriminating unit in which the circuit configuration shown in FIG. 3 is reconstructed using ordinary logic. According to the present invention, it is possible to easily configure the comparator output Rij without using a logical expression and using the following rule. That is, in the comparator output Rij provided from the comparator 10 to the intermediate value discrimination unit 20, when there are zero or two inputs with j = 3, the exclusive OR gate is configured as it is and j = 3. If the input is one (1), it can be configured by switching to an exclusive OR gate and an exclusive NOR gate and expressing the input as (Rij). According to the above-described scheme, the configuration of the exclusive OR gate shown in FIG. 3 is composed of the modified exclusive NOR gate as shown in FIG.

In the above-described determination of the intermediate value, the intermediate value can always be selected if the input data D ₁ , D ₂ , ..., D _N all have different values, but if i, j≤N, ij, Di = In the case of Dj, the output Rij of the comparator Cij comparing these Di and Dj is zero. When Di = Dj under the conditions i, j ≤ N and ij, the comparator Cij comparing these Di and Dj outputs 1 as its output Rij. Therefore, this rule is expressed as Di and Dj as follows.

In the formula (1), ε represents a minute positive value. Therefore, even if Dj = Di, the intermediate value can always be selected by the above equation (1).

That is, when using R as the output of the comparator, the other output P of the comparator is the inverse of R, and when Q is Di = Dj, the output becomes 1 and the remaining 0 becomes the output of the P and Q. It should not be used in the median determination unit. On the contrary, if the output of the comparator is used as P, the outputs of Q and R are not used.

If P is used as the output of the comparator, the median value Dk can be selected as follows. First, assuming the intermediate value Dk, check whether the output logic of j = k and the number of inverted output logic 0 and 1 when i = k becomes (N-1) / 2 in the comparator output Pij. . In addition, when the values of the input combinations Di and Dj are the same, the output P becomes logic 1 if ij, and the output P becomes logic 0 when ij. That is, since P is the inverse of R described above, it is possible to substitute the inverse of the comparison determination unit in the rule of R.

The above rules are extensible for general N. For example, if N is 7, the combination of comparators is {C ₁₂ , C ₁₃ , C ₁₄ , C ₁₅ , C ₁₆ , C ₁₇ ,; C ₂₃ , C ₂₄ , C ₂₅ , C ₂₆ , C ₂₇ ,; C ₃₄ , C ₃₅ , C ₃₆ , C ₃₇ ; C ₄₅ , C ₄₆ , C ₄₇

C ₅₆ , C ₅₇ ; C ₆₇ }, a total of 21 comparators are required, and the discrimination circuit for determining whether D ₁ is an intermediate value is configured as a median value discriminating unit as shown in FIG. Could be implemented. Similarly, the circuit configuration of the intermediate value discriminating unit of the remaining D ₂ , D ₃ , D ₄ , D ₅ , D ₆ , and D ₇ can be easily implemented using the above-described rules.

Therefore, as described above, the median filter according to the present invention can select the median as a simple hardware structure without using a separate memory by using information about the median known in advance.

Claims (4)

In the median filter for selecting the median value Dk among the N input digital data D ₁ , D ₂ ,..., And D _N , each N (N-1) / 2 comparators Cij are provided. The comparator Cij compares a combination Di and Dj of the input data applied through its two input terminals X1 and X2 and compares logic 1 as its output Rij in the case of DiDj and its output in the case of DiDj. A comparator (10) for outputting logic 0 as (Rij) and satisfying a condition of ij and i ≠ j in the comparator Cij; In the comparator output Rij, the number of 0 and 1 of the output logic in the case of i = j and the inverted output logic in the case of i = k is examined, and the input data Dk is obtained when (N-1) / 2 respectively. An intermediate value judging means 20 for outputting a judging signal Sk for judging. The N digital values D ₁ , D ₂ ,. . , D _N as an input, and including an intermediate value selecting means (30) for selecting and outputting an intermediate value (Dk) corresponding to the discriminating signal (Sk) provided by the intermediate value determining means (20), wherein A median filter in which N is odd and i, j, k are positive integers. The comparator output Rij according to claim 1, wherein when the values of Di and Dj are the same in the input combination Di and Dj, the comparator output Rij becomes logic 0, and the comparator output is ij. (Rij) is the median filter that makes logic 1 In the median filter for selecting the median value Dk among the N input digital data D ₁ , D ₂ ,..., And D _N , each N (N-1) / 2 comparators Cij are provided. The comparator Cij compares the combination (Di, Dj) of input data applied through its two input terminals X1 and X2 and compares logic 1 as a comparator output Rij for DiDj and a comparator output for DiDj. A comparator (10) for outputting logic 0 as (Rij) and satisfying a condition of ij and i ≠ j in the comparator Cij; In the comparator output Rij, it is checked whether the number of 0 and 1 of the output logic when j = k and the inverted output logic when i = k becomes (N-1) / 2, respectively. Intermediate value discriminating means (20) for outputting a discriminating signal (Sk) for discriminating the input data (Dk) as an intermediate value when 1) / 2 is obtained; An intermediate value for selecting and outputting the N digital values D ₁ , D ₂ ,..., And D _N , and selecting and outputting an intermediate value Dk corresponding to the determination signal provided by the intermediate value determining means 20. Median filter comprising selection means (30), where N is an odd number and i, j, k are positive integers. The comparator output Rij according to claim 3, wherein when the values of Di and Dj are the same in the input combination Di, Dj, the comparator output Rij becomes logic 1, and when the ij is comparator output. (Rij) is the median filter that causes logic to be zero.