KR0122847B1 - Reduction of warpage in integrated circuit packages - Google Patents

Reduction of warpage in integrated circuit packages

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Publication number
KR0122847B1
KR0122847B1 KR1019970010103A KR19970010103A KR0122847B1 KR 0122847 B1 KR0122847 B1 KR 0122847B1 KR 1019970010103 A KR1019970010103 A KR 1019970010103A KR 19970010103 A KR19970010103 A KR 19970010103A KR 0122847 B1 KR0122847 B1 KR 0122847B1
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South Korea
Prior art keywords
circuit board
package
die pad
semiconductor chip
integrated circuit
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KR1019970010103A
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Korean (ko)
Inventor
허영욱
한경희
심일권
류재진
염동신
손주영
김진천
황인선
음세진
전춘배
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황인길
아남산업주식회사
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Publication of KR0122847B1 publication Critical patent/KR0122847B1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83194Lateral distribution of the layer connectors
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    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
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    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 집적회로패키지의 휨현상 감소방법에 관한 것으로, 집적회로 패키지중에 BGA(Ball Grid Array; 볼그리드어레이) 및 COB(Chip On Board; 보드상의 칩) 패키지를 패키지화하기 위한 몰딩시에 불평형한 몰딩으로 인하여 발생하는 휨현상을 패키지 및 다이패드(Die Pad)의 디자인을 변경함으로써 휨현상을 최소화한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reducing warpage of an integrated circuit package, wherein an unbalanced molding is used during molding to package a ball grid array (BGA) and a chip on board (COB) package in an integrated circuit package. The warpage phenomenon is minimized by changing the design of the package and the die pad.

즉, 패키지 회로기판상의 다이패드의 협상을 변형시켜 열팽창에 대한 휨을 최소화하는 형상으로 하거나 다이패드에 솔더마스크를 입혀 외부 패키지의 열변화에 대한 영향을 받지 않도록 한 것으로 보다 향상된 집적회로패키지를 제조할 수 있어 제조공정상에서 발생되는 반도체칩의 기능 및 신뢰성을 높일 수 있는 것이다.In other words, by modifying the negotiation of the die pad on the package circuit board to minimize warpage due to thermal expansion or by applying a solder mask to the die pad so as to not be affected by thermal changes of the external package, an improved integrated circuit package can be manufactured. It can increase the function and reliability of the semiconductor chip generated in the manufacturing process.

Description

집적회로 패키지의 휨현상 감소방법Reduction of warpage in integrated circuit packages

본 발명은 집적회로패키지에 있어서, BGA(Ball Grid Array; 볼 그리드 어레이) 및 COB(Chip On Board; 회로기판상의 칩)를 패키지화하기 위한 몰딩시에 회로기판의 휨현상을 최소화한 집적회로패키지의 휨현상 감소방법에 관한 것이다.The present invention relates to an integrated circuit package, in which a bending phenomenon of an integrated circuit package is minimized during molding to package a ball grid array (BGA) and a chip on board (COB). It is about a reduction method.

일반적으로 집적회로패키지(IC Pakage)의 제조공정은, 회로기판(PCB)의 다이패드상에 실리콘재의 반도체칩을 부착하고, 와이어 본딩한 다음에, 몰딩공정에서 몰딩수지물로 집적회로를 패키지화하는 공정을 포함하여 이루어진다. 즉, 첨부도면의 제1도(a)(b)에 도시되어 있는 바와 같이, 종래의 BGA 패키지(100)는 상면중앙에 다이패드(11)가 형성되어 있고 표면에는 회로패턴(12)이 형성되어 있으며 상기 회로패턴(12)을 보호하기 위해 솔더마스크(13)가 코팅되어 있는 회로기판(10)과, 상기 회로기판(10)의 상면 중앙에 부착되어 있는 반도체칩(20)과, 상기 반도체칩(20)과 상기 회로기판(10)의 회로패턴(12)을 연결하여 신호를 전달하는 와이어(30)와, 상기 회로기판(10)의 회로패턴(12)에 융착되어 외부로 신호를 전달하는 솔더볼(40)과, 상기 반도체칩(20)과 그외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 몰딩 수지물(50)로 구성된다. 이 경우에, 상기한 종래의 BGA 패키지(100)는, 몰딩 수지물(50)의 형상이 단순히 정사각형이나 직사각형의 모양을 가지고 있을 뿐만 아니라, 상기한 몰딩 수지물(50)의 측벽이 7~12°범위의 각도(α)로 되어 있으며, 또한 반도체칩(20)이 부착되는 다이패드(11)의 형상도 단순한 정사각형이나 직사각형의 평면으로 되어 회로기판(10)의 상면에만 형성되는 구조로 이루어진다.In general, an IC Pakage fabrication process involves attaching a semiconductor chip made of silicon on a die pad of a PCB, wire bonding, and then packaging the integrated circuit with a molding resin in a molding process. Including the process. That is, as shown in FIG. 1 (a) and (b) of the accompanying drawings, in the conventional BGA package 100, the die pad 11 is formed at the center of the upper surface and the circuit pattern 12 is formed on the surface thereof. And a circuit board 10 having a solder mask 13 coated thereon to protect the circuit pattern 12, a semiconductor chip 20 attached to a center of an upper surface of the circuit board 10, and the semiconductor. The wire 20 is connected to the chip 20 and the circuit pattern 12 of the circuit board 10 to transmit a signal, and the circuit pattern 12 of the circuit board 10 is fused to transmit a signal to the outside. The solder ball 40 and the semiconductor chip 20 and other peripheral components are formed of a molding resin 50 wrapped around the outside to protect it from oxidation and corrosion. In this case, in the conventional BGA package 100, the shape of the molding resin 50 is not merely square or rectangular, and the sidewalls of the molding resin 50 are 7-12. The die pad 11 to which the semiconductor chip 20 is attached is also formed in a simple square or rectangular plane and is formed only on the upper surface of the circuit board 10.

그러나, 이와 같은 형상 및 구조를 갖는 종래의 BGA패키지 및 COB패키지는, 회로기판(10)의 일측면만을 몰딩하는 원사이드(One-Side) 몰딩방식이기 때문에 몰딩공정후에 회로기판(10)과 몰딩 수지물(50)과의 서로 다른 열팽창 계수로 인하여 발생되는 응력(스트레스; Stress)을 충분히 감쇄시켜 줄 수 없으므로 열을 가하는 공정때마다 자재의 휨현상이 심화되는 문제점이 있다.However, the conventional BGA package and COB package having such a shape and structure is a one-side molding method in which only one side of the circuit board 10 is molded. Therefore, the BGA package and the COB package are molded with the circuit board 10 after the molding process. Since the stress (stress) generated due to different coefficients of thermal expansion with the resin material 50 cannot be sufficiently attenuated, there is a problem that the warpage of the material is intensified with each step of applying heat.

상기한 휨현상은 패키지의 몰딩수지물(50)의 경화시 발생되는 수축에 의해서 패키지(100)에 발생되는 응력에 의해서 유발되는데, 이러한 휨현상은 패캐지의 측벽에서 발생되며, 특히 패키지의 측벽이 서로 만나는 각각의 코너부(A)에서 가장 심하게 발생된다. 이에따라, 몰딩수지물(50)의 내부에 있는 다이패드(11)가 휘고, 회로기판(10)의 회로패턴(12)에 융착된 솔더볼(40)(Solder Ball; 납공, 집적회로의 리드핀 역할)의 평탄성이 문제가 된다.The warpage phenomenon is caused by the stress generated in the package 100 by shrinkage generated during curing of the molding resin 50 of the package. This warpage phenomenon is generated in the sidewalls of the package, and in particular, the sidewalls of the package meet each other. Most severely generated at each corner portion A. FIG. Accordingly, the die pad 11 inside the molding resin 50 is bent, and a solder ball 40 fused to the circuit pattern 12 of the circuit board 10 is a solder ball; ) Flatness becomes a problem.

특히, 다이패드(11)의 휨은 반도체칩(20)과의 접착력을 저하시켜 계면박리 및 크랙을 가져오므로 집적회로패키지(100)의 기능 및 신뢰성에 큰 문제로 대두되며, 또한 솔더볼(40)의 비평탄성으로 인하여 마더보드에 BGA패키지 및 COB패키지를 실장시 솔더볼(40)이 마더보드에 접속되지 않아 패키지(100)의 기능수행에 문제가 발생된다.In particular, since the bending of the die pad 11 lowers the adhesive force with the semiconductor chip 20 and brings about interfacial peeling and cracking, it is a big problem in the function and reliability of the integrated circuit package 100, and also solder balls 40. Due to the non-flatness of the), when mounting the BGA package and COB package on the motherboard, the solder ball 40 is not connected to the motherboard, causing problems in the performance of the package 100.

본 발명의 목적은 상기한 바와 같은 종래의 문제점을 해소하기 위한 것으로서, 회로기판의 다이패드에 솔더마스크를 덮어씌우거나, 회로기판의 저면에 별도의 다이패드를 형성함으로써 열가공 공정에서 패키지의 휨을 방지하고, 다이패드 상에 부착된 반도체칩의 계면박리 및 크랙을 방지할 수 있는 집적회로패키지의 휨현상 감소방법을 제공하는데 있다.An object of the present invention is to solve the conventional problems as described above, by covering the solder mask on the die pad of the circuit board, or by forming a separate die pad on the bottom of the circuit board to reduce the warpage of the package in the thermal processing process. The present invention provides a method of reducing the warpage phenomenon of an integrated circuit package, which can prevent the interfacial peeling and cracking of a semiconductor chip attached to a die pad.

제1도는 일반적인 집적회로패키지를 도시한 것으로,1 shows a general integrated circuit package,

a도는 집적회로패키지의 단면도.a is a sectional view of an integrated circuit package.

b도는 집적회로패키지의 평면도.b is a plan view of the integrated circuit package.

제2a,b도는 본 발명의 제1실시예에 따른 회로기판의 저면 및 단면도.2A and 2B are bottom and cross-sectional views of a circuit board according to a first embodiment of the present invention.

제3도는 본 발명의 제2실시예에 따른 회로기판을 도시한 단면도.3 is a cross-sectional view showing a circuit board according to a second embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

100 : 집적회로패키지 10 : 회로기판100: integrated circuit package 10: circuit board

11 : 다이패드 12 : 회로패턴11: die pad 12: circuit pattern

13 : 솔더마스크 20 : 반도체칩13 solder mask 20 semiconductor chip

30 : 와이어 40 : 솔더볼30: wire 40: solder ball

50 : 몰딩수지물50: molding resin

본 발명의 목적을 달성하기 위하여, 회로기판(10)의 저면에 다이패드(11)와 동일한 재질로 다이패드(11)와 유사한 표면적을 갖는 또 다른 다이패드(11a)를 형성하여 열팽창에 대한 휨을 최소화 하거나, 다이패드(11)에 솔더마스크(13)를 입혀 외부 패키지(100)의 열변화에 대한 영향을 받지 않도록 하였다.In order to achieve the object of the present invention, the bottom surface of the circuit board 10 to form another die pad (11a) having the same surface area as the die pad 11 of the same material as the die pad 11 to bend the thermal expansion Minimized or by applying a solder mask 13 to the die pad 11 so as not to be affected by the thermal change of the outer package (100).

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조로 하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings in order to be described in detail to those skilled in the art can easily practice the present invention.

제2도의 (a)는 본 발명의 제1실시예에 따른 회로기판(10)의 저면도이고, 제2도의 (b)는 제2도(a)의 I-I선 단면도이다. 본 발명의 제1실시예에서는, 제2도에 도시되어 있지 않은 부분은 제1도에 도시되어 있는 부분과 동일한 구조를 가지므로 편의상 이에 대한 도시를 생략하여 표현하였다.FIG. 2A is a bottom view of the circuit board 10 according to the first embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along the line I-I of FIG. In the first embodiment of the present invention, since the part not shown in FIG. 2 has the same structure as that shown in FIG. 1, the description thereof is omitted for convenience.

제2도에 도시되어 있는 바와 같이 본 발명의 제1실시예에서, 상기 회로기판(10)상의 다이패드(11)는 몰딩수지물(50)로 몰딩하거나 열이 가해지면 상기 회로기판(10)과 다이패드(11)의 재질이 상이하여 열팽창이 다르므로 회로기판(10) 자체의 형상이 휘게 되는데, 이를 방지하기 위하여 회로기판(10) 상에 형성된 다이패드(11)와 동일한 재질로 회로기판(10)의 저면에 또 다른 다이패드(11a)를 형성함으로서 열팽창에 의한 회로기판의 휨을 감소시켰다.As shown in FIG. 2, in the first embodiment of the present invention, the die pad 11 on the circuit board 10 is molded with a molding resin 50 or the heat is applied to the circuit board 10. Since the thermal expansion is different because the materials of the die pad 11 and the die pad 11 are different, the shape of the circuit board 10 itself is bent. To prevent this, the circuit board is made of the same material as the die pad 11 formed on the circuit board 10. By forming another die pad 11a on the bottom of (10), the warpage of the circuit board due to thermal expansion was reduced.

이때, 상기 회로기판(10)의 상하면에 형성된 다이패트(11)(11a)의 재질은 구리(Cu)를 사용하는 것이 일반적이며, 회로기판(10) 상에 형성된 다이패드(11)의 표면적과 유사한 표면적을 갖도록 회로기판(10)의 저면에도 다이패드(11a)를 형성함으로서 열팽창에 의해서 회로기판(10)이 변형될 때 상기 회로기판(10)의 상하면에 형성된 다이패드(11)(11a)에 의해 회로기판(10)의 상하면이 동일한 열팽창이 이루어짐으로써 휨을 방지한다.At this time, the material of the die pads 11 and 11a formed on the upper and lower surfaces of the circuit board 10 is generally made of copper (Cu), and the surface area of the die pad 11 formed on the circuit board 10 and By forming a die pad 11a on the bottom surface of the circuit board 10 to have a similar surface area, the die pads 11 and 11 a formed on the upper and lower surfaces of the circuit board 10 when the circuit board 10 is deformed by thermal expansion. As a result, the upper and lower surfaces of the circuit board 10 have the same thermal expansion, thereby preventing warpage.

제3도는 본 발명의 제2실시예에 따른 회로기판(10)의 단면도를 나타낸다. 본 발명의 제2실시예에서도, 제3도에 도시되어 있지 않은 부분은 제1도에 도시되어 있는 부분과 동일한 구조를 가지므로 편의상 이에 대한 도시를 생략하여 표현하였다.3 shows a cross-sectional view of a circuit board 10 according to a second embodiment of the present invention. In the second embodiment of the present invention, the parts not shown in FIG. 3 have the same structure as the parts shown in FIG. 1, and are not shown for convenience.

제3도에 도시되어 있는 바와 같이 본 발명의 제2실시예는, 상기 회로기판(10)의 다이패드(11)에 솔더마스크(13)로 덮어 씌어 다이패드(11)의 열팽창을 억제시키고 다이패드(11)상에 반도체칩(20) 정착시 접착수지의 두께를 균일하게 유지할 수 있다. 즉, 상기 회로기판(10)의 저면에는 솔더마스크(13)가 도포되어 있고, 회로기판(10)의 상면 외측부에도 솔더마스크(13)가 도포되어 잇다.As shown in FIG. 3, in the second embodiment of the present invention, the die pad 11 of the circuit board 10 is covered with a solder mask 13 to suppress thermal expansion of the die pad 11, When fixing the semiconductor chip 20 on the pad 11, the thickness of the adhesive resin can be maintained uniformly. That is, the solder mask 13 is applied to the bottom of the circuit board 10, and the solder mask 13 is also applied to the outer side of the upper surface of the circuit board 10.

이와 같이 회로기판(10)상의 다이패드(11)에 솔더마스크(13)를 도포함으로써 열팽창에 의해서 회로기판(10)이 변형될 때 회로기판 상하부에 도포된 솔더마스크의 표면적이 비슷함으로서 변형을 방지한다. 즉, 회로기판(10) 상면의 솔더마스크에 의한 열팽창과 하면의 솔더마스크에 의한 열팽창이 동일함으로서 회로기판의 변형이 최소화 되는 것이다.By applying the solder mask 13 to the die pad 11 on the circuit board 10 as described above, when the circuit board 10 is deformed by thermal expansion, the surface area of the solder mask applied to the upper and lower parts of the circuit board is similar to prevent deformation. do. That is, the thermal expansion by the solder mask on the upper surface of the circuit board 10 and the thermal expansion by the solder mask on the lower surface are the same, so that deformation of the circuit board is minimized.

이상의 설명에서와 같이 본 발명은 BGA 및 COB패키지의 몰딩시나 열가공공정에서 발생하는 패키지의 휨현상을, 회로기판의 다이패드에 솔더마스크를 덮어 씌우거나, 회로기판의 저면에 별도의 다이패드를 형성하여 억제함으로써 회로기판과 다이패드의 열팽창에 따른 반도체칩의 파손이나 솔더볼의 비평탄성 문제등을 해결할 수 있는 것이다. 또한 패키지화되는 여타의 집적회로패키지에 본 발명의 디자인을 적용함으로써 보다 향상된 집적회로패키지를 제조할 수가 있어 제조공정상에서 발생되는 반도체칩의 기능 및 신뢰성을 높일 수가 있다.As described above, the present invention covers the warpage of the package generated during the molding of the BGA and COB packages or during the thermal processing process, by covering a solder mask on the die pad of the circuit board, or by forming a separate die pad on the bottom of the circuit board. This can solve the problem of breakage of the semiconductor chip due to thermal expansion of the circuit board and the die pad, and the problem of non-flatness of the solder ball. In addition, by applying the design of the present invention to other integrated circuit packages to be packaged, it is possible to manufacture an improved integrated circuit package, thereby improving the function and reliability of the semiconductor chip generated in the manufacturing process.

Claims (2)

상면 중앙에는 다이패드(11)가 형성되고, 표면에는 회로패턴(12)이 형성되며 상기 회로패턴(12)을 보호하기 위해 솔더마스크(13)가 코팅된 회로기판(10)과, 상기 회로기판(10)의 다이패드(11)에 부착된 반도체칩(20)과, 상기 반도체칩(20)과 회로기판(10)의 회로패턴(12)을 연결하여 신호를 전달하는 와이어(30)와, 상기 회로기판(10)의 회로패턴(12)에 융착되어 외부로 신호를 전달하는 솔더볼(40)과, 상기 반도체칩(20)과 그외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 몰딩수지물(50)을 포함하는 집적회로패키지에 있어서, 상기 회로기판(10)상의 다이패드(11)와 동일한 재질로 다이패드(11)와 유사한 표면적을 가지도록 회로기판(10)의 저면에 또 다른 다이패드(11a)를 형성함으로써 열팽창에 대한 패키지의 휨현상을 최소화시키는 것을 특징으로 하는 집적회로패키지의 휨현상 감소방법.A die pad 11 is formed at the center of the upper surface, a circuit pattern 12 is formed on the surface thereof, and a circuit board 10 coated with a solder mask 13 to protect the circuit pattern 12, and the circuit board. A semiconductor chip 20 attached to the die pad 11 of FIG. 10, a wire 30 connecting the semiconductor chip 20 and a circuit pattern 12 of the circuit board 10 to transmit a signal; The solder ball 40 fused to the circuit pattern 12 of the circuit board 10 to transmit a signal to the outside and the outside of the semiconductor chip 20 and other peripheral components to protect the semiconductor chip 20 and other peripheral components from external oxidation and corrosion. In the integrated circuit package including the wrapped molding resin 50, the bottom surface of the circuit board 10 to have a surface area similar to the die pad 11 of the same material as the die pad 11 on the circuit board 10; Minimizing the warpage of the package against thermal expansion by forming another die pad 11a in the A method for reducing warpage of an integrated circuit package as claimed. 상면 중앙에는 다이패드(11)가 형성되고, 표면에는 회로패턴(12)이 형성되며 상기 회로패턴(12)을 보호하기 위해 솔더마스크(13)가 코팅된 회로기판(10)과, 상기 회로기판(10)의 다이패드(11)에 부착된 반도체칩(20)과, 상기 반도체칩(20)과 회로기판(10)의 회로패턴(12)을 연결하여 신호를 전달하는 와이어(30)와, 상기 회로기판(10)의 회로패턴(12)에 융착되어 외부로 신호를 전달하는 솔더볼(40)과, 상기 반도체칩(20)과 그외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 몰딩수지물(50)을 포함하는 집적회로패키지에 있어서, 상기 회로기판(10)상의 다이패드(11) 위에 솔더마스크를 덮어 씌워 회로기판(10)의 상면과 하면에 도포된 각각의 솔더마스크(13)의 표면적을 유사하게 하여 줌으로써 열에 의한 패키지의 휨현상을 최소화시키는 것을 특징으로 하는 집적회로패키지의 휨현상 감소방법.A die pad 11 is formed at the center of the upper surface, a circuit pattern 12 is formed on the surface thereof, and a circuit board 10 coated with a solder mask 13 to protect the circuit pattern 12, and the circuit board. A semiconductor chip 20 attached to the die pad 11 of FIG. 10, a wire 30 connecting the semiconductor chip 20 and a circuit pattern 12 of the circuit board 10 to transmit a signal; The solder ball 40 fused to the circuit pattern 12 of the circuit board 10 to transmit a signal to the outside and the outside of the semiconductor chip 20 and other peripheral components to protect the semiconductor chip 20 and other peripheral components from external oxidation and corrosion. In the integrated circuit package including the wrapped molding resin 50, each solder mask applied to the upper and lower surfaces of the circuit board 10 by covering the solder mask on the die pad 11 on the circuit board 10. By similarizing the surface area of (13) to minimize the warpage of the package due to heat A method for reducing warpage of an integrated circuit package, characterized by.
KR1019970010103A 1993-08-18 1997-03-24 Reduction of warpage in integrated circuit packages KR0122847B1 (en)

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