JPWO2023199182A5 - - Google Patents

Info

Publication number
JPWO2023199182A5
JPWO2023199182A5 JP2024515180A JP2024515180A JPWO2023199182A5 JP WO2023199182 A5 JPWO2023199182 A5 JP WO2023199182A5 JP 2024515180 A JP2024515180 A JP 2024515180A JP 2024515180 A JP2024515180 A JP 2024515180A JP WO2023199182 A5 JPWO2023199182 A5 JP WO2023199182A5
Authority
JP
Japan
Prior art keywords
cache
substrate
layer
die
core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024515180A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2023199182A1 (https=
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/IB2023/053511 external-priority patent/WO2023199182A1/ja
Publication of JPWO2023199182A1 publication Critical patent/JPWO2023199182A1/ja
Publication of JPWO2023199182A5 publication Critical patent/JPWO2023199182A5/ja
Pending legal-status Critical Current

Links

JP2024515180A 2022-04-15 2023-04-06 Pending JPWO2023199182A1 (https=)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022067525 2022-04-15
PCT/IB2023/053511 WO2023199182A1 (ja) 2022-04-15 2023-04-06 半導体装置

Publications (2)

Publication Number Publication Date
JPWO2023199182A1 JPWO2023199182A1 (https=) 2023-10-19
JPWO2023199182A5 true JPWO2023199182A5 (https=) 2026-04-09

Family

ID=88329214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024515180A Pending JPWO2023199182A1 (https=) 2022-04-15 2023-04-06

Country Status (3)

Country Link
US (1) US20250208999A1 (https=)
JP (1) JPWO2023199182A1 (https=)
WO (1) WO2023199182A1 (https=)

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012185764A (ja) * 2011-03-08 2012-09-27 Nec Corp メモリアクセス処理システム、制御方法、及びプログラム
WO2013080426A1 (ja) * 2011-12-01 2013-06-06 パナソニック株式会社 熱を考慮した構造を持つ集積回路装置、三次元集積回路、三次元プロセッサ装置、及びプロセススケジューラ
US9152568B1 (en) * 2011-12-05 2015-10-06 Seagate Technology Llc Environmental-based device operation
US9853053B2 (en) * 2012-09-10 2017-12-26 3B Technologies, Inc. Three dimension integrated circuits employing thin film transistors
US9342135B2 (en) * 2013-10-11 2016-05-17 Qualcomm Incorporated Accelerated thermal mitigation for multi-core processors
US9443564B2 (en) * 2015-01-26 2016-09-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic component, and electronic device
KR102412243B1 (ko) * 2017-01-10 2022-06-23 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 동작 방법, 전자 부품, 및 전자 기기
US20180210836A1 (en) * 2017-01-24 2018-07-26 Microsoft Technology Licensing, Llc Thermal and reliability based cache slice migration
US12271306B2 (en) * 2021-03-27 2025-04-08 Intel Corporation Integrated three-dimensional (3D) DRAM cache

Similar Documents

Publication Publication Date Title
US9698049B2 (en) Nonvolatile memory device and method for fabricating the same
US10096612B2 (en) Three dimensional memory device having isolated periphery contacts through an active layer exhume process
JP2017034243A5 (ja) メモリセルの作製方法及び半導体装置の作製方法
JP2018116758A5 (https=)
JP2016054282A5 (https=)
JP2017191934A5 (https=)
JP2012068627A5 (ja) 半導体装置の作製方法
JP2012114148A5 (https=)
JPS5936262U (ja) 半導体メモリ素子
JP2013520844A5 (https=)
JP2013093573A5 (https=)
JP2009246352A5 (ja) 薄膜トランジスタの作製方法
US20180358317A1 (en) Wafer level package structure with internal conductive layer
JP2006173432A5 (https=)
CN104851910A (zh) 薄膜晶体管、阵列基板、制备方法、显示面板和显示装置
CN107431022B (zh) 具有带有整体附接结构的嵌入式迹线层的微电子衬底
TWI716420B (zh) 接觸電阻減輕
CN106653758A (zh) 快闪存储器的制作方法
JPWO2022249872A5 (https=)
JPWO2023199182A5 (https=)
CN103730374A (zh) 封装基板腔体的制作工艺
JP2006343755A5 (https=)
CN107331661B (zh) 一种cmos兼容的温度探测器及其制造方法
TWI467745B (zh) 非揮發性記憶體及其製作方法
JPWO2023285951A5 (https=)