JPWO2023199182A1 - - Google Patents

Info

Publication number
JPWO2023199182A1
JPWO2023199182A1 JP2024515180A JP2024515180A JPWO2023199182A1 JP WO2023199182 A1 JPWO2023199182 A1 JP WO2023199182A1 JP 2024515180 A JP2024515180 A JP 2024515180A JP 2024515180 A JP2024515180 A JP 2024515180A JP WO2023199182 A1 JPWO2023199182 A1 JP WO2023199182A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024515180A
Other languages
Japanese (ja)
Other versions
JPWO2023199182A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2023199182A1 publication Critical patent/JPWO2023199182A1/ja
Publication of JPWO2023199182A5 publication Critical patent/JPWO2023199182A5/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893Caches characterised by their organisation or structure
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1052Security improvement
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Thin Film Transistor (AREA)
JP2024515180A 2022-04-15 2023-04-06 Pending JPWO2023199182A1 (https=)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022067525 2022-04-15
PCT/IB2023/053511 WO2023199182A1 (ja) 2022-04-15 2023-04-06 半導体装置

Publications (2)

Publication Number Publication Date
JPWO2023199182A1 true JPWO2023199182A1 (https=) 2023-10-19
JPWO2023199182A5 JPWO2023199182A5 (https=) 2026-04-09

Family

ID=88329214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024515180A Pending JPWO2023199182A1 (https=) 2022-04-15 2023-04-06

Country Status (3)

Country Link
US (1) US20250208999A1 (https=)
JP (1) JPWO2023199182A1 (https=)
WO (1) WO2023199182A1 (https=)

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012185764A (ja) * 2011-03-08 2012-09-27 Nec Corp メモリアクセス処理システム、制御方法、及びプログラム
WO2013080426A1 (ja) * 2011-12-01 2013-06-06 パナソニック株式会社 熱を考慮した構造を持つ集積回路装置、三次元集積回路、三次元プロセッサ装置、及びプロセススケジューラ
US9152568B1 (en) * 2011-12-05 2015-10-06 Seagate Technology Llc Environmental-based device operation
US9853053B2 (en) * 2012-09-10 2017-12-26 3B Technologies, Inc. Three dimension integrated circuits employing thin film transistors
US9342135B2 (en) * 2013-10-11 2016-05-17 Qualcomm Incorporated Accelerated thermal mitigation for multi-core processors
US9443564B2 (en) * 2015-01-26 2016-09-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic component, and electronic device
KR102412243B1 (ko) * 2017-01-10 2022-06-23 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 동작 방법, 전자 부품, 및 전자 기기
US20180210836A1 (en) * 2017-01-24 2018-07-26 Microsoft Technology Licensing, Llc Thermal and reliability based cache slice migration
US12271306B2 (en) * 2021-03-27 2025-04-08 Intel Corporation Integrated three-dimensional (3D) DRAM cache

Also Published As

Publication number Publication date
US20250208999A1 (en) 2025-06-26
WO2023199182A1 (ja) 2023-10-19

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Legal Events

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