|
US4577293A
(en)
*
|
1984-06-01 |
1986-03-18 |
International Business Machines Corporation |
Distributed, on-chip cache
|
|
US4941201A
(en)
*
|
1985-01-13 |
1990-07-10 |
Abbott Laboratories |
Electronic data storage and retrieval apparatus and method
|
|
US5003459A
(en)
|
1988-04-01 |
1991-03-26 |
Digital Equipment Corporation |
Cache memory system
|
|
KR920009192B1
(ko)
*
|
1989-12-26 |
1992-10-14 |
재단법인한국전자 통신연구소 |
다중처리 시스템의 스눕 인터페이스 방법 및 그 장치
|
|
US5412799A
(en)
*
|
1990-02-27 |
1995-05-02 |
Massachusetts Institute Of Technology |
Efficient data processor instrumentation for systematic program debugging and development
|
|
US5256293A
(en)
|
1991-09-20 |
1993-10-26 |
Research Corporation Technologies, Inc. |
Separation of enantiomers of non-steroidal anti-inflammatory drugs and chiral selector therefor
|
|
US5325503A
(en)
*
|
1992-02-21 |
1994-06-28 |
Compaq Computer Corporation |
Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line
|
|
JPH05342107A
(ja)
*
|
1992-06-11 |
1993-12-24 |
Fujitsu Ltd |
キャッシュメモリ制御装置
|
|
US5418973A
(en)
*
|
1992-06-22 |
1995-05-23 |
Digital Equipment Corporation |
Digital computer system with cache controller coordinating both vector and scalar operations
|
|
US6219773B1
(en)
*
|
1993-10-18 |
2001-04-17 |
Via-Cyrix, Inc. |
System and method of retiring misaligned write operands from a write buffer
|
|
US5687338A
(en)
*
|
1994-03-01 |
1997-11-11 |
Intel Corporation |
Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor
|
|
US5826052A
(en)
*
|
1994-04-29 |
1998-10-20 |
Advanced Micro Devices, Inc. |
Method and apparatus for concurrent access to multiple physical caches
|
|
US5644752A
(en)
*
|
1994-06-29 |
1997-07-01 |
Exponential Technology, Inc. |
Combined store queue for a master-slave cache system
|
|
US5561782A
(en)
*
|
1994-06-30 |
1996-10-01 |
Intel Corporation |
Pipelined cache system having low effective latency for nonsequential accesses
|
|
US5577227A
(en)
*
|
1994-08-04 |
1996-11-19 |
Finnell; James S. |
Method for decreasing penalty resulting from a cache miss in multi-level cache system
|
|
DE69616402T2
(de)
*
|
1995-03-31 |
2002-07-18 |
Sun Microsystems, Inc. |
Schnelle Zweitor-Cachesteuerungsschaltung für Datenprozessoren in einem paketvermittelten cachekohärenten Multiprozessorsystem
|
|
US5651136A
(en)
*
|
1995-06-06 |
1997-07-22 |
International Business Machines Corporation |
System and method for increasing cache efficiency through optimized data allocation
|
|
US5706467A
(en)
*
|
1995-09-05 |
1998-01-06 |
Emc Corporation |
Sequential cache management system utilizing the establishment of a microcache and managing the contents of such according to a threshold comparison
|
|
JPH09114734A
(ja)
*
|
1995-10-16 |
1997-05-02 |
Hitachi Ltd |
ストアバッファ装置
|
|
US5809228A
(en)
*
|
1995-12-27 |
1998-09-15 |
Intel Corporaiton |
Method and apparatus for combining multiple writes to a memory resource utilizing a write buffer
|
|
US5822755A
(en)
*
|
1996-01-25 |
1998-10-13 |
International Business Machines Corporation |
Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache
|
|
US5758056A
(en)
*
|
1996-02-08 |
1998-05-26 |
Barr; Robert C. |
Memory system having defective address identification and replacement
|
|
JP3429948B2
(ja)
*
|
1996-04-10 |
2003-07-28 |
株式会社日立製作所 |
組込み型ｃｐｕ用制御装置
|
|
US20010034808A1
(en)
*
|
1996-07-19 |
2001-10-25 |
Atsushi Nakajima |
Cache memory device and information processing system
|
|
US6038645A
(en)
*
|
1996-08-28 |
2000-03-14 |
Texas Instruments Incorporated |
Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache
|
|
US5860107A
(en)
*
|
1996-10-07 |
1999-01-12 |
International Business Machines Corporation |
Processor and method for store gathering through merged store operations
|
|
KR100190379B1
(ko)
|
1996-11-06 |
1999-06-01 |
김영환 |
쓰기 사이클의 성능 향상을 위한 프로세서
|
|
US5978888A
(en)
*
|
1997-04-14 |
1999-11-02 |
International Business Machines Corporation |
Hardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels
|
|
US5894569A
(en)
*
|
1997-04-14 |
1999-04-13 |
International Business Machines Corporation |
Method and system for back-end gathering of store instructions within a data-processing system
|
|
US6173371B1
(en)
*
|
1997-04-14 |
2001-01-09 |
International Business Machines Corporation |
Demand-based issuance of cache operations to a processor bus
|
|
US5935233A
(en)
*
|
1997-05-21 |
1999-08-10 |
Micron Electronics, Inc. |
Computer system with a switch interconnector for computer devices
|
|
US6085294A
(en)
*
|
1997-10-24 |
2000-07-04 |
Compaq Computer Corporation |
Distributed data dependency stall mechanism
|
|
US6078992A
(en)
|
1997-12-05 |
2000-06-20 |
Intel Corporation |
Dirty line cache
|
|
US6226713B1
(en)
|
1998-01-21 |
2001-05-01 |
Sun Microsystems, Inc. |
Apparatus and method for queueing structures in a multi-level non-blocking cache subsystem
|
|
US6195729B1
(en)
*
|
1998-02-17 |
2001-02-27 |
International Business Machines Corporation |
Deallocation with cache update protocol (L2 evictions)
|
|
US6289438B1
(en)
*
|
1998-07-29 |
2001-09-11 |
Kabushiki Kaisha Toshiba |
Microprocessor cache redundancy scheme using store buffer
|
|
US6215497B1
(en)
*
|
1998-08-12 |
2001-04-10 |
Monolithic System Technology, Inc. |
Method and apparatus for maximizing the random access bandwidth of a multi-bank DRAM in a computer graphics system
|
|
US6243791B1
(en)
*
|
1998-08-13 |
2001-06-05 |
Hewlett-Packard Company |
Method and architecture for data coherency in set-associative caches including heterogeneous cache sets having different characteristics
|
|
ATE294415T1
(de)
*
|
1998-09-01 |
2005-05-15 |
Texas Instruments Inc |
Verbesserte speicherhierarchie für prozessoren und koherenzprotokoll hierfür
|
|
US6397296B1
(en)
*
|
1999-02-19 |
2002-05-28 |
Hitachi Ltd. |
Two-level instruction cache for embedded processors
|
|
US6366984B1
(en)
*
|
1999-05-11 |
2002-04-02 |
Intel Corporation |
Write combining buffer that supports snoop request
|
|
FR2795196B1
(fr)
*
|
1999-06-21 |
2001-08-10 |
Bull Sa |
Processus de liberation de pages physiques pour mecanisme d'adressage virtuel
|
|
US6446166B1
(en)
*
|
1999-06-25 |
2002-09-03 |
International Business Machines Corporation |
Method for upper level cache victim selection management by a lower level cache
|
|
US6484237B1
(en)
*
|
1999-07-15 |
2002-11-19 |
Texas Instruments Incorporated |
Unified multilevel memory system architecture which supports both cache and addressable SRAM
|
|
US6609171B1
(en)
*
|
1999-12-29 |
2003-08-19 |
Intel Corporation |
Quad pumped bus architecture and protocol
|
|
US6633299B1
(en)
*
|
2000-01-10 |
2003-10-14 |
Intel Corporation |
Method and apparatus for implementing smart allocation policies for a small frame buffer cache serving 3D and 2D streams
|
|
JP2001249846A
(ja)
*
|
2000-03-03 |
2001-09-14 |
Hitachi Ltd |
キャッシュメモリ装置及びデータ処理システム
|
|
US20020087821A1
(en)
*
|
2000-03-08 |
2002-07-04 |
Ashley Saulsbury |
VLIW computer processing architecture with on-chip DRAM usable as physical memory or cache memory
|
|
US6513104B1
(en)
*
|
2000-03-29 |
2003-01-28 |
I.P-First, Llc |
Byte-wise write allocate with retry tracking
|
|
JP3498673B2
(ja)
|
2000-04-05 |
2004-02-16 |
日本電気株式会社 |
記憶装置
|
|
US6751720B2
(en)
*
|
2000-06-10 |
2004-06-15 |
Hewlett-Packard Development Company, L.P. |
Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy
|
|
JP2002007209A
(ja)
|
2000-06-26 |
2002-01-11 |
Fujitsu Ltd |
データ処理装置
|
|
US20020069341A1
(en)
*
|
2000-08-21 |
2002-06-06 |
Gerard Chauvel |
Multilevel cache architecture and data transfer
|
|
EP1182570A3
(en)
*
|
2000-08-21 |
2004-08-04 |
Texas Instruments Incorporated |
TLB with resource ID field
|
|
US7099913B1
(en)
*
|
2000-08-31 |
2006-08-29 |
Hewlett-Packard Development Company, L.P. |
Speculative directory writes in a directory based cache coherent nonuniform memory access protocol
|
|
JP2002108702A
(ja)
*
|
2000-10-03 |
2002-04-12 |
Hitachi Ltd |
マイクロコンピュータ及びデータ処理装置
|
|
US6546461B1
(en)
*
|
2000-11-22 |
2003-04-08 |
Integrated Device Technology, Inc. |
Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices therein
|
|
JP2002163150A
(ja)
*
|
2000-11-28 |
2002-06-07 |
Toshiba Corp |
プロセッサ
|
|
US6732236B2
(en)
*
|
2000-12-18 |
2004-05-04 |
Redback Networks Inc. |
Cache retry request queue
|
|
US6766389B2
(en)
|
2001-05-18 |
2004-07-20 |
Broadcom Corporation |
System on a chip for networking
|
|
US6775750B2
(en)
|
2001-06-29 |
2004-08-10 |
Texas Instruments Incorporated |
System protection map
|
|
US6839808B2
(en)
*
|
2001-07-06 |
2005-01-04 |
Juniper Networks, Inc. |
Processing cluster having multiple compute engines and shared tier one caches
|
|
US6587929B2
(en)
*
|
2001-07-31 |
2003-07-01 |
Ip-First, L.L.C. |
Apparatus and method for performing write-combining in a pipelined microprocessor using tags
|
|
US7085955B2
(en)
*
|
2001-09-14 |
2006-08-01 |
Hewlett-Packard Development Company, L.P. |
Checkpointing with a write back controller
|
|
US6810465B2
(en)
*
|
2001-10-31 |
2004-10-26 |
Hewlett-Packard Development Company, L.P. |
Limiting the number of dirty entries in a computer cache
|
|
JP2003196084A
(ja)
|
2001-12-25 |
2003-07-11 |
Toshiba Corp |
リードモディファイライトユニットを有するシステム
|
|
US20030182539A1
(en)
*
|
2002-03-20 |
2003-09-25 |
International Business Machines Corporation |
Storing execution results of mispredicted paths in a superscalar computer processor
|
|
US6912628B2
(en)
|
2002-04-22 |
2005-06-28 |
Sun Microsystems Inc. |
N-way set-associative external cache with standard DDR memory devices
|
|
US7937559B1
(en)
*
|
2002-05-13 |
2011-05-03 |
Tensilica, Inc. |
System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes
|
|
US7308540B2
(en)
*
|
2002-05-24 |
2007-12-11 |
Koninklijke Philips Electronics N.V. |
Pseudo multiport data memory has stall facility
|
|
JP4262680B2
(ja)
*
|
2002-10-04 |
2009-05-13 |
エヌエックスピー ビー ヴィ |
データ処理システムおよび同システムを動作させる方法
|
|
US7290093B2
(en)
*
|
2003-01-07 |
2007-10-30 |
Intel Corporation |
Cache memory to support a processor's power mode of operation
|
|
US6976125B2
(en)
*
|
2003-01-29 |
2005-12-13 |
Sun Microsystems, Inc. |
Method and apparatus for predicting hot spots in cache memories
|
|
US7571287B2
(en)
*
|
2003-03-13 |
2009-08-04 |
Marvell World Trade Ltd. |
Multiport memory architecture, devices and systems including the same, and methods of using the same
|
|
US6880047B2
(en)
*
|
2003-03-28 |
2005-04-12 |
Emulex Design & Manufacturing Corporation |
Local emulation of data RAM utilizing write-through cache hardware within a CPU module
|
|
US6976132B2
(en)
*
|
2003-03-28 |
2005-12-13 |
International Business Machines Corporation |
Reducing latency of a snoop tenure
|
|
US20040199722A1
(en)
*
|
2003-04-03 |
2004-10-07 |
International Business Machines Corp. |
Method and apparatus for performing bus tracing in a data processing system having a distributed memory
|
|
TWI246658B
(en)
*
|
2003-04-25 |
2006-01-01 |
Ip First Llc |
Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status
|
|
ITRM20030354A1
(it)
*
|
2003-07-17 |
2005-01-18 |
Micron Technology Inc |
Unita' di controllo per dispositivo di memoria.
|
|
US7240277B2
(en)
*
|
2003-09-26 |
2007-07-03 |
Texas Instruments Incorporated |
Memory error detection reporting
|
|
WO2005066830A1
(en)
*
|
2004-01-08 |
2005-07-21 |
Agency For Science, Technology & Research |
A shared storage network system and a method for operating a shared storage network system
|
|
US7308526B2
(en)
*
|
2004-06-02 |
2007-12-11 |
Intel Corporation |
Memory controller module having independent memory controllers for different memory types
|
|
US7277982B2
(en)
*
|
2004-07-27 |
2007-10-02 |
International Business Machines Corporation |
DRAM access command queuing structure
|
|
US20060036817A1
(en)
*
|
2004-08-10 |
2006-02-16 |
Oza Alpesh B |
Method and system for supporting memory unaligned writes in a memory controller
|
|
US8775740B2
(en)
*
|
2004-08-30 |
2014-07-08 |
Texas Instruments Incorporated |
System and method for high performance, power efficient store buffer forwarding
|
|
US7360035B2
(en)
*
|
2004-09-01 |
2008-04-15 |
International Business Machines Corporation |
Atomic read/write support in a multi-module memory configuration
|
|
US7606998B2
(en)
*
|
2004-09-10 |
2009-10-20 |
Cavium Networks, Inc. |
Store instruction ordering for multi-core processor
|
|
JP2006091995A
(ja)
*
|
2004-09-21 |
2006-04-06 |
Toshiba Microelectronics Corp |
キャッシュメモリのライトバック装置
|
|
US7716424B2
(en)
*
|
2004-11-16 |
2010-05-11 |
International Business Machines Corporation |
Victim prefetching in a cache hierarchy
|
|
US20060143396A1
(en)
|
2004-12-29 |
2006-06-29 |
Mason Cabot |
Method for programmer-controlled cache line eviction policy
|
|
US8103749B2
(en)
*
|
2005-01-05 |
2012-01-24 |
Yissum Research Development Company Of The Hebrew University Of Jerusalem |
Method and apparatus for managing communications
|
|
US20060179231A1
(en)
|
2005-02-07 |
2006-08-10 |
Advanced Micron Devices, Inc. |
System having cache memory and method of accessing
|
|
US7490200B2
(en)
*
|
2005-02-10 |
2009-02-10 |
International Business Machines Corporation |
L2 cache controller with slice directory and unified cache structure
|
|
JP2006260378A
(ja)
*
|
2005-03-18 |
2006-09-28 |
Seiko Epson Corp |
半導体集積回路
|
|
US7386685B2
(en)
|
2005-03-29 |
2008-06-10 |
International Busniess Machines Corporation |
Method and apparatus for filtering snoop requests using multiple snoop caches
|
|
US7970998B2
(en)
*
|
2005-04-08 |
2011-06-28 |
Panasonic Corporation |
Parallel caches operating in exclusive address ranges
|
|
US20070005842A1
(en)
*
|
2005-05-16 |
2007-01-04 |
Texas Instruments Incorporated |
Systems and methods for stall monitoring
|
|
US20060277352A1
(en)
*
|
2005-06-07 |
2006-12-07 |
Fong Pong |
Method and system for supporting large caches with split and canonicalization tags
|
|
US7711988B2
(en)
*
|
2005-06-15 |
2010-05-04 |
The Board Of Trustees Of The University Of Illinois |
Architecture support system and method for memory monitoring
|
|
US8019944B1
(en)
*
|
2005-09-28 |
2011-09-13 |
Oracle America, Inc. |
Checking for a memory ordering violation after a speculative cache write
|
|
US7779307B1
(en)
*
|
2005-09-28 |
2010-08-17 |
Oracle America, Inc. |
Memory ordering queue tightly coupled with a versioning cache circuit
|
|
US7437510B2
(en)
*
|
2005-09-30 |
2008-10-14 |
Intel Corporation |
Instruction-assisted cache management for efficient use of cache and memory
|
|
US20070094450A1
(en)
*
|
2005-10-26 |
2007-04-26 |
International Business Machines Corporation |
Multi-level cache architecture having a selective victim cache
|
|
JP4832862B2
(ja)
*
|
2005-11-18 |
2011-12-07 |
株式会社日立製作所 |
ディスクアレイシステム及びセキュリティ方法
|
|
US8327075B2
(en)
*
|
2005-12-08 |
2012-12-04 |
International Business Machines Corporation |
Methods and apparatus for handling a cache miss
|
|
US7613941B2
(en)
*
|
2005-12-29 |
2009-11-03 |
Intel Corporation |
Mechanism for self refresh during advanced configuration and power interface (ACPI) standard C0 power state
|
|
WO2007116612A1
(ja)
*
|
2006-03-31 |
2007-10-18 |
Matsushita Electric Industrial Co., Ltd. |
コマンド出力制御装置
|
|
US7461210B1
(en)
*
|
2006-04-14 |
2008-12-02 |
Tilera Corporation |
Managing set associative cache memory according to entry type
|
|
US8407395B2
(en)
*
|
2006-08-22 |
2013-03-26 |
Mosaid Technologies Incorporated |
Scalable memory system
|
|
US8495308B2
(en)
*
|
2006-10-09 |
2013-07-23 |
International Business Machines Corporation |
Processor, data processing system and method supporting a shared global coherency state
|
|
KR101086417B1
(ko)
|
2006-11-27 |
2011-11-25 |
삼성전자주식회사 |
다이내믹 랜덤 액세스 메모리의 부분 액세스 장치 및 방법
|
|
CN101558391B
(zh)
*
|
2006-12-15 |
2013-10-16 |
密克罗奇普技术公司 |
用于微处理器的可配置高速缓冲存储器
|
|
US7539062B2
(en)
*
|
2006-12-20 |
2009-05-26 |
Micron Technology, Inc. |
Interleaved memory program and verify method, device and system
|
|
US7996632B1
(en)
*
|
2006-12-22 |
2011-08-09 |
Oracle America, Inc. |
Device for misaligned atomics for a highly-threaded x86 processor
|
|
JP5010271B2
(ja)
|
2006-12-27 |
2012-08-29 |
富士通株式会社 |
エラー訂正コード生成方法、およびメモリ制御装置
|
|
US7620780B1
(en)
*
|
2007-01-23 |
2009-11-17 |
Xilinx, Inc. |
Multiprocessor system with cache controlled scatter-gather operations
|
|
US7660967B2
(en)
*
|
2007-02-01 |
2010-02-09 |
Efficient Memory Technology |
Result data forwarding in parallel vector data processor based on scalar operation issue order
|
|
US7945840B2
(en)
*
|
2007-02-12 |
2011-05-17 |
Micron Technology, Inc. |
Memory array error correction apparatus, systems, and methods
|
|
JP2008234806A
(ja)
*
|
2007-03-23 |
2008-10-02 |
Toshiba Corp |
半導体記憶装置およびそのリダンダンシ方法
|
|
US20080244190A1
(en)
*
|
2007-03-30 |
2008-10-02 |
Shedivy David A |
Method, Apparatus, System and Program Product Supporting Efficient Eviction of an Entry From a Central Coherence Directory
|
|
US7836262B2
(en)
*
|
2007-06-05 |
2010-11-16 |
Apple Inc. |
Converting victim writeback to a fill
|
|
WO2008155844A1
(ja)
|
2007-06-20 |
2008-12-24 |
Fujitsu Limited |
情報処理装置およびキャッシュ制御方法
|
|
US8166246B2
(en)
*
|
2008-01-31 |
2012-04-24 |
International Business Machines Corporation |
Chaining multiple smaller store queue entries for more efficient store queue usage
|
|
KR100947178B1
(ko)
*
|
2008-02-01 |
2010-03-12 |
엠텍비젼 주식회사 |
카메라 시리얼 통신 인터페이스와 디스플레이 시리얼 통신인터페이스의 통합구조를 가지는 인터페이스 통합 장치
|
|
CN102016810A
(zh)
*
|
2008-04-22 |
2011-04-13 |
Nxp股份有限公司 |
具有允许写入未预先加载的高速缓存行的高速缓存电路的多处理电路
|
|
US7814300B2
(en)
*
|
2008-04-30 |
2010-10-12 |
Freescale Semiconductor, Inc. |
Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access
|
|
US9146744B2
(en)
*
|
2008-05-06 |
2015-09-29 |
Oracle America, Inc. |
Store queue having restricted and unrestricted entries
|
|
US7934080B2
(en)
*
|
2008-05-28 |
2011-04-26 |
Oracle America, Inc. |
Aggressive store merging in a processor that supports checkpointing
|
|
US8117395B1
(en)
*
|
2008-06-25 |
2012-02-14 |
Marvell Israel (Misl) Ltd. |
Multi-stage pipeline for cache access
|
|
US8327072B2
(en)
|
2008-07-23 |
2012-12-04 |
International Business Machines Corporation |
Victim cache replacement
|
|
US8943273B1
(en)
*
|
2008-08-14 |
2015-01-27 |
Marvell International Ltd. |
Method and apparatus for improving cache efficiency
|
|
US8181005B2
(en)
|
2008-09-05 |
2012-05-15 |
Advanced Micro Devices, Inc. |
Hybrid branch prediction device with sparse and dense prediction caches
|
|
US8782348B2
(en)
*
|
2008-09-09 |
2014-07-15 |
Via Technologies, Inc. |
Microprocessor cache line evict array
|
|
TW201017421A
(en)
*
|
2008-09-24 |
2010-05-01 |
Panasonic Corp |
Cache memory, memory system and control method therefor
|
|
US8225045B2
(en)
*
|
2008-12-16 |
2012-07-17 |
International Business Machines Corporation |
Lateral cache-to-cache cast-in
|
|
US9053030B2
(en)
*
|
2009-01-28 |
2015-06-09 |
Nec Corporation |
Cache memory and control method thereof with cache hit rate
|
|
US8259520B2
(en)
*
|
2009-03-13 |
2012-09-04 |
Unity Semiconductor Corporation |
Columnar replacement of defective memory cells
|
|
US8117390B2
(en)
*
|
2009-04-15 |
2012-02-14 |
International Business Machines Corporation |
Updating partial cache lines in a data processing system
|
|
US9183145B2
(en)
*
|
2009-04-27 |
2015-11-10 |
Intel Corporation |
Data caching in a network communications processor architecture
|
|
US8095734B2
(en)
|
2009-04-30 |
2012-01-10 |
Lsi Corporation |
Managing cache line allocations for multiple issue processors
|
|
US8533388B2
(en)
*
|
2009-06-15 |
2013-09-10 |
Broadcom Corporation |
Scalable multi-bank memory architecture
|
|
US8296526B2
(en)
*
|
2009-06-17 |
2012-10-23 |
Mediatek, Inc. |
Shared memory having multiple access configurations
|
|
JP5413001B2
(ja)
*
|
2009-07-09 |
2014-02-12 |
富士通株式会社 |
キャッシュメモリ
|
|
US8244981B2
(en)
*
|
2009-07-10 |
2012-08-14 |
Apple Inc. |
Combined transparent/non-transparent cache
|
|
US8392661B1
(en)
*
|
2009-09-21 |
2013-03-05 |
Tilera Corporation |
Managing cache coherence
|
|
US8595425B2
(en)
*
|
2009-09-25 |
2013-11-26 |
Nvidia Corporation |
Configurable cache for multiple clients
|
|
US8688901B2
(en)
*
|
2009-12-08 |
2014-04-01 |
Intel Corporation |
Reconfigurable load-reduced memory buffer
|
|
US20110149661A1
(en)
*
|
2009-12-18 |
2011-06-23 |
Rajwani Iqbal R |
Memory array having extended write operation
|
|
US9081501B2
(en)
*
|
2010-01-08 |
2015-07-14 |
International Business Machines Corporation |
Multi-petascale highly efficient parallel supercomputer
|
|
US9507647B2
(en)
*
|
2010-01-08 |
2016-11-29 |
Globalfoundries Inc. |
Cache as point of coherence in multiprocessor system
|
|
US8341353B2
(en)
*
|
2010-01-14 |
2012-12-25 |
Qualcomm Incorporated |
System and method to access a portion of a level two memory and a level one memory
|
|
US8370582B2
(en)
*
|
2010-01-26 |
2013-02-05 |
Hewlett-Packard Development Company, L.P. |
Merging subsequent updates to a memory location
|
|
US8429374B2
(en)
*
|
2010-01-28 |
2013-04-23 |
Sony Corporation |
System and method for read-while-write with NAND memory device
|
|
US8621145B1
(en)
*
|
2010-01-29 |
2013-12-31 |
Netapp, Inc. |
Concurrent content management and wear optimization for a non-volatile solid-state cache
|
|
US20130117838A1
(en)
*
|
2010-02-11 |
2013-05-09 |
Timothy Evert LEVIN |
Superpositional Control of Integrated Circuit Processing
|
|
US8514235B2
(en)
*
|
2010-04-21 |
2013-08-20 |
Via Technologies, Inc. |
System and method for managing the computation of graphics shading operations
|
|
JP5650441B2
(ja)
*
|
2010-06-07 |
2015-01-07 |
キヤノン株式会社 |
演算装置、キャッシュ装置、その制御方法及びコンピュータプログラム
|
|
US8751745B2
(en)
|
2010-08-11 |
2014-06-10 |
Advanced Micro Devices, Inc. |
Method for concurrent flush of L1 and L2 caches
|
|
US8352685B2
(en)
*
|
2010-08-20 |
2013-01-08 |
Apple Inc. |
Combining write buffer with dynamically adjustable flush metrics
|
|
US20120079245A1
(en)
*
|
2010-09-25 |
2012-03-29 |
Cheng Wang |
Dynamic optimization for conditional commit
|
|
US8904115B2
(en)
|
2010-09-28 |
2014-12-02 |
Texas Instruments Incorporated |
Cache with multiple access pipelines
|
|
US8756374B2
(en)
*
|
2010-11-05 |
2014-06-17 |
Oracle International Corporation |
Store queue supporting ordered and unordered stores
|
|
US8572325B2
(en)
*
|
2010-12-07 |
2013-10-29 |
International Business Machines Corporation |
Dynamic adjustment of read/write ratio of a disk cache
|
|
WO2012116369A2
(en)
|
2011-02-25 |
2012-08-30 |
Fusion-Io, Inc. |
Apparatus, system, and method for managing contents of a cache
|
|
US9547593B2
(en)
*
|
2011-02-28 |
2017-01-17 |
Nxp Usa, Inc. |
Systems and methods for reconfiguring cache memory
|
|
JP2012203729A
(ja)
*
|
2011-03-25 |
2012-10-22 |
Fujitsu Ltd |
演算処理装置および演算処理装置の制御方法
|
|
US9229879B2
(en)
*
|
2011-07-11 |
2016-01-05 |
Intel Corporation |
Power reduction using unmodified information in evicted cache lines
|
|
JP5524144B2
(ja)
*
|
2011-08-08 |
2014-06-18 |
株式会社東芝 |
ｋｅｙ−ｖａｌｕｅストア方式を有するメモリシステム
|
|
JP5674613B2
(ja)
*
|
2011-09-22 |
2015-02-25 |
株式会社東芝 |
制御システム、制御方法およびプログラム
|
|
US9330002B2
(en)
*
|
2011-10-31 |
2016-05-03 |
Cavium, Inc. |
Multi-core interconnect in a network processor
|
|
US8634221B2
(en)
*
|
2011-11-01 |
2014-01-21 |
Avago Technologies General Ip (Singapore) Pte. Ltd. |
Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer and that utilizes a SerDes interface to interface a memory controller with an integrated circuit, and a method
|
|
US8966457B2
(en)
*
|
2011-11-15 |
2015-02-24 |
Global Supercomputing Corporation |
Method and system for converting a single-threaded software program into an application-specific supercomputer
|
|
US9928179B2
(en)
*
|
2011-12-16 |
2018-03-27 |
Intel Corporation |
Cache replacement policy
|
|
WO2013095381A1
(en)
*
|
2011-12-20 |
2013-06-27 |
Intel Corporation |
Method and system for data de-duplication
|
|
US9251086B2
(en)
|
2012-01-24 |
2016-02-02 |
SanDisk Technologies, Inc. |
Apparatus, system, and method for managing a cache
|
|
JP5565425B2
(ja)
*
|
2012-02-29 |
2014-08-06 |
富士通株式会社 |
演算装置、情報処理装置および演算方法
|
|
US11024352B2
(en)
*
|
2012-04-10 |
2021-06-01 |
Samsung Electronics Co., Ltd. |
Memory system for access concentration decrease management and access concentration decrease method
|
|
US20130321439A1
(en)
*
|
2012-05-31 |
2013-12-05 |
Allen B. Goodrich |
Method and apparatus for accessing video data for efficient data transfer and memory cache performance
|
|
CN104508646A
(zh)
*
|
2012-06-08 |
2015-04-08 |
惠普发展公司，有限责任合伙企业 |
访问存储器
|
|
US8904100B2
(en)
*
|
2012-06-11 |
2014-12-02 |
International Business Machines Corporation |
Process identifier-based cache data transfer
|
|
US9092359B2
(en)
*
|
2012-06-14 |
2015-07-28 |
International Business Machines Corporation |
Identification and consolidation of page table entries
|
|
JP6011194B2
(ja)
|
2012-09-21 |
2016-10-19 |
富士通株式会社 |
演算処理装置及び演算処理装置の制御方法
|
|
US9639469B2
(en)
*
|
2012-09-28 |
2017-05-02 |
Qualcomm Technologies, Inc. |
Coherency controller with reduced data buffer
|
|
US10169091B2
(en)
*
|
2012-10-25 |
2019-01-01 |
Nvidia Corporation |
Efficient memory virtualization in multi-threaded processing units
|
|
US9158725B2
(en)
*
|
2012-11-20 |
2015-10-13 |
Freescale Semiconductor, Inc. |
Flexible control mechanism for store gathering in a write buffer
|
|
US9170955B2
(en)
|
2012-11-27 |
2015-10-27 |
Intel Corporation |
Providing extended cache replacement state information
|
|
US20140149684A1
(en)
*
|
2012-11-29 |
2014-05-29 |
Samsung Electronics Co., Ltd. |
Apparatus and method of controlling cache
|
|
US9612972B2
(en)
*
|
2012-12-03 |
2017-04-04 |
Micron Technology, Inc. |
Apparatuses and methods for pre-fetching and write-back for a segmented cache memory
|
|
US9244841B2
(en)
|
2012-12-31 |
2016-01-26 |
Advanced Micro Devices, Inc. |
Merging eviction and fill buffers for cache line transactions
|
|
US9317433B1
(en)
*
|
2013-01-14 |
2016-04-19 |
Marvell Israel (M.I.S.L.) Ltd. |
Multi-core processing system having cache coherency in dormant mode
|
|
US8984230B2
(en)
*
|
2013-01-30 |
2015-03-17 |
Hewlett-Packard Development Company, L.P. |
Method of using a buffer within an indexing accelerator during periods of inactivity
|
|
US9189422B2
(en)
*
|
2013-02-07 |
2015-11-17 |
Avago Technologies General Ip (Singapore) Pte. Ltd. |
Method to throttle rate of data caching for improved I/O performance
|
|
US9324128B2
(en)
*
|
2013-03-14 |
2016-04-26 |
Intel Corporation |
Techniques for improving rendering efficiency
|
|
US9489204B2
(en)
*
|
2013-03-15 |
2016-11-08 |
Qualcomm Incorporated |
Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process
|
|
US9223710B2
(en)
*
|
2013-03-16 |
2015-12-29 |
Intel Corporation |
Read-write partitioning of cache memory
|
|
US9361240B2
(en)
*
|
2013-04-12 |
2016-06-07 |
International Business Machines Corporation |
Dynamic reservations in a unified request queue
|
|
US20150006820A1
(en)
|
2013-06-28 |
2015-01-01 |
Texas Instruments Incorporated |
Dynamic management of write-miss buffer to reduce write-miss traffic
|
|
US10061675B2
(en)
*
|
2013-07-15 |
2018-08-28 |
Texas Instruments Incorporated |
Streaming engine with deferred exception reporting
|
|
US9606803B2
(en)
|
2013-07-15 |
2017-03-28 |
Texas Instruments Incorporated |
Highly integrated scalable, flexible DSP megamodule architecture
|
|
US8704842B1
(en)
*
|
2013-07-17 |
2014-04-22 |
Spinella Ip Holdings, Inc. |
System and method for histogram computation using a graphics processing unit
|
|
WO2015010327A1
(zh)
*
|
2013-07-26 |
2015-01-29 |
华为技术有限公司 |
数据发送方法、数据接收方法和存储设备
|
|
US9092345B2
(en)
*
|
2013-08-08 |
2015-07-28 |
Arm Limited |
Data processing systems
|
|
US9612961B2
(en)
*
|
2013-08-29 |
2017-04-04 |
Empire Technology Development Llc |
Cache partitioning in a multicore processor
|
|
US9710380B2
(en)
*
|
2013-08-29 |
2017-07-18 |
Intel Corporation |
Managing shared cache by multi-core processor
|
|
JP6088951B2
(ja)
*
|
2013-09-20 |
2017-03-01 |
株式会社東芝 |
キャッシュメモリシステムおよびプロセッサシステム
|
|
US9645938B2
(en)
*
|
2013-09-27 |
2017-05-09 |
Intel Corporation |
Cache operations for memory management
|
|
WO2015057828A1
(en)
*
|
2013-10-15 |
2015-04-23 |
Mill Computing, Inc. |
Computer processor employing cache memory storing backless cache lines
|
|
TWI514145B
(zh)
*
|
2013-10-21 |
2015-12-21 |
Univ Nat Sun Yat Sen |
可儲存除錯資料的處理器、其快取及控制方法
|
|
JP6179369B2
(ja)
|
2013-11-22 |
2017-08-16 |
富士通株式会社 |
演算処理装置及び演算処理装置の制御方法
|
|
GB2520942A
(en)
*
|
2013-12-03 |
2015-06-10 |
Ibm |
Data Processing system and method for data processing in a multiple processor system
|
|
US10216632B2
(en)
*
|
2013-12-30 |
2019-02-26 |
Michael Henry Kass |
Memory system cache eviction policies
|
|
WO2015101827A1
(en)
*
|
2013-12-31 |
2015-07-09 |
Mosys, Inc. |
Integrated main memory and coprocessor with low latency
|
|
US9436972B2
(en)
*
|
2014-03-27 |
2016-09-06 |
Intel Corporation |
System coherency in a distributed graphics processor hierarchy
|
|
US9342403B2
(en)
*
|
2014-03-28 |
2016-05-17 |
Intel Corporation |
Method and apparatus for managing a spin transfer torque memory
|
|
US9483310B2
(en)
*
|
2014-04-29 |
2016-11-01 |
Bluedata Software, Inc. |
Associating cache memory with a work process
|
|
WO2015165055A1
(zh)
*
|
2014-04-30 |
2015-11-05 |
华为技术有限公司 |
存储数据的方法、内存控制器和中央处理器
|
|
US9864007B2
(en)
*
|
2014-04-30 |
2018-01-09 |
Duke University |
Software-based self-test and diagnosis using on-chip memory
|
|
US9696920B2
(en)
*
|
2014-06-02 |
2017-07-04 |
Micron Technology, Inc. |
Systems and methods for improving efficiencies of a memory system
|
|
US9691452B2
(en)
*
|
2014-08-15 |
2017-06-27 |
Micron Technology, Inc. |
Apparatuses and methods for concurrently accessing different memory planes of a memory
|
|
GB2549239A
(en)
*
|
2014-11-13 |
2017-10-18 |
Advanced Risc Mach Ltd |
Context sensitive barriers in data processing
|
|
KR102014624B1
(ko)
*
|
2014-12-19 |
2019-11-04 |
마이크론 테크놀로지, 인크. |
오류 정정 코딩이 있는 메모리 연산을 파이프라이닝하기 위한 방법 및 장치
|
|
US9690710B2
(en)
*
|
2015-01-15 |
2017-06-27 |
Qualcomm Incorporated |
System and method for improving a victim cache mode in a portable computing device
|
|
US9696934B2
(en)
*
|
2015-02-12 |
2017-07-04 |
Western Digital Technologies, Inc. |
Hybrid solid state drive (SSD) using PCM or other high performance solid-state memory
|
|
WO2016144521A1
(en)
*
|
2015-03-10 |
2016-09-15 |
Rambus, Inc. |
Memories and memory components with interconnected and redundant data interfaces
|
|
US20160269501A1
(en)
*
|
2015-03-11 |
2016-09-15 |
Netapp, Inc. |
Using a cache cluster of a cloud computing service as a victim cache
|
|
US20160294983A1
(en)
*
|
2015-03-30 |
2016-10-06 |
Mellanox Technologies Ltd. |
Memory sharing using rdma
|
|
US20170046278A1
(en)
*
|
2015-08-14 |
2017-02-16 |
Qualcomm Incorporated |
Method and apparatus for updating replacement policy information for a fully associative buffer cache
|
|
JP6540363B2
(ja)
*
|
2015-08-19 |
2019-07-10 |
富士通株式会社 |
ストレージ制御装置、ストレージ制御方法、およびストレージ制御プログラム
|
|
US9824012B2
(en)
*
|
2015-09-24 |
2017-11-21 |
Qualcomm Incorporated |
Providing coherent merging of committed store queue entries in unordered store queues of block-based computer processors
|
|
US10002076B2
(en)
*
|
2015-09-29 |
2018-06-19 |
Nxp Usa, Inc. |
Shared cache protocol for parallel search and replacement
|
|
US10255196B2
(en)
*
|
2015-12-22 |
2019-04-09 |
Intel Corporation |
Method and apparatus for sub-page write protection
|
|
US20170255569A1
(en)
*
|
2016-03-01 |
2017-09-07 |
Qualcomm Incorporated |
Write-allocation for a cache based on execute permissions
|
|
US10019375B2
(en)
|
2016-03-02 |
2018-07-10 |
Toshiba Memory Corporation |
Cache device and semiconductor device including a tag memory storing absence, compression and write state information
|
|
US10169240B2
(en)
|
2016-04-08 |
2019-01-01 |
Qualcomm Incorporated |
Reducing memory access bandwidth based on prediction of memory request size
|
|
US10185668B2
(en)
*
|
2016-04-08 |
2019-01-22 |
Qualcomm Incorporated |
Cost-aware cache replacement
|
|
US9940267B2
(en)
*
|
2016-05-17 |
2018-04-10 |
Nxp Usa, Inc. |
Compiler global memory access optimization in code regions using most appropriate base pointer registers
|
|
US12287763B2
(en)
*
|
2016-05-27 |
2025-04-29 |
Netapp, Inc. |
Methods for facilitating external cache in a cloud storage environment and devices thereof
|
|
US10430349B2
(en)
*
|
2016-06-13 |
2019-10-01 |
Advanced Micro Devices, Inc. |
Scaled set dueling for cache replacement policies
|
|
US9928176B2
(en)
|
2016-07-20 |
2018-03-27 |
Advanced Micro Devices, Inc. |
Selecting cache transfer policy for prefetched data based on cache test regions
|
|
US9946646B2
(en)
*
|
2016-09-06 |
2018-04-17 |
Advanced Micro Devices, Inc. |
Systems and method for delayed cache utilization
|
|
US10719447B2
(en)
*
|
2016-09-26 |
2020-07-21 |
Intel Corporation |
Cache and compression interoperability in a graphics processor pipeline
|
|
DE112016007298T5
(de)
*
|
2016-09-30 |
2019-06-13 |
Mitsubishi Electric Corporation |
Informationsverarbeitungsgerät
|
|
US20180107602A1
(en)
*
|
2016-10-13 |
2018-04-19 |
Intel Corporation |
Latency and Bandwidth Efficiency Improvement for Read Modify Write When a Read Operation is Requested to a Partially Modified Write Only Cacheline
|
|
US10860495B2
(en)
|
2016-11-29 |
2020-12-08 |
Arm Limited |
Storage circuitry responsive to a tag-matching command
|
|
US10430706B2
(en)
*
|
2016-12-01 |
2019-10-01 |
Via Alliance Semiconductor Co., Ltd. |
Processor with memory array operable as either last level cache slice or neural network unit memory
|
|
US10282296B2
(en)
*
|
2016-12-12 |
2019-05-07 |
Intel Corporation |
Zeroing a cache line
|
|
US10162756B2
(en)
*
|
2017-01-18 |
2018-12-25 |
Intel Corporation |
Memory-efficient last level cache architecture
|
|
US10331582B2
(en)
|
2017-02-13 |
2019-06-25 |
Intel Corporation |
Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time
|
|
JP2018133038A
(ja)
*
|
2017-02-17 |
2018-08-23 |
Ｎｅｃプラットフォームズ株式会社 |
情報処理装置、制御装置、制御方法及びプログラム
|
|
US10102149B1
(en)
*
|
2017-04-17 |
2018-10-16 |
Intel Corporation |
Replacement policies for a hybrid hierarchical cache
|
|
US10482028B2
(en)
*
|
2017-04-21 |
2019-11-19 |
Intel Corporation |
Cache optimization for graphics systems
|
|
US20180336143A1
(en)
*
|
2017-05-22 |
2018-11-22 |
Microsoft Technology Licensing, Llc |
Concurrent cache memory access
|
|
WO2019005166A1
(en)
*
|
2017-06-30 |
2019-01-03 |
Intel Corporation |
METHOD AND APPARATUS FOR VECTORIZING HISTOGRAM BUCKLES
|
|
US10318436B2
(en)
*
|
2017-07-25 |
2019-06-11 |
Qualcomm Incorporated |
Precise invalidation of virtually tagged caches
|
|
US11294594B2
(en)
*
|
2017-08-07 |
2022-04-05 |
Kioxia Corporation |
SSD architecture supporting low latency operation
|
|
US20190073305A1
(en)
*
|
2017-09-05 |
2019-03-07 |
Qualcomm Incorporated |
Reuse Aware Cache Line Insertion And Victim Selection In Large Cache Memory
|
|
US10503656B2
(en)
*
|
2017-09-20 |
2019-12-10 |
Qualcomm Incorporated |
Performance by retaining high locality data in higher level cache memory
|
|
US10719058B1
(en)
*
|
2017-09-25 |
2020-07-21 |
Cadence Design Systems, Inc. |
System and method for memory control having selectively distributed power-on processing
|
|
US10691345B2
(en)
|
2017-09-29 |
2020-06-23 |
Intel Corporation |
Systems, methods and apparatus for memory access and scheduling
|
|
US10402096B2
(en)
*
|
2018-01-31 |
2019-09-03 |
EMC IP Holding Company LLC |
Unaligned IO cache for inline compression optimization
|
|
US10909040B2
(en)
*
|
2018-04-19 |
2021-02-02 |
Intel Corporation |
Adaptive calibration of nonvolatile memory channel based on platform power management state
|
|
US10983922B2
(en)
*
|
2018-05-18 |
2021-04-20 |
International Business Machines Corporation |
Selecting one of multiple cache eviction algorithms to use to evict a track from the cache using a machine learning module
|
|
US10884751B2
(en)
*
|
2018-07-13 |
2021-01-05 |
Advanced Micro Devices, Inc. |
Method and apparatus for virtualizing the micro-op cache
|
|
US11030098B2
(en)
*
|
2018-09-25 |
2021-06-08 |
Micron Technology, Inc. |
Configurable burst optimization for a parameterizable buffer
|
|
US10628312B2
(en)
*
|
2018-09-26 |
2020-04-21 |
Nxp Usa, Inc. |
Producer/consumer paced data transfer within a data processing system having a cache which implements different cache coherency protocols
|
|
US10802974B2
(en)
*
|
2018-10-15 |
2020-10-13 |
Texas Instruments Incorporated |
Virtual network pre-arbitration for deadlock avoidance and enhanced performance
|
|
US10768899B2
(en)
*
|
2019-01-29 |
2020-09-08 |
SambaNova Systems, Inc. |
Matrix normal/transpose read and a reconfigurable data processor including same
|
|
US11061810B2
(en)
*
|
2019-02-21 |
2021-07-13 |
International Business Machines Corporation |
Virtual cache mechanism for program break point register exception handling
|
|
US11487616B2
(en)
*
|
2019-05-24 |
2022-11-01 |
Texas Instruments Incorporated |
Write control for read-modify-write operations in cache memory
|
|
US11360905B2
(en)
*
|
2019-05-24 |
2022-06-14 |
Texas Instmments Incorporated |
Write merging on stores with different privilege levels
|
|
US11163700B1
(en)
*
|
2020-04-30 |
2021-11-02 |
International Business Machines Corporation |
Initiating interconnect operation without waiting on lower level cache directory lookup
|
|
CN116257472B
(zh)
*
|
2023-05-15 |
2023-08-22 |
上海励驰半导体有限公司 |
接口控制方法、装置、电子设备及存储介质
|