JPWO2009107562A1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to solve the problem of reducing the effect of a contact etch stop film system with the progress of miniaturization. A semiconductor device according to the present invention has a bent shape and a beam as a bent shape portion that generates a stress from the shape, and the carrier moves by being distorted by receiving the stress from the beam. This is a MISFET having a channel region 12 as a semiconductor portion whose degree is changed. According to the semiconductor device 10, the beam 11 having a bent shape is used and the channel region 12 is distorted by using the stress of the beam 11, so that the distortion is generated by a method different from the contact etch stop film method. Therefore, it is possible to solve the problem of effect reduction with the progress of miniaturization of the contact etch stop film system. [Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device whose mobility is improved by strain and a manufacturing method thereof. Hereinafter, “MIS (Metal-Insulator-Semiconductor) type field effect transistor” is abbreviated as “MISFET (MIS Field Effect Transistor)”. Of course, MOS-type (Metal-Oxide-Semiconductor) field effect transistors are also included in the MISFET. In addition, element symbols are used as element names.

  In recent years, it has become difficult to improve the performance of MISFETs due to various physical constraints even if miniaturization of an integrated circuit is advanced in accordance with a proportional reduction law (scaling law). Under such circumstances, attention has been paid to a technique for improving mobility by distortion. In this technique, stress is applied to the channel region of the MISFET, thereby distorting the crystal lattice of the channel region and improving the carrier mobility.

  For example, when the channel direction of the MISFET is the <110> direction of the (100) surface of Si, applying a tensile stress in this direction to distort the Si crystal lattice in the channel region improves the electron mobility. At the same time, the mobility of holes decreases. Further, when compressive stress is applied in the same direction to distort the Si crystal lattice in the channel region, electron mobility is lowered and hole mobility is improved. Hereinafter, a technique using such characteristics is referred to as a “strained Si technique”.

  There are roughly two methods of strained Si technology. One is called an embedded silicon germanium (eSiGe) method, and the other is called a contact etch stop layer (CESL) method. The former is a method of embedding SiGe having a lattice constant larger than that of Si using selective epitaxial growth in the source and drain of the MISFET, and is mainly used for a p-channel type MISFET. On the other hand, the latter is a method using a Si nitride film that causes distortion in the channel region as the contact etch stop film, and is a method disclosed in, for example, Patent Document 1, Patent Document 2, and Non-Patent Document 1. In these documents, a plurality of gate stacks formed on a Si substrate (hereinafter referred to as a gate stack in the present specification is composed of a gate insulating film and a gate electrode) are formed from above all of them. A technique is disclosed in which a Si nitride film used as a contact etch stop film is covered and stress is applied to the channel region by the Si nitride film. In recent years, a technique has been reported in which a semiconductor is bent and a current flows in the semiconductor (Patent Document 3).

  Patent Document 1 discloses an example in which the performance of an n-channel MISFET is improved by using a thermal nitride film having a high tensile stress as a contact etch stop film. In Patent Document 2 and Non-Patent Document 1, an Si nitride film that applies tensile stress to the channel region is used for the n-channel MISFET, and an Si nitride film that applies compressive stress to the channel region is used for the p-channel MISFET. Accordingly, a technique for improving the performance of both the n-channel MISFET and the p-channel MISFET is disclosed. As described above, in the contact etch stop film system, a technique for separately using Si nitride films that apply stresses in different directions to improve the mobility of carriers in n-channel MISFETs and p-channel MISFETs, respectively. (Dual Stress Liner) technology.

JP 2002-198368 A JP 2003-086708 A International Publication No. 2005/122276 December 2005, International Electron Device Meeting 2005, Technical Digest, pages 229-232 (International Electron Devices Meeting 2005, Technical Digest, pp.229-232) February 18, 2002, supervised by Industrial Technology Service Center, Masayoshi Esashi, Micromachine-A small and highly functional system that integrates different elements, pages 221-230, Jiro Sakata "Countermeasures against sticking"

  However, the semiconductor devices disclosed in Patent Document 1, Patent Document 2, and Non-Patent Document 1 have the following problems.

  Generally, as shown in FIG. 5 of Non-Patent Document 1 (here, as in the DSL technique, a film that applies tensile stress to an n-channel MISFET and a film that applies compressive stress to a p-channel MISFET are used. In the contact etch stop film method, the on-current increases as the Si nitride film becomes thicker. That is, when the Si nitride film is thickened, the stress is increased, so that the distortion of the channel region is also increased, and the mobility of the carriers is improved reflecting this, so that the on-current is also increased.

  However, as shown in FIGS. 7 to 9 of Non-Patent Document 1, the following problem occurs when a plurality of gate stacked bodies are arranged adjacent to each other at the minimum pitch. When the Si nitride film of the contact etch stop film is made thicker, the space between adjacent gate stacks is filled after the film thickness exceeds a certain thickness. When the space between the gate stacks begins to fill with the Si nitride film, the region with the strongest stress (especially the stress in the gate length direction) gradually moves away from the channel region. For this reason, even when the Si nitride film is thickened, the strain in the channel region abruptly decreases from around the thickness at which the space between the gate stacks begins to fill, and the on-current is also reduced. That is, there is an upper limit to the thickness of the Si nitride film that can increase the on-current.

  On the other hand, miniaturization of MISFET is progressing year by year. As a matter of course, the pitch between adjacent gate stacks is reduced as the size is reduced. This means that as the miniaturization progresses, a thinner Si nitride film fills the space between adjacent gate stacks. That is, the upper limit of the thickness of the Si nitride film that can increase the on-current is further reduced as the size is reduced. For this reason, as the amount of strain caused by the Si nitride film decreases as the miniaturization progresses, the degree of improvement in mobility also decreases, so the rate of increase in on-current by the Si nitride film also decreases. To go.

  As described above, the contact etch stop film system has a problem that the effect is reduced when the MISFET is miniaturized. In general, since the effect of strain is additive, in the p-channel type MISFET, the effect of the contact etch stop film method is reduced, and if it is newly combined with the embedded SiGe method, the same compressive stress is applied even if it is miniaturized. Is possible. However, since the embedded SiGe method cannot be applied to the n-channel type MISFET, the effect of the contact etch stop film method becomes small when miniaturized. Therefore, a new method for generating tensile strain in the channel region of the n-channel MISFET has been demanded.

  Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, in which distortion is applied to the channel region of the MISFET with a novel structure so as to compensate for the effect reduction of the contact etch stop film system accompanying the progress of miniaturization. It is in.

  The semiconductor device according to the present invention includes a bent shape portion that has a bent shape and generates stress from the shape, and a semiconductor portion in which the mobility of the carrier is changed due to distortion due to the stress.

  The method for manufacturing a semiconductor device according to the present invention includes a first step of forming on the semiconductor substrate a structure in which one end is fixed to the semiconductor substrate and the other end is not fixed anywhere, and a liquid is applied to a space around the structure. A second step of filling and drying the liquid filled in the space to bend the structure and fix the other end in contact with the semiconductor substrate or another structure on the semiconductor substrate And a third step.

  According to the present invention, by using a bent shape portion having a bent shape, the semiconductor portion is distorted by using the stress generated from the bent shape portion, thereby using a method different from the contact etch stop film method. Since distortion can be generated, it is possible to solve the problem of effect reduction with the progress of miniaturization of the contact etch stop film system.

<First embodiment>
FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is an enlarged view of a main part of FIG. However, in FIG. 2, hatching is omitted for the sake of clarity. The outline of the semiconductor device of this embodiment will be described below with reference to these drawings.

  The semiconductor device 10 according to the present embodiment includes a beam 11 as a bent shape portion that has a bent shape and generates stress from the shape, and a semiconductor in which carrier mobility is changed by distortion due to the stress of the beam 11. MISFET having a channel region 12 as a part.

  However, the semiconductor device is not limited to the MISFET, and may be any device that has a semiconductor portion through which a current flows, such as a junction FET, a bipolar transistor, a diode, a light emitting element, a light receiving element, and a sensor. The semiconductor portion is not limited to the channel region 12 and may be any semiconductor as long as carriers flow. The bent shape portion is not limited to the beam 11 and may be, for example, a plate or other complicated shape as long as it has a bent shape and generates stress. Moreover, in order to avoid an electrical influence, it is preferable that a bending shape part is an insulator.

  According to the semiconductor device 10, by using the beam 11 having a bent shape and distorting the channel region 12 using the stress of the beam 11, distortion is caused by a method different from the contact etch stop film method. Therefore, it is possible to solve the problem of reducing the effect accompanying the progress of miniaturization of the contact etch stop film system.

  The beam 11 is a beam in which one end 11a and the other end 11b are fixed in a bent state. The beam 11 has an advantage that it is easy to manufacture because the structure is relatively simple. A channel region 12 is formed on the surface of the semiconductor substrate 13, one end 11a of the beam 11 is fixed to the surface of the semiconductor substrate 13, and the stress of the beam 11 acts on the channel region 12 through the one end 11a. The semiconductor substrate 13 is a Si substrate. However, the semiconductor substrate is not limited to the Si substrate, and may be, for example, a Ge substrate, a SiC substrate, a GaAs substrate, an SOI (Silicon On Insulator) substrate, an SGOI (Silicon Germanium On Insulator) substrate, or the like.

  In addition, the semiconductor device 10 includes a gate stacked body 16 including a gate insulating film 14 and a gate electrode 15 formed on the channel region 12, and a gate sidewall 17 formed on a side surface of the gate stacked body 16. The beam 11 is a part of the gate side wall 17, and the other end 11 b of the beam 11 is fixed to the side surface of the gate stacked body 16. The gate sidewall 17 includes a void 18 surrounded by the beam 11 and the gate stack 16. Since the gap 18 has the lowest dielectric constant, the parasitic capacitance of the gate electrode 15 can be reduced. The strain applied to the channel region 12 is mainly controlled by the length L1 of the beam 11 in the gate length direction (thickness of the beam 11) L1 and the distance L2 from one end 11a of the beam 11 to the side surface of the gate stacked body 16. ing. The material, surface, and channel direction of the channel region 12 vary depending on the substrate used. In the most general case, the semiconductor substrate 13 is a bulk Si substrate, the channel region 12 is made of Si, and the surface of the channel region 12 and This is the case where the channel direction is the <110> direction or the <100> direction of the (100) plane of Si. The beam 11 is preferably made of a material having a large Young's modulus, and is made of, for example, a Si nitride film.

  Although not shown, the semiconductor device 10 may include a plurality of MISFETs. At this time, the strain applied to the channel region 12 in each MISFET may be set to two or more types by varying at least one of the length (thickness of the beam 11) L1 and the distance L2. The plurality of MISFETs may include an n-channel MISFET and a p-channel MISFET. At this time, depending on the channel direction, only the n-channel MISFET may be the MISFET shown in FIG. 1, or both the n-channel MISFET and the p-channel MISFET may be the MISFET shown in FIG.

  In the semiconductor device 10 of this embodiment, a bent beam 11 formed of an insulator is used as a part of the gate side wall 17, and a region to which stress is applied by the bent beam 11 is transferred to a carrier (electron and / or The channel region 12 in which holes) move is used. In the channel region 12, tensile strain is introduced by applying stress from the deflected beam 11. Therefore, the mobility of electrons moving through the channel region 12 is improved, and the n-channel MISFET in which electrons are the main carriers is a semiconductor device 10 having a high on-current and capable of high-speed operation. As described above, the structure of the present invention can be applied to various semiconductor devices as long as electrons and / or holes move in a region where stress is applied by a deflected beam and the mobility is related to performance. Can be applied.

  The original beam 11 is a cantilever beam. One end 11 a of the beam 11 serves as a fulcrum fixed to the semiconductor substrate 13. Here, the other end 11 b of the beam 11 is bent in the direction of the gate stacked body 16 from the state of the cantilever. Then, the reaction force acting on the fulcrum of the beam 11 works in the direction away from the gate stacked body 16. Therefore, a tensile stress can be applied to the channel region 12 under the gate stacked body 16, so that a tensile strain can be introduced into the channel region 12. A cantilever is a beam that has one end fixed and the other end free. When a concentrated load is applied to the tip of the cantilever, the opposite direction is the same as the concentrated load. It is known that force acts on the fulcrum of the beam.

  FIG. 3 is a cross-sectional view for explaining the relationship between the bending of the beam and the stress acting on the semiconductor portion in the present embodiment. Hereinafter, description will be given based on this drawing.

  The beam structure in this embodiment will be described with reference to FIG. In the following explanation, the influence of gravity is ignored because it is sufficiently small. Further, the cantilever beams 30 and 30a in FIG. 3 correspond to the beam 11 in FIG.

  FIG. 3 (a) shows a cantilever beam which is common in material mechanics and before bending occurs. The beam 30a has a length l, a thickness h, and a width (a length in the drawing depth direction) b. The cross-sectional shape of the beam 30a is a rectangle. One end of the beam 30 a is fixed to the fixing member 31. One end thereof is a fixed end 32.

As shown in FIG. 3B, it is assumed that a concentrated load 33 having a size P is acting on the tip of the bent cantilever 30. The tip deflection v occurring at that time is given by the following equation.
v = Pl ³ / 3EI (1)
I = bh ³ / l ² (2)
Here, E is the Young's modulus of the material constituting the cantilever 30 and I is the moment of inertia of the cross section. A reaction force 34 having the same magnitude as the concentrated load 33 and the opposite direction acts on the fixed end 32 serving as a fulcrum of the bent cantilever 30.

  In the present embodiment, the structure shown in FIGS. 3A and 3B is rotated by 90 degrees and used as shown in FIGS. 3C and 3D. The structure before the rotation and the structure after the rotation do not change physically. In FIG. 3D, if a concentrated load 33 having a size P is acting on the tip of the bent cantilever 30, the tip deflection v generated at that time is given by equation (1). Further, a reaction force 34 having the same magnitude as the concentrated load 33 and the opposite direction acts on the fixed end 32 serving as a fulcrum of the bent cantilever 30. Here, in FIG. 3D, if the fixing member 31 is regarded as a semiconductor substrate, it can be seen that the reaction force 34 can be used as a stress acting on the channel region.

  FIG. 4 is a cross-sectional view for explaining how the beam is bent in the present embodiment. Hereinafter, description will be given based on this drawing.

  In the present embodiment, how to apply a force corresponding to the concentrated load 33 in FIG. 3 will be described with reference to FIG. FIG. 4A shows a situation where two cantilever beams 30a are present at a certain interval on a semiconductor substrate which is the fixing member 31. FIG. After filling the two cantilever beams 30a with the liquid, the liquid is dried. Then, as shown in FIG. 4A, a situation occurs in which the liquid 35 remains between the two cantilever beams 30a. In such a situation, due to the surface tension of the liquid 35, a force that pulls each other between the two cantilevers 30a works, so that the two cantilevers 30a bow together. Try to flex. In general, if the distance between the two cantilevers 30a is sufficiently wide, the influence of the surface tension of the liquid is small and the liquid 35 on the semiconductor substrate of the fixing member 31 is not dried. The cantilever 30a is in an upright state.

  However, when the distance between the two cantilevers 30a is narrower than a certain value, the force attracted by the two cantilevers 30a due to the surface tension of the liquid 35 exceeds the restoring force of each cantilever 30a. As a result, as shown in FIG. 4B, the two cantilever beams 30 adhere to each other while being bent, and this state is maintained by the adhesive force even after the liquid 35 is completely dried. The The identity of the adhesive force is said to be the adhesive force of the residue of the liquid 35, the hydrogen bond force between the two cantilever beams 30, the van der Waals force between the two cantilever beams 30 (Non-patent Document 2). ). Such a phenomenon is often observed when a line and space pattern having a high aspect ratio is formed with a resist. Of course, the material in which such an adhesion phenomenon is observed is not limited to the resist, and the same phenomenon is observed in, for example, Si.

  When the two cantilever beams 30a are immersed in the liquid and then the liquid is completely dried, the adhesive force acting on the tip of the cantilever beam 30 is as shown in FIG. It can be regarded as the concentrated load 33 shown in d). At this time, a reaction force 34 that is equal in magnitude to the adhesion force and opposite in direction acts on the fixed end 32 of the cantilever 30.

  5 and 6 are cross-sectional views for explaining the force received by the semiconductor portion from the deflected beam in the present embodiment. Further, the cantilever beams 30, 30a, 30s, and 30d in FIGS. 5 and 6 correspond to the beam 11 in FIG. Hereinafter, description will be given based on this drawing.

  Each of FIGS. 5 and 6 shows a cross-sectional view of the n-channel MISFET in the gate length direction. First, as shown in FIG. 5A, a semiconductor substrate 13 on which an element isolation insulating film 19 is formed is prepared, and a gate stacked body 16 including a gate insulating film 14 and a gate electrode 15 is formed on the semiconductor substrate 13. At the same time, two cantilevers 30 a are formed in the vicinity of the gate stack 16.

  Subsequently, as shown in FIG. 5B, the cantilever 30 a is bent and attached to the gate stacked body 16 using the method shown in FIG. 4. The cantilever 30 in this state is bent due to the adhesive force from the gate stack 16 at the tip. Hereinafter, the cantilever 30 on the source side is referred to as a cantilever 30s, and the cantilever 30 on the drain side is referred to as a cantilever 30d.

  At this time, as shown in FIG. 5C, a gate stack is formed as a reaction force of the force P1, which is an adhesive force, on the fulcrum of the source-side cantilever 30s, that is, the contact between the cantilever 30s and the semiconductor substrate 13. A force P2 in a direction away from the body 16 works. Similarly, as shown in FIG. 6 (d), the gate stack is formed as a reaction force of the force P1, which is an adhesive force, at the fulcrum of the drain side cantilever 30d, that is, the contact between the cantilever 30d and the semiconductor substrate 13. A force P2 in a direction away from the body 16 works.

  On the other hand, since the cantilever beams 30s and 30d are attached to the gate stacked body 16 as shown in FIG. 6E, the gate stacked body 16 is pulled by the force P1 from both the cantilever beams 30s and 30d. Since these forces P1 are opposite in direction and equal in magnitude, they cancel each other, and as a result, the gate stack 16 is not affected.

  Therefore, as shown in FIG. 6F, the force P2 acts on the channel region 12 from the fulcrums of the cantilever beams 30s and 30d. Therefore, the channel region 12 receives a stress in a direction away from the gate stacked body 16, that is, a tensile stress. Therefore, the on-current of the n-channel type MISFET increases by improving the electron mobility. Note that this method is suitable for miniaturization because a position where stress is applied to the channel region 12 is closer to the channel region 12 than a similar position in the DSL technique.

In addition, about the magnitude | size of the force which acts like FIG.6 (f), it estimates as follows. As described with reference to FIGS. 3 and 4, the magnitude of the reaction force 34 is equal to the concentrated load 33 acting on the tip of the cantilever 30. In FIG. 6 (f), what corresponds to the concentrated load 33 is the adhesive force acting between the gate stack 16 and the cantilever beams 30s, 30d. It is assumed that the adhesive force is bent by an interval between the gate stack 16 and the cantilever 30a before being bent. That is, it is approximated that the bending v in the equation (1) is equal to the interval between the gate stacked body 16 and the cantilever 30a before bending. Then, the concentrated load P is calculated | required as follows from (1) Formula and (2) Formula.
P = 3vEI / l ³ (3)

Assuming that this force acts on the region of the junction depth x _j in the n-channel MISFET, the stress σ caused by the bent cantilever 30 is as follows from the equations (2) and (3): It is required as follows.
σ = P / (bx _j ) = [vE / (4x _j )] (l / h) ⁻³ (4)

  From equation (4), in order to increase the stress, a material having a high Young's modulus E is used for the beam, the beam is greatly deflected (the deflection v is increased), and the beam aspect ratio (= l / h). It can be seen that it is important to reduce. Since the Si nitride film has a larger Young's modulus than the Si oxide film, it is preferable as a material for the cantilever 30. However, these conditions are also conditions that make it difficult for the cantilever beam 30 to adhere to the gate stack 16. For this reason, parameters that satisfy the above-described conditions should be adopted as parameters that are allowed in a range in which the cantilever 30 adheres to the gate stacked body 16.

From the equation (4), when the magnitude of the stress is specifically estimated, for example, if l = 50 nm, h = 10 nm, v = 10 nm, x _j = 10 nm, E = 250 GPa (assuming Si nitride film) Σ = 0.5 GPa.
Therefore, according to the present embodiment, it is possible to apply a stress that compensates for the decrease to the contact etch stop film system in which the effect becomes smaller as the miniaturization progresses. Further, if the configuration of the present embodiment is applied to an existing element to which a contact etch stop film system such as DSL technology is applied, the on-current increases by the amount of stress due to the configuration of the present embodiment.

  Next, an outline of the semiconductor device manufacturing method of the present embodiment will be described.

  As a method of bending the beam, as shown in FIG. 5A, a straight beam 30a is formed on the source side and the drain side in the vicinity of the gate laminate 16, and then the beam 30a and the gate laminate 16 are interposed. It is preferable to fill the space with a liquid and dry the liquid. At this time, due to the surface tension of the liquid, the beam 30a is pulled and bent toward the gate stacked body 16 side. Furthermore, when this force exceeds the restoring force of the beam 30a, as shown in FIG. 5 (b), the beam 30 remains attached to the gate stacked body 16 without being bent. Examples of the liquid used here include an organic solvent, water, mercury, and the like, but water or mercury is preferable because it has a large surface tension and easily causes bending.

  The drying in the present embodiment is preferably a method in which the drying proceeds while maintaining the surface tension as a liquid, and examples include a drying method that passes a gas-liquid equilibrium curve in the substance phase diagram. Any drying method may be used, and examples include spin drying, spraying of dry nitrogen, heating of the wafer, and drying under reduced pressure. However, drying methods that do not pass the vapor-liquid equilibrium curve in the substance phase diagram, such as supercritical drying via the supercritical state and freeze drying, are not preferable. This is because in the method of drying a liquid that does not pass the vapor-liquid equilibrium curve in the state diagram of the substance, the surface tension of the liquid does not work, and thus the beam of the cantilever structure does not bend.

  Next, returning to FIGS. 1 and 2, the semiconductor device of this embodiment will be described in more detail.

  FIG. 1 is a cross-sectional view along the gate length direction. Further, the semiconductor device 10 of FIG. 1 is an n-channel MISFET, and shows a state where the contact 24 is formed.

  The semiconductor device 10 of the present embodiment includes a beam 11 in which a cantilever beam with a semiconductor substrate 13 as a fulcrum is bent and a free end is fixed. The beam 11 has a structure in which the other end 11b is bent in the direction of the gate stacked body 16 and is attached to the gate stacked body 16, and is a part of the gate side wall 17. Also, the beam 11 is bent to form the gate stacked body. In order to create a state of adhering to the body 16, an air gap 18 exists between the gate stack 16 and the beam 11. The air gap 18 is also a part of the gate side wall 17.

  As will be described later, after the beam 11 is processed into a cantilever shape upright on the semiconductor substrate 13, the tip of the beam 11 is fixed to the gate stacked body 16, thereby forming a bent shape. The beam 11 is fixed in a state where it is pulled and bent in the direction of the gate stacked body 16 by the adhesive force from the gate stacked body 16. On the fulcrum 11a of the beam 11, a reaction force having the same magnitude as the adhesion force from the gate stacked body 16 and acting in the opposite direction acts. One beam 11 that is bent and attached to the gate stacked body 16 exists on the source side and the drain side in the vicinity of the gate stacked body 16 and has the same shape. A reaction force in a direction away from the gate stacked body 16 acts on the fulcrum 11a of each beam 11. Therefore, these forces cause a tensile stress on Si in the channel region 12. As a result, the distance between the crystal lattices of Si is increased, so that the electron mobility is improved, and the on-current of the n-channel MISFET is increased.

  Since the semiconductor device 10 of this embodiment is an n-channel MISFET, its basic configuration is the same as a general-purpose n-channel MISFET. That is, the element isolation insulating film 19 and the p well 20 are provided on the semiconductor substrate 13, and the channel region 12 is doped p-type. On the semiconductor substrate 13, a gate stacked body 16 including a gate insulating film 14 and a gate electrode 15 is formed. An n-type S / D (Source / Drain) extension electrode 21 and an n-type deep S / D electrode 22 are formed on the semiconductor substrate 13 from the vicinity of the gate stacked body 16. Silicide layers 15b and 22b are formed on the gate electrode 15 and the deep S / D electrode 22, respectively. Further, a metal contact 24 is formed on the interlayer insulating film 23, and a stopper nitride film 25 is provided as a contact etch stop film at the time of forming the contact hole.

  7 to 10 are cross-sectional views showing the method for manufacturing the semiconductor device of this embodiment. Hereinafter, description will be given based on these drawings.

  Each of FIGS. 7 to 10 shows the state of each stage of the manufacturing process of the n-channel type MISFET of this embodiment. With reference to FIGS. 7 to 10, a method of manufacturing the semiconductor device of this embodiment will be described. Each cross-sectional view shows a cross section in the gate length direction of the MISFET.

  First, as shown in FIG. 7A, an element isolation insulating film 19 is formed on the semiconductor substrate 13. At this time, an STI (Shallow Trench Isolation) method, which is a general method for forming element isolation of the MISFET, is used. Further, a LOCOS (Local Oxidation of Silicon) method may be used instead of the STI method. In this embodiment, an Si substrate is used as the semiconductor substrate 13, but an SOI (Silicon on Insulator) substrate, an SGOI (Silicon Germanium on Insulator) substrate, a Ge substrate, an SiC substrate, or the like may be used. Further, in the present embodiment, the <110> direction of the (100) plane of Si is used as the channel direction. However, if it receives tensile strain, the mobility of electrons improves, and the on-current of the n-channel MISFET increases. Any direction may be used.

Subsequently, as shown in FIG. 7B, p-well implantation is performed to form the p-well 20, and ion implantation for adjusting the threshold value of the n-channel MISFET is further performed. For example, as p-well implantation, monovalent B ions are implanted at an acceleration energy of 150 keV and a dose of 8 × 10 ¹² cm ⁻² . Further, as ion implantation for threshold adjustment, monovalent B ions are implanted at an acceleration energy of 15 keV and a dose of 8 × 10 ¹² cm ⁻² .

Subsequently, as shown in FIG. 7C, a gate insulating film 14 and a poly-Si layer 15 a are formed on the semiconductor substrate 13. As the gate insulating film 14, for example, a 1.2 nm-thickness Si oxynitride film is formed. In addition to this, as the gate insulating film 14, a Si oxide film, a so-called High-k film such as Ta ₂ O ₅ , Al ₂ O ₃ , HfO ₂ , ZrO ₂ , ZrON, HfON, HfAlON, HfSiON, HfAlSiON, or the like can be used. May be used. Moreover, these laminated films may be sufficient.

After the formation of the gate insulating film 14, a poly Si layer 15a is deposited as a gate electrode material. For example, 50 nm of poly-Si is deposited using a CVD (Chemical Vapor Deposition) method. Instead of poly-Si, a semiconductor such as amorphous Si or poly-SiGe may be used, a metal such as TaN, TiN, W, or WN may be used, or full silicide such as NiSi may be used. Moreover, it is good also as these laminated structure. Pre-doping may be performed after the formation of the poly-Si layer 15a. In that case, for example, monovalent P ions are implanted with an acceleration energy of 4 keV and a dose of 4 × 10 ¹⁵ cm ⁻² .

  Subsequently, as shown in FIG. 7D, lithography is performed, and the poly-Si layer 15a is etched using the resist as a mask. After etching, the resist is peeled off. As a result, an n-channel MISFET gate stack 16a is formed. If the poly-Si layer 15a is pre-doped in the step of FIG. 7C, the impurity is activated by annealing after the formation of the gate stacked body 16a. For example, the impurities are activated by spike annealing at 1030 ° C. Spike annealing refers to annealing in which when the target temperature is reached, the temperature is immediately reduced with a maintenance time of 0 seconds.

Subsequently, as shown in FIG. 8E, extension injection is performed to form the S / D extension electrode 21. For example, monovalent As ions are implanted with an acceleration energy of 1 keV and a dose of 5 × 10 ¹⁴ cm ^{−2 using} the n-channel MISFET gate stack 16a as a mask. Although not shown in FIG. 8E and the subsequent drawings, ion implantation for forming a pocket region is performed before or after ion implantation for forming the S / D extension electrode 21 of the n-channel type MISFET. May do. For example, monovalent BF ₂ ions are implanted at a dose of 2 × 10 ¹³ cm ⁻² .

  Subsequently, as shown in FIG. 8F, a gate sidewall 17a is formed. First, the first insulating film 41 is formed, and then etched back, so that the first insulating film 41 has an offset spacer shape. Subsequently, the second insulating film 42 is formed, and then etched back to make the second insulating film 42 into an offset spacer shape. Finally, a sidewall insulating film 43 is formed and etched back so as to be overetched to form the gate sidewall 17a. At this time, the first insulating film 41 and the sidewall insulating film 43 are the same kind of insulating films. Alternatively, the first insulating film 41 and the sidewall insulating film 43 may be of different types, but can be removed by the same etching method, and in order to leave the second insulating film 42, Therefore, the film type can be selectively etched by the same etching method. For example, a 10 nm Si oxide film is formed as the first insulating film 41 and the sidewall insulating film 43, and a 10 nm Si nitride film is formed as the second insulating film.

  In FIG. 8E, extension implantation is performed using only the gate stacked body 16a as a mask. However, after forming the offset spacer shape made of the first insulating film 41 in FIG. 8F or after forming the offset spacer shape made of the second insulating film 42 in FIG. It is also possible to perform ion implantation to be formed.

Subsequently, as shown in FIG. 8G, after forming the gate side wall 17a, the deep S / D electrode 22 is formed by performing S / D implantation. For example, monovalent As ions are implanted at an acceleration energy of 5 keV and a dose of 5 × 10 ¹⁴ cm ^{−2 using} the gate stack 16a and gate sidewall 17a of the n-channel type MISFET as a mask, and further monovalent P ions are implanted. Implantation is performed with an acceleration energy of 3 keV and a dose of 4 × 10 ¹⁵ cm ⁻² .

  Subsequently, as shown in FIG. 9H, impurities are activated. For example, spike annealing at 1030 ° C. is performed. Alternatively, laser annealing with a carbon dioxide laser with a wavelength of 10.6 μm, a semiconductor laser with a wavelength of 810 nm, or a YAG laser with a wavelength of 1064 nm, or flash lamp annealing may be performed. A combination of spike annealing and laser annealing or flash lamp annealing is also possible.

  Subsequently, as shown in FIG. 9I, the first insulating film 41 and the sidewall insulating film 43 are removed. For this, selective etching is used in which the etching rate of the first insulating film 41 and the sidewall insulating film 43 is significantly higher than the etching rate of the second insulating film 42.

  Subsequently, as shown in FIG. 9J, the entire semiconductor substrate 13 is immersed in the liquid 35. For example, water is used as the liquid 35.

  Subsequently, as shown in FIG. 10 (k), the liquid 35 is dried. At this time, the second insulating film 42 is pulled toward the gate stacked body 16 a by the surface tension of the liquid 35. When this force exceeds the restoring force of the cantilevered second insulating film 42, the second insulating film 42 adheres to the gate stacked body 16a while being bent. Even if the liquid 35 is completely removed, the bent second insulating film 42 does not return to the original state due to the adhesive force between the second insulating film 42 and the gate stacked body 16a. As a result, the second insulating film 42 becomes the beam 11.

  Such a phenomenon is called a sticking phenomenon (or adhesion phenomenon), and is widely known in the field of micromachines as seen in Non-Patent Document 2. However, in the field of micromachines, once a portion that should originally move is attached and fixed, it does not make sense as a machine. Therefore, the sticking phenomenon is a problem phenomenon, and processing for avoiding this is performed. In the manufacturing method of the present embodiment, the second insulating film 42 is intentionally bent by actively using this sticking phenomenon. The greatest feature of this embodiment is that a tensile stress is applied to Si in the channel region 12 by utilizing a reaction force acting on a fulcrum of the bent cantilever.

  As described above, any drying method can be used as long as it passes through the vapor-liquid equilibrium curve in the phase diagram of the substance, such as spin drying, spraying of dry nitrogen, wafer heating, and drying under reduced pressure. Good. Although the example of water was given as the liquid 35, in order to bend more easily, it is also possible to use the liquid whose surface tension is larger than water. However, such liquid is only mercury. However, due to environmental pollution and handling safety, great care should be taken when using mercury.

  Subsequently, as shown in FIG. 10L, silicide layers 15b and 22b are formed on the gate stacked body 16a and the deep S / D electrode 22, respectively. For example, Ni silicide with a film thickness of 30 nm is formed. Thereby, the gate stacked body 16 a becomes the gate stacked body 16. The silicide is not limited to Ni silicide, but may be Ti silicide, Co silicide, Pd silicide, Pt silicide, NiPt silicide, or Er silicide.

  Finally, as shown in FIG. 10 (m), a stopper insulating film 25 and an interlayer insulating film 23 are sequentially deposited, and CMP (Chemical Mechanical Polishing), lithography and etching are performed to form contact holes. Then, a contact 24 is formed by embedding a metal in the contact hole. As the metal used for the contact 24, W, Al, TiN, Ti, Cu, or a laminated film of these metals is used.

  As described above, the semiconductor device 10 of FIG. 1 can be obtained by using the above manufacturing method.

  In other words, the manufacturing method of the semiconductor device of this embodiment includes the following steps. First step: A cantilever-shaped second insulating film 42 as a structure in which one end 11a (see FIG. 2) is fixed to the semiconductor substrate 13 and the other end 11b (see FIG. 2) is not fixed anywhere. It is formed on top (FIG. 8 (f) to FIG. 9 (i)). Second step: The liquid 35 is filled in the space around the second insulating film 42 (FIG. 9J). Third step: By drying the liquid 35 filled in the space, the second insulating film 42 is bent and the other end 11b is fixed in contact with the gate stacked body 16 as another structure ( FIG. 9 (k)).

  Moreover, the first step includes the following steps. A step of forming a first insulating film 41 as a first side wall on the side surface of the gate stacked body 16 (FIG. 8F). A step of forming a second insulating film 42 as a second side wall on the side surface of the first insulating film 41 (FIG. 8F). A step of forming the second insulating film 42 as a cantilever by removing the first insulating film 41 (FIG. 9I).

<Second embodiment>
In order to give different tensile strains to different MISFETs in one chip, there are mainly two methods. One is << 1 >> a method of changing the magnitude of bending the beam by changing the thickness of the first insulating film 41 in FIG. 8F, that is, a method of changing v in the equation (4). In the equation (4), v corresponds to L2 in FIG. The other is << 2 >> a method of changing the easiness of bending (difficulty of bending) of the beam by changing the thickness of the second insulating film 42 in FIG. 8F, that is, a method of changing h in the equation (4). is there. In the equation (4), h corresponds to L1 in FIG. In principle, << 3 >> a method of changing the beam material (method of changing E in (4)) and << 4 >> a method of changing the length of the beam (method of changing l in (4)) are also considered. It is done. However, because of the ease of the manufacturing method, the method <1> is used in the second embodiment, and the method <2> is used in the third embodiment.

  11 and 12 are cross-sectional views showing a semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention. Hereinafter, description will be given based on these drawings. However, in these drawings, the same parts as those in FIG.

  The present embodiment is a semiconductor device using the method << 1 >> and a method for manufacturing the same. In this case, it is only necessary to change (f) in FIG. 8 of the manufacturing method of the first embodiment to FIGS. 11 (f1) to 12 (f4). FIG. 11 (f1) to FIG. 12 (f4) are cross-sectional views showing the states of the respective manufacturing steps in the present embodiment. Each cross-sectional view shows a cross section in the gate length direction of the MISFET. In each cross-sectional view, two MISFETs are shown. Finally, the left MISFET and the right MISFET have different film thicknesses corresponding to the first insulating film in FIG. 8F, and the left MISFET film is thinner.

  First, as shown in FIG. 11 (f1), a first insulating film 41a is formed and then etched back to form an offset spacer shape. The film thickness of the first insulating film 41a is the final film thickness difference between the left MISFET and the right MISFET.

  Subsequently, as shown in FIG. 11F2, lithography is performed to cover the right MISFET with a resist 44, and the first insulating film 41a of the left MISFET is removed by etching. Thereafter, the resist 44 is removed.

  Subsequently, as shown in FIG. 12 (f3), a first insulating film 41 is formed and then etched back to form an offset spacer shape. The film thickness of the first insulating film 41 is the same as that of the first insulating film 41 in FIG. 8F in the left MISFET. As a result, in the MISFET on the right side, the first insulating films 41a and 41 having a thickness that is the sum of the thickness of the first insulating film 41a for the first time and the thickness of the first insulating film 41 for the second time are stacked. 16 side surfaces are formed.

  Finally, as shown in FIG. 12 (f4), as in the first embodiment, a second insulating film 42 is formed and then etched back to form an offset spacer shape. Then, a sidewall insulating film 43 is formed and etched back so as to be over-etched to form gate sidewalls 17a and 17b.

  As described above, after finishing the manufacturing steps from FIG. 11 (f1) to FIG. 12 (f4), the same manufacturing steps as those in the first embodiment after FIG. 8 (g) are performed. By doing so, the thickness of the first insulating film 41 in FIG. 8F can be changed, and the size of bending the beam can be changed within the chip, whereby different tensile strains can be applied to the MISFET. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

<Third embodiment>
13 and 14 are cross-sectional views showing a semiconductor device and a manufacturing method thereof according to the third embodiment of the present invention. Hereinafter, description will be given based on these drawings. However, in these drawings, the same parts as those in FIG.

  The present embodiment is a semiconductor device using the method << 2 >> described above and a manufacturing method thereof. In this case, it is only necessary to change (f) in FIG. 8 of the manufacturing method of the first embodiment to FIGS. 13 (f5) to 14 (f8). FIG. 13 (f5) to FIG. 14 (f8) are cross-sectional views showing the state of each manufacturing process in the present embodiment. Each cross-sectional view shows a cross section in the gate length direction of the MISFET. In each cross-sectional view, two MISFETs are shown. Finally, the left MISFET and the right MISFET have different film thicknesses corresponding to the second insulating film in FIG. 8F, and the left MISFET film is thinner.

  First, as shown in FIG. 13 (f5), a first insulating film 41 is formed, and then etched back to form an offset spacer shape. Subsequently, a second insulating film 42a is formed, and then etched back to obtain an offset spacer shape. The film thickness of the second insulating film 42a is the final film thickness difference between the left MISFET and the right MISFET.

  Subsequently, as shown in FIG. 13 (f6), lithography is performed to cover the right MISFET with a resist 44, and the second insulating film 42a of the left MISFET is removed by etching. Thereafter, the resist 44 is removed.

  Subsequently, as shown in FIG. 14 (f7), a second insulating film 42 is formed and then etched back to form an offset spacer shape. The film thickness of the second insulating film 42 is the same as that of the second insulating film 42 in FIG. 8F in the left MISFET. As a result, in the MISFET on the right side, the second insulating films 42a and 42 having a thickness obtained by combining the thickness of the second insulating film 42a for the first time and the thickness of the second insulating film 42 for the second time are formed in the gate stack. Formed on the side of the body 16.

  Finally, as shown in FIG. 14 (f8), a sidewall insulating film 43 is formed and etched back so as to be overetched to form gate sidewalls 17a and 17c.

  As mentioned above, after finishing the manufacturing process of FIG.13 (f5)-FIG.14 (f6), the manufacturing process similar to 1st embodiment after FIG.8 (g) is performed. By doing so, the thickness of the second insulating film in FIG. 8F can be changed to change the bendability (difficulty of bending) of the beam, thereby giving different tensile strains to the MISFET. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

  It is also possible to carry out by combining the methods << 1 >> and << 2 >>. As described in the second and third embodiments above, tensile strains having different sizes can be applied to different MISFETs in one chip. As a result, it is possible to give different distortion to transistors in a specific layout position, and to give different distortion for each transistor that plays a different role in the chip, such as a core transistor and an I / O transistor. become.

<Fourth embodiment>
15 to 22 are sectional views showing a semiconductor device and a manufacturing method thereof according to the fourth embodiment of the present invention. Hereinafter, description will be given based on these drawings. However, in these drawings, the same parts as those in FIGS.

  In this embodiment, the present invention is applied to a CMOS (Complementary MOS) device. As described above, when tensile stress is applied in the gate length direction of the MISFET to distort the crystal lattice, electron mobility is improved and hole mobility is degraded. However, the gate length direction of the MISFET is the <110> direction of the Si (100) plane. For this reason, when the technique described in the first to third embodiments is applied to the p-channel MISFET, the on-current of the p-channel MISFET is reduced. Therefore, it is necessary to manufacture a CMOS device without using the techniques of the first to third embodiments for the p-channel type MISFET. A manufacturing method according to the fourth embodiment for manufacturing a CMOS device will be described below with reference to FIGS. 15 to 22 are cross-sectional views showing the state of each manufacturing process of the CMOS device of the present invention. Each cross-sectional view shows a cross section in the gate length direction of the MISFET, and an n-channel MISFET is shown on the left side and a p-channel MISFET is shown on the right side.

  First, as shown in FIG. 15A, the element isolation structure 19 is formed on the semiconductor substrate 13 as in FIG. 7A of the first embodiment.

Subsequently, as shown in FIG. 15B, lithography is performed to cover the region that becomes the p-channel type MISFET with a resist 44, and p-well implantation is performed in the region that becomes the n-channel type MISFET to form the p-well 20. . Further, ion implantation for adjusting a threshold value is performed in a region to be an n-channel MISFET. For example, as p-well implantation, monovalent B ions are implanted at an acceleration energy of 150 keV and a dose of 8 × 10 ¹² cm ⁻² . Further, as ion implantation for threshold adjustment, monovalent B ions are implanted at an acceleration energy of 15 keV and a dose of 8 × 10 ¹² cm ⁻² . Thereafter, the resist 44 is peeled off.

Subsequently, as shown in FIG. 16C, lithography is performed to cover the region to be the n-channel type MISFET with a resist 44, and n-well implantation is performed to the region to be the p-channel type MISFET to form an n-well 50. . Further, ion implantation for threshold adjustment is performed in a region to be a p-channel type MISFET. For example, as an n-well implantation, monovalent P ions are implanted at an acceleration energy of 350 keV and a dose of 1.5 × 10 ¹³ cm ⁻² . As ion implantation for threshold adjustment, monovalent As ions are implanted at an acceleration energy of 80 keV and a dose of 2.5 × 10 ¹² cm ⁻² . Thereafter, the resist 44 is peeled off.

Subsequently, as shown in FIG. 16D, a gate insulating film 14 and a poly-Si layer 15a are formed on the semiconductor substrate 13, as in FIG. 7C of the first embodiment. In the case where pre-doping is performed after the formation of the poly-Si layer 15a, the following steps are necessary. Lithography is performed to cover a region to be a p-channel type MISFET with a resist, and monovalent P ions, for example, are implanted into the region to be an n-channel type MISFET at an acceleration energy of 4 keV and a dose of 4 × 10 ¹⁵ cm ^−2. To peel off. Then, lithography is performed to cover the region to be an n-channel MISFET with a resist, and monovalent B ions, for example, are implanted into the region to be a p-channel MISFET with an acceleration energy of 1 keV and a dose of 5 × 10 ¹⁵ cm ⁻² . Thereafter, the resist is peeled off.

  Subsequently, as shown in FIG. 17E, similarly to FIG. 7D of the first embodiment, lithography is performed, and the poly-Si layer 15a is etched using a resist (not shown) as a mask. After the etching, the resist mask is peeled off. Then, an n-channel MISFET gate stack 16a and a p-channel MISFET gate stack 56a are formed. When the poly-Si layer 15a is pre-doped in the step of FIG. 16D, annealing is performed after the formation of the n-channel MISFET gate stack 16a and the p-channel MISFET gate stack 56a. Activate the impurities. For example, spike annealing at 1030 ° C. is performed.

Subsequently, as shown in FIG. 17F, lithography is performed to cover the p-channel type MISFET with a resist 44, and extension implantation of the n-channel type MISFET is performed, whereby the S / D extension electrode 21 of the n-channel type MISFET. Form. For example, monovalent As ions are implanted at an acceleration energy of 1 keV and a dose of 5 × 10 ¹⁴ cm ^{−2 using} the gate stacked body 16a and the resist 44 as a mask. Although not shown in FIG. 17F and the subsequent drawings, ion implantation for forming a pocket region may be performed before or after ion implantation for forming the S / D extension electrode 21. For example, monovalent BF ₂ ions are implanted at a dose of 2 × 10 ¹³ cm ⁻² . Thereafter, the resist 44 is peeled off.

Subsequently, as shown in FIG. 18G, lithography is performed so that the n-channel MISFET is covered with a resist 44, and extension implantation of the p-channel MISFET is performed, so that the S / D extension electrode 51 of the p-channel MISFET. Form. For example, monovalent B ions are implanted with an acceleration energy of 0.3 keV and a dose of 5 × 10 ¹⁴ cm ^{−2 using} the gate stacked body 56 a and the resist 44 as a mask. Although not shown in FIG. 18G and the subsequent drawings, ion implantation for forming a pocket region may be performed before or after ion implantation for forming the S / D extension electrode 51. . For example, monovalent As ions are implanted at a dose of 2 × 10 ¹³ cm ⁻² . Thereafter, the resist 44 is peeled off.

  Subsequently, as shown in FIG. 18H, a gate sidewall 17a is formed in the same manner as in FIG. 8F of the first embodiment. As described above, the n-channel MISFET and the p-channel MISFET are simultaneously formed with the offset spacer-shaped first insulating film 41, the offset spacer-shaped second insulating film 42, and finally the sidewall insulating film 43. Is formed.

  In FIGS. 17F and 18G, extension implantation is performed using only the gate stacked bodies 16a and 56a as a mask in addition to the resist 44. However, extension implantation may be performed after the first insulating film 41 of FIG. 18H is formed in the gate stacked bodies 16a and 56a or after the second insulating film 42 of FIG. 18H is formed. .

  Generally, the diffusion constant of the dopant that forms the S / D extension electrode 51 of the p-channel type MISFET is larger than the diffusion constant of the dopant that forms the S / D extension electrode 21 of the n-channel type MISFET. Therefore, you may take the following manufacturing processes. First, the S / D extension electrode 21 is formed by performing ion implantation using the gate stacked body 16a and the resist 44 as a mask, and then the first insulating film 41 having an offset spacer shape is formed. Subsequently, the S / D extension electrode 51 is formed by performing ion implantation using the gate stacked body 56a, the first insulating film 41, and the resist 44 as a mask. Finally, after forming a second insulating film 42 having an offset spacer shape, a sidewall insulating film 43 is formed.

  For the same reason, the following manufacturing process may be adopted. First, the S / D extension electrode 21 is formed by performing ion implantation using the gate stacked body 16a, the offset spacer-shaped first insulating film 41 and the resist 44 as a mask, and then the offset spacer-shaped first electrode. Two insulating films 42 are formed. Subsequently, the S / D extension electrode 51 is formed by performing ion implantation using the gate stacked body 56a, the first insulating film 41, the second insulating film 42, and the resist 44 as a mask. Finally, a sidewall insulating film 43 is formed.

Subsequently, as shown in FIG. 19I, lithography is performed to cover the p-channel type MISFET with a resist 44, and S / D implantation is performed to form a deep S / D electrode 22. For example, monovalent As ions are implanted at an acceleration energy of 5 keV and a dose of 5 × 10 ¹⁴ cm ^{−2 using} the gate stacked body 16a, the gate sidewall 17a, and the resist 44 as a mask, and further monovalent P ions are accelerated. Implantation is performed with an energy of 3 keV and a dose of 4 × 10 ¹⁵ cm ⁻² . Thereafter, the resist 44 is peeled off.

Subsequently, as shown in FIG. 19J, lithography is performed to cover the n-channel MISFET with a resist 44, and S / D implantation is performed to form a deep S / D electrode 52. For example, monovalent B ions are implanted at an acceleration energy of 1 keV and a dose of 3 × 10 ¹⁵ cm ^{−2 using} the gate stacked body 56a, the gate sidewall 17a, and the resist 44 as a mask. Thereafter, the resist 44 is peeled off.

  Subsequently, as shown in FIG. 20K, the impurity is activated in the same manner as in FIG. 9H of the first embodiment.

  Subsequently, as shown in FIG. 20L, lithography is performed to cover the p-channel type MISFET with a resist 44. After that, as in the first embodiment, the first insulating film 41 and the sidewall insulating film 43 of the n-channel MISFET are removed. Thereafter, the resist 44 is peeled off. Thus, the cantilever-shaped second insulating film 42 is formed in the vicinity of the gate stacked body 16a only in the n-channel type MISFET region.

  Subsequently, as shown in FIG. 21 (m), the entire semiconductor substrate 13 is immersed in the liquid 35 as in FIG. 9 (j) of the first embodiment.

  Subsequently, as shown in FIG. 21 (n), the liquid 35 is dried as in FIG. 10 (k) of the first embodiment. In this process, the surface tension of the liquid 35 affects only the n-channel MISFET in which the distance between the gate stack 16a and the cantilever-shaped second insulating film 42 is narrow. As a result, in the n-channel MISFET, as in the first embodiment, the second insulating film 42 bends toward the gate stacked body 16a and adheres to the gate stacked body 16a. As a result, the second insulating film 42 becomes the beam 11. On the other hand, in the p-channel type MISFET, since a structure that can be bent is not formed, the shapes of the gate stacked body 56a and the gate sidewall 17a are not changed.

  When the wet process is used in the resist 44 peeling process of FIG. 20L, the process of FIG. 21M is automatically performed at the stage of immersion in the liquid used in the wet process. . That is, when the last liquid used in the wet process of the resist 44 peeling process is dried, the process of FIG. 21 (n) is automatically performed. The subsequent steps are the same as those in the first embodiment.

  Subsequently, as shown in FIG. 22 (o), as in FIG. 10 (l) of the first embodiment, silicides 15b and 22b are respectively formed on the gate stacked bodies 16a and 56a and the deep S / D electrodes 22 and 52, respectively. , 52b. Thereby, the gate stacked bodies 16a and 56a become the gate stacked bodies 16 and 56, respectively.

  Finally, as shown in FIG. 22 (p), as in FIG. 10 (m) of the first embodiment, the stopper nitride films 25a and 25b and the interlayer insulating film 23 are deposited, and CMP, lithography and etching are performed. And contact holes are formed. A contact 24 is formed by embedding a metal in the contact hole.

  In this embodiment, there are n-channel type MISFETs and p-channel type MISFETs. Therefore, instead of the single stopper nitride film 25 of FIG. The stopper nitride film 25a brings a tensile stress to the channel region of the n-channel type MISFET, and the stopper nitride film 25b brings a compressive stress to the channel region of the p-channel type MISFET.

  As described above, a CMOS device can be obtained by using the manufacturing method of this embodiment. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

<Fifth embodiment>
23 to 25 are sectional views showing a semiconductor device and a manufacturing method thereof according to the fifth embodiment of the present invention. Hereinafter, description will be given based on these drawings. However, in these drawings, the same parts as those in FIGS. 20 to 22 are denoted by the same reference numerals.

  In the present embodiment, as in the fourth embodiment, the present invention is applied to a CMOS device. However, in this embodiment, unlike the fourth embodiment, the channel direction is, for example, the <100> direction of the Si (100) plane. That is, a case where the degree of mobility decrease is small even when tensile stress is applied in the gate length direction of the p-channel MISFET will be described. In this case, when the present invention is applied to a p-channel type MISFET, the on-current is reduced, but the effect of reducing the parasitic capacitance due to the introduction of the air gap into the gate sidewall exceeds or the effect of reducing the parasitic capacitance compensates for the on-current reduction. The operation speed does not change. In the fourth embodiment, the present invention is applied only to the n-channel MISFET, and the p-channel MISFET is a general-purpose one. In the present embodiment, the present invention is applied to both an n-channel MISFET and a p-channel MISFET. If it carries out like this, the number of processes can be reduced compared with 4th embodiment by using the manufacturing method which is mentioned later.

  The manufacturing method of the fourth embodiment for obtaining a CMOS device will be described below with reference to FIGS. 23 to 25 are cross-sectional views showing the state of each manufacturing process of the CMOS device in the present embodiment. Each cross-sectional view shows a cross section in the gate length direction of the MISFET, and an n-channel MISFET is shown on the left side and a p-channel MISFET is shown on the right side.

  In the manufacturing method of this embodiment, the steps from FIG. 15A to FIG. 19J are the same as the manufacturing method of the fourth embodiment.

  First, as shown in FIG. 23 (k), after the step of FIG. 19 (j), the impurity is activated as in FIG. 9 (h) of the first embodiment.

  Subsequently, as shown in FIG. 23L, the first insulating film 41 and the sidewall insulating film 43 are removed as in FIG. 9I of the first embodiment.

  Subsequently, as shown in FIG. 24M, the entire semiconductor substrate 13 is immersed in the liquid 35 as in FIG. 9J of the first embodiment.

  Subsequently, as shown in FIG. 24 (n), the liquid 35 is dried as in FIG. 10 (k) of the first embodiment. Through these steps, the second insulating film 42 bends and adheres to the gate stacks 16a and 56a in both the n-channel MISFET and the p-channel MISFET. As a result, the second insulating film 42 becomes the beam 11. The subsequent steps are the same as those in the first embodiment.

  Subsequently, as shown in FIG. 25 (o), as in FIG. 10 (l) of the first embodiment, the gate stacks 16a and 56a and the deep S / D electrodes 22 and 52 are provided with silicide layers 15b and 22b, 52b is formed. As a result, the gate stacked bodies 16 a and 56 a become the gate stacked bodies 16 and 56.

  Finally, as shown in FIG. 25 (p), as in FIG. 10 (m) of the first embodiment, the stopper insulating films 25a and 25b and the interlayer insulating film 23 are deposited, and CMP, lithography and etching are performed. By doing so, a contact hole is formed. A contact 24 is formed by embedding a metal in the contact hole.

  In this embodiment, since there are an n-channel MISFET and a p-channel MISFET, the stopper nitride films 25a and 25b are formed by applying the DSL technique instead of the single stopper nitride film 25 in FIG. Use. The stopper nitride film 25a brings a tensile stress to the channel region of the n-channel type MISFET, and the stopper nitride film 25b brings a compressive stress to the channel region of the p-channel type MISFET.

  As described above, even if the p-channel type MISFET is subjected to tensile strain due to the beam in the gate length direction, since the decrease in the on-current due to the decrease in mobility is small, a gap is introduced into the gate side wall and the parasitic capacitance is introduced. Since the influence of the decrease in the on-current is compensated by reducing the current, the operation of the p-channel MISFET may be unchanged or accelerated. In these cases, the CMOS device can be manufactured with a smaller number of steps by using the manufacturing method of the present embodiment. This is because according to the manufacturing method of the present embodiment, the number of lithography processes can be reduced by one as compared with the manufacturing method of the fourth embodiment. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

<Sixth embodiment>
26 and 27 are cross-sectional views showing a semiconductor device and a manufacturing method thereof according to the sixth embodiment. Hereinafter, description will be given based on these drawings.

  As the first to fifth embodiments, a technique is described in which a deflected beam formed of an insulator is used as a part of a gate sidewall structure in a MISFET, and a region to which stress is applied by the deflected beam is used as a channel region. Stated. In this embodiment, as other aspects, in a pin (p-intrinsic-n) photodiode, the semiconductor is distorted by stress from the deflected beam, and the mobility of carriers in the distorted region is improved. An example in which higher speed operation is possible will be described.

In general, the response speed of the pin photodiode (here, the diode output rise time T) is approximated by the following equation.
T = (Ta ² + Tb ² + Tc ² ) ^1/2 (5)
In the equation (5), Ta is a time constant of inter-terminal capacitance (= sum of package capacitance and photodiode junction capacitance) and load resistance, Tb is the diffusion time of carriers generated outside the depletion layer, and Tc is the carrier time Depletion layer travel time.

Of these, Tc is approximated by the following equation, where d is the depletion layer length (in a pin photodiode, the sum of the depletion layer length and intrinsic region), E is the average electric field, and μ is the carrier mobility. It is expressed in
Tc = d / (μE) (6)

  Therefore, from the equations (5) and (6), if the carrier mobility μ increases, the response speed of the pin photodiode is improved.

  FIG. 27E is a structural schematic diagram of the semiconductor device of the present embodiment. FIG. 27E is a cross-sectional view of the semiconductor device, which is a cross-sectional view along the direction in which current flows. FIG. 27 (e) shows a state before electrode formation. First, the outline | summary of the semiconductor device 60 of this embodiment is demonstrated based on drawing.

  The semiconductor device 60 has a bent shape and a beam 61 as a bent shape portion that generates a stress P from the shape, and a semiconductor portion 62 in which the carrier mobility is changed by receiving the stress P of the beam 61 and being distorted. And a pin photodiode.

  According to the semiconductor device 60, by using the beam 61 having a bent shape and distorting the semiconductor portion 62 using the stress P of the beam 61, the strain is reduced by a method different from the contact etch stop film method. Therefore, it is possible to solve the problem of reducing the effect accompanying the progress of miniaturization of the contact etch stop film system.

  The beam 61 is a beam in which one end 61a and the other end 61b are fixed in a bent state. The semiconductor part 62 is formed on the surface of the semiconductor substrate 13, one end 61 a of the beam 61 is fixed to the surface of the semiconductor substrate 13, and the stress P of the beam 61 acts on the semiconductor part 62 through the one end 61 a. The semiconductor substrate 13 is a Si substrate.

  The semiconductor unit 62 includes a p-type region 62p, an intrinsic region 62i, and an n-type region 62n. The semiconductor device 60 has an n-type electrode layer 63 as a convex portion formed on the surface of the semiconductor substrate 13, and has a bilaterally symmetric structure with the n-type electrode layer 63 and the n-type region 62n as the center. That is, the semiconductor device 60 has a pair of beams 61, a pair of p-type regions 62p, and a pair of intrinsic regions 62i. The beam 61 has one end 61a fixed to the intrinsic region 62i, the other end 61b fixed to the n-type electrode layer 63, and is bent in the direction of the n-type region 62n.

  Next, details of the semiconductor device 60 of the present embodiment will be described with reference to the drawings.

  As shown in FIG. 27E, the semiconductor device 60 has a bent beam 61 made of an insulator. The beam 61 has one end 61 a serving as a fulcrum in an intrinsic region 62 i formed in the semiconductor substrate 13, and the other end 61 b is attached to the n-type electrode layer 38 as a convex portion. Note that the beam 61 is configured not to block received light. For example, the beam 61 is made of a transparent insulator material. Alternatively, when the light receiving window is formed in a jumping manner in the depth direction of the drawing, the beam 61 is not formed in the window portion. The n-type electrode layer 63 is connected to the n-type region 62n and extends upward in a convex shape from the n-type region 62n. In the semiconductor device 60, stress acts from the one end 61a of the deflected beam 61 toward the p-type region 62p. Therefore, the n-type region 62n side of the intrinsic region 62i and the depletion layer of the n-type region 62n are tensile-strained. The 62i side of the p-type region 62p and the depletion layer of the p-type region 62p are subjected to compressive strain.

  When the semiconductor unit 62 receives light having energy greater than or equal to the band gap, an electron / hole pair is generated. Here, the operation of the semiconductor device 60 in a state where the pin junction is reverse-biased will be described. First, we will talk about electrons. The electrons excited in the conduction band of the p-type region 62p are extinguished by recombination with holes except for electrons reaching the depletion layer within the minority carrier lifetime. The electrons that reach the depletion layer within the minority carrier lifetime are electrons excited within the minority carrier diffusion length from the end of the depletion layer. The electrons that reach the depletion layer are accelerated by the electric field and move to the n-type region 62n through the depletion layer of the n-type region 62n. Similarly, the electrons excited in the conduction band of the intrinsic region 62i are accelerated by the electric field and move to the n-type region 62n through the depletion layer of the n-type region 62n.

  Thus, the electrons excited in the conduction band move to the n-type region 62n by the electric field. Therefore, more electrons are present in the depletion layer of the n-type region 62n and the n-type region 62n of the intrinsic region 62i than in the depletion layer of the p-type region 62p and the p-type region 62p of the intrinsic region 62i. . In the semiconductor part 62, due to the stress P caused by the bent beam 61, the electron mobility changes as follows. Since the intrinsic region 62i and the depletion layer of the p-type region 62 on the p-type region 62p side are subjected to compressive strain, the mobility of electrons decreases. On the other hand, the n-type region 62n side of the intrinsic region 62i and the depletion layer of the n-type region 62n are subjected to tensile strain, so that the electron mobility is improved. Here, for the reasons described above, the number of electrons existing in the portion where the mobility is increased is larger than the number of electrons existing in the portion where the mobility is decreased. Accordingly, when considering the entire semiconductor portion 62, the mobility of electrons is improved.

  Similarly, in the semiconductor portion 62, due to the stress P caused by the bent beam 61, the hole mobility changes as follows. Since the intrinsic region 62i side of the p-type region 62p and the depletion layer of the p-type region 62p are subjected to compressive strain, the mobility of holes is improved. On the other hand, in the n-type region 62n side of the intrinsic region 62i and the depletion layer of the n-type region 62n, since tensile strain is applied, the hole mobility is lowered. Here, since the number of holes present in the portion where the mobility is increased is larger than the number of holes present in the portion where the mobility is lowered, the mobility of the holes is improved when the semiconductor portion 62 is considered as a whole. To do.

  From the above, in the structure such as the semiconductor device 60, the carrier mobility is improved, so that the response speed as a pin photodiode is improved.

  Next, a method for manufacturing the semiconductor device 60 will be described with reference to FIGS.

  First, as shown in FIG. 26A, a semiconductor substrate 13 made of Si is prepared, and an STI method or a LOCOS method is used so that a current flows in the <110> direction of the (100) plane. An element isolation insulating film 19 is formed.

  Subsequently, as shown in FIG. 26B, the p-type region 62n, the intrinsic region 62i, and the n-type region 62n are formed by repeating lithography, ion implantation, and resist peeling a plurality of times on the surface of the semiconductor substrate 13. To do.

  Subsequently, as shown in FIG. 26C, an n-doped poly-Si layer 63a is deposited on the p-type region 62n, the intrinsic region 62i, and the n-type region 62n.

  Subsequently, as shown in FIG. 27 (d), the n-doped poly-Si layer 63a is subjected to lithography and etching, and the resist is removed, thereby forming the n-type electrode layer 63 as a convex portion on the n-type region 62n. Form.

  Subsequently, as shown in FIG. 27 (e), as in the above-described embodiments, one end 61a serving as a fulcrum forms a cantilever beam positioned in the intrinsic region 36, and the other cantilever beam is bent. The beam 61 is formed by attaching the end 61 b to the n-type electrode layer 63.

  Thereafter, the introduced impurity is activated to form electrodes (not shown) on the surface of the p-type region 62p and the surface of the n-type electrode layer 63, thereby completing the semiconductor device 60 as a pin photodiode. .

  The material of the semiconductor substrate is not limited to Si, and may be SiGe, SiC, or the like, for example. Further, the semiconductor device of this embodiment may be a pn photodiode instead of a pin photodiode. In this case, the position of the fulcrum of the beam is the pn junction boundary. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

<Others>
The configuration of the present invention can also be expressed as follows.

  1. A semiconductor device in which a carrier moves in a region to which stress is applied by a bent beam formed of an insulator. 2. 2. The semiconductor device according to claim 1, wherein the beam is a cantilever whose one end is fixed to the substrate, and a tensile strain is applied to a region where the carrier moves due to a stress acting on the fulcrum. 3. 3. The semiconductor device as described in 1 or 2 above, wherein the beam is used as a part of a gate sidewall structure of an FET. 4). 4. The semiconductor device according to any one of claims 1 to 3, wherein the gate sidewall structure includes a gap in addition to the beam. 5. 5. The semiconductor device according to any one of 1 to 4, wherein the beam has a front end portion of the beam attached to a gate of the FET. 6). 6. The semiconductor device as described in 5 above, wherein the strain applied by the beam is controlled by the length in the gate length direction of the beam before bending and the distance between the beam and the gate before bending. 7. A semiconductor device having a plurality of FETs, wherein at least one of the length in the gate length direction of the beam before bending and the distance between the beam and the gate before bending is different, different strains are introduced. 7. The semiconductor device according to 6 above, comprising at least two types of FETs. 8). The semiconductor device having an n-type FET and a p-type FET, wherein only the n-type FET uses the beam as a part of a gate sidewall structure. A semiconductor device according to 1. 9. 9. The semiconductor device according to claim 8, wherein a channel direction of the semiconductor device having the n-type FET and the p-type FET is the <110> direction of the Si (100) plane. 10. A semiconductor device having an n-type FET and a p-type FET, wherein the beam is used as part of a gate sidewall structure for both the n-type FET and the p-type. The semiconductor device according to any one of 1 to 7. 11 9. The semiconductor device according to claim 8, wherein a channel direction of the semiconductor device having the n-type FET and the p-type FET is the <100> direction of the Si (100) plane. 12 12. The semiconductor device according to any one of 1 to 11, wherein the beam material is a Si nitride film. 13. A method of manufacturing a semiconductor device in which a carrier moves in a region where stress is applied by a bent beam formed of an insulator, and a straight beam of a cantilever structure formed of an insulator is positioned in the vicinity thereof Forming a space between the structure and the structure, filling the space with a liquid, drying the liquid, and attaching the tip of the beam to the structure to form a bent beam A method for manufacturing a semiconductor device. 14 14. The method of manufacturing a semiconductor device as described in 13, wherein the liquid is water or mercury. 15. Forming a second type insulating film having an offset spacer shape in contact with the gate; forming a second type insulating film having an offset spacer shape in contact with the second type insulating film; and Forming a second type of insulating film in the shape of a sidewall in contact with the insulating film, and removing the second type of insulating film to form a straight cantilever made of the second type of insulating film An FET manufacturing method comprising: a step, a step of filling a space between the gate and the cantilever with a liquid; and a step of drying the liquid and attaching the cantilever to the gate to bend. 16. The beam is a cantilever whose one end is fixed to the substrate, the position of the fulcrum is at the intrinsic region of the pin diode or the junction boundary of the pn diode, and the beam is bent toward the n-type region. The semiconductor device as described in 1 above.

  The effect of the present invention can also be expressed as follows.

  In the present invention, after forming a cantilever structure with an insulator, this is bent and the reaction force acting on the fulcrum of the bent cantilever is used as the tensile stress to the semiconductor layer that becomes the channel region of the FET. , Generate distortion. Such a structure is suitable for miniaturization because stress is applied from a position closer to the channel region as compared with the DSL technique. In addition, the structure in which the strain applied to the channel region can be controlled by bending has an advantage that the design of the semiconductor device is facilitated. Further, in the method of the present invention, since the gate side wall structure includes the air gap, the parasitic capacitance is reduced, so that the FET can be operated at high speed.

  Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention. Further, the present invention includes a combination of some or all of the configurations of the above-described embodiments as appropriate.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-050113 for which it applied on February 29, 2008, and takes in those the indications of all here.

  According to the present invention, a bent shape portion having a bent shape is used, and the semiconductor portion is distorted by using the stress generated from the bent shape portion, and the distortion is performed by a method different from the contact etch stop film method. This can contribute to the solution of the problem of reducing the effect accompanying the progress of miniaturization of the contact etch stop film system.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. It is a principal part enlarged view of FIG. It is sectional drawing for demonstrating the relationship between the deflection | deviation of the beam in 1st embodiment, and the stress which acts on a semiconductor part. It is sectional drawing for demonstrating the bending method of the beam in 1st embodiment. It is sectional drawing (the 1) for demonstrating the force which a semiconductor part receives from the beam which bent in 1st embodiment. It is sectional drawing for demonstrating the force which a semiconductor part receives from the bent beam in 1st embodiment (the 2). It is sectional drawing (the 1) which shows the semiconductor device which concerns on 1st embodiment, and its manufacturing method. It is sectional drawing (the 2) which shows the semiconductor device which concerns on 1st embodiment, and its manufacturing method. It is sectional drawing (the 3) which shows the semiconductor device which concerns on 1st embodiment, and its manufacturing method. It is sectional drawing (the 4) which shows the semiconductor device which concerns on 1st embodiment, and its manufacturing method. It is sectional drawing (the 1) which shows the semiconductor device which concerns on 2nd embodiment, and its manufacturing method. It is sectional drawing (the 2) which shows the semiconductor device which concerns on 2nd embodiment, and its manufacturing method. It is sectional drawing (the 1) which shows the semiconductor device which concerns on 3rd embodiment, and its manufacturing method. It is sectional drawing (the 2) which shows the semiconductor device which concerns on 3rd embodiment, and its manufacturing method. It is sectional drawing (the 1) which shows the semiconductor device which concerns on 4th embodiment, and its manufacturing method. It is sectional drawing (the 2) which shows the semiconductor device which concerns on 4th embodiment, and its manufacturing method. It is sectional drawing (the 3) which shows the semiconductor device which concerns on 4th embodiment, and its manufacturing method. It is sectional drawing (the 4) which shows the semiconductor device which concerns on 4th embodiment, and its manufacturing method. It is sectional drawing (the 5) which shows the semiconductor device which concerns on 4th embodiment, and its manufacturing method. It is sectional drawing (the 6) which shows the semiconductor device which concerns on 4th embodiment, and its manufacturing method. It is sectional drawing (the 7) which shows the semiconductor device which concerns on 4th embodiment, and its manufacturing method. It is sectional drawing (the 8) which shows the semiconductor device which concerns on 4th embodiment, and its manufacturing method. It is sectional drawing (the 1) which shows the semiconductor device which concerns on 5th embodiment, and its manufacturing method. It is sectional drawing (the 2) which shows the semiconductor device which concerns on 5th embodiment, and its manufacturing method. It is sectional drawing (the 3) which shows the semiconductor device which concerns on 5th embodiment, and its manufacturing method. It is sectional drawing (the 1) which shows the semiconductor device which concerns on 6th embodiment, and its manufacturing method. It is sectional drawing (the 2) which shows the semiconductor device which concerns on 6th embodiment, and its manufacturing method.

Explanation of symbols

10 Semiconductor device 11 Beam (flexible shape part)
11a One end of the beam 11b The other end of the beam 12 Channel region (semiconductor part)
DESCRIPTION OF SYMBOLS 13 Semiconductor substrate 14 Gate insulating film 15 Gate electrode 15a Poly Si layer 15b Silicide layer 16, 16a Gate laminated body 17, 17a, 17b, 17c Gate side wall 18 Void 19 Element isolation insulating film 20 P well 21 N channel type MISFET S / D extension electrode 22 Deep S / D electrode 22b of n-channel MISFET Silicide layer 23 Interlayer insulating film 24 Contacts 25, 25a, 20b Stopper nitride films 30, 30a, 30s, 30d Cantilever 31 Fixed member 32 Fixed end 33 Concentrated load 34 reaction force 35 liquid 41, 41a first insulating film 42, 42a second insulating film 43 sidewall insulating film 44 resist 50 n well 51 S / D extension electrode 52 of p-channel type MISFET 52 deep S / D of p-channel type MISFET Electrode 52b Side layer 56,56a gate stack 60 semiconductor device 61 beam (deflection shape portion)
61a One end of the beam 61b The other end of the beam 62 Semiconductor portion 62p p-type region 62i intrinsic region 62n n-type region 63 n-type electrode layer (convex portion)
63a n-doped poly-Si layer

Claims (19)

A bent shape portion that has a bent shape and generates stress from the shape, and a semiconductor portion in which the mobility of the carrier has changed due to distortion due to the stress,
A semiconductor device comprising: The bending shape portion is a beam having both ends fixed in a bent state.
The semiconductor device according to claim 1. The semiconductor part is formed on the surface of the semiconductor substrate, one end of the beam is fixed to the surface of the semiconductor substrate, and the stress acts on the semiconductor part through the one end.
The semiconductor device according to claim 2. A channel region formed on the surface of the semiconductor substrate; a gate stack including a gate insulating film and a gate electrode formed on the channel region; and a gate sidewall formed on a side surface of the gate stack. MIS type field effect transistor,
The semiconductor portion is the channel region, the beam is a part of the gate sidewall, and the other end of the beam is fixed to a side surface of the gate stack;
The semiconductor device according to claim 3. The strain applied to the channel region was set by the length of the beam in the gate length direction and the distance from one end of the beam to the side surface of the gate stack,
The semiconductor device according to claim 4. A plurality of MIS type field effect transistors;
The strain applied to the channel region in these MIS field effect transistors makes at least one of the length of the beam in the gate length direction different from the distance from one end of the beam to the side surface of the gate stack. By setting two or more types,
The semiconductor device according to claim 5. The gate sidewall includes a gap surrounded by the beam and the gate stack,
The semiconductor device according to claim 4, wherein: A semiconductor device comprising an n-channel field effect transistor and a p-channel field effect transistor,
Of the n-channel field effect transistor and the p-channel field effect transistor, only the n-channel field effect transistor is the MIS field effect transistor.
The semiconductor device according to claim 4, wherein: A semiconductor device comprising an n-channel field effect transistor and a p-channel field effect transistor,
Both the n-channel field effect transistor and the p-channel field effect transistor are the MIS field effect transistors.
The semiconductor device according to claim 4, wherein: The channel region is made of Si, and the channel direction of the channel region is the <110> direction of the (100) plane of the Si.
The semiconductor device according to claim 4, wherein: The channel region is made of Si, and the channel direction of the channel region is a <100> direction of the (100) plane of the Si.
The semiconductor device according to claim 4, wherein: The beam is made of a Si nitride film;
The semiconductor device according to claim 4, wherein: A pin photodiode having a p-type region, an intrinsic region, and an n-type region respectively formed on the surface of the semiconductor substrate, and a convex portion formed on the surface of the semiconductor substrate;
The semiconductor part is the p-type region, intrinsic region and n-type region;
The beam has one end fixed to the intrinsic region and the other end fixed to the convex portion, and is bent in the direction of the n-type region.
The semiconductor device according to claim 3. A pn photodiode having a p-type region and an n-type region respectively formed on the surface of the semiconductor substrate, and a convex portion formed on the surface of the semiconductor substrate;
The semiconductor portion is the p-type region and the n-type region;
One end of the beam is fixed to the boundary between the p-type region and the n-type region, the other end is fixed to the convex portion, and is bent in the direction of the n-type region.
The semiconductor device according to claim 3. The bent shape portion is made of an insulator;
The semiconductor device according to claim 1, wherein: A first step of forming on the semiconductor substrate a structure in which one end is fixed to the semiconductor substrate and the other end is not fixed anywhere;
A second step of filling a liquid in a space around the structure;
A third step of drying the liquid filled in the space to bend the structure and fix the other end in contact with the semiconductor substrate or another structure on the semiconductor substrate; and
A method for manufacturing a semiconductor device, comprising: The structure is a cantilever formed vertically on the semiconductor substrate;
The other structure is a gate laminate including a gate insulating film and a gate electrode,
In the third step, the other end of the cantilever is fixed in contact with the side surface of the gate stack,
The method of manufacturing a semiconductor device according to claim 16. The first step includes
Forming a first sidewall on a side surface of the gate stack;
Forming a second side wall on a side surface of the first side wall;
Forming the second side wall as the cantilever by removing the first side wall;
The method for manufacturing a semiconductor device according to claim 17, comprising: The liquid is water or mercury;
The method for manufacturing a semiconductor device according to claim 16, wherein the method is a semiconductor device manufacturing method.

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