JPWO2005074035A1 - Field effect transistor and manufacturing method thereof - Google Patents

Abstract

A semiconductor layer projecting upward from the plane of the substrate, a gate electrode extending on opposite side surfaces from the top so as to straddle the semiconductor layer, and gate insulation interposed between the gate electrode and the side surface of the semiconductor layer A cap insulating layer provided on the upper surface of the semiconductor layer and positioned under the gate electrode; and a source / drain region formed in a region of the semiconductor layer not covered by the gate electrode, The layer has a projecting portion projecting from the surface of the gate insulating film in a direction parallel to the plane of the substrate and perpendicular to the channel length direction connecting the pair of source / drain regions. Transistor.

Description

  The present invention relates to a field effect transistor and a manufacturing method thereof.

[Construction]
For the purpose of improving the performance of a field effect transistor, a field effect transistor called FinFET has been proposed, characterized in that a gate electrode is provided on both side surfaces of a protruding semiconductor region and a channel is formed on both side surfaces of the semiconductor region. Yes. The typical structure is shown in FIGS. 81 is a plan view, FIG. 82 (a) is a cross-sectional view taken along the line AA ′ of FIG. 81, and FIG. 82 (b) is a cross-sectional view taken along the line BB ′ of FIG. A buried insulating film 2 is provided on the support substrate 1, and a semiconductor layer 3 is provided thereon. A gate electrode 5 is provided on a side surface of the semiconductor layer 3 via a gate insulating film 4 (FIG. 82A). A portion of the semiconductor layer 3 that is not covered with the gate electrode is doped with a high-concentration first conductivity type impurity to form a source / drain region 6. The semiconductor layer 3 covered with the gate electrode 5 forms a channel formation region 7, and when a suitable voltage is applied to the gate electrode, carriers of the first conductivity type are induced on the surface thereof, thereby forming a channel. In general, a low-concentration second-conductivity type impurity is introduced into the channel formation region or not.

  81 is a cross section in a plane perpendicular to the direction connecting two source / drain regions (hereinafter, this direction is referred to as a channel length direction) at the position where the semiconductor layer is covered by the gate. 81, the BB ′ cross section in FIG. 81 shows a cross section in the channel length direction.

  In the FinFET, when the difference between the thickness of the insulating film provided on the semiconductor layer 3 and the thickness of the insulating film provided on the side surface of the semiconductor layer 3 is small, the channel formation region 7 is formed when the transistor is turned on. Channels are formed on both side surfaces of the semiconductor layer 3 and the upper surface of the semiconductor layer. This structure is called a trigate structure. In a tri-gate transistor, the relationship between the thickness of the insulating film provided on the semiconductor layer 3 and the thickness of the insulating film provided on the side surface of the semiconductor layer 3 is typically such that one film thickness is the other. The film thickness is 1 to 5 times the film thickness, more typically one film thickness is 1 to 2 times the other film thickness, and most ideally both film thicknesses are approximately equal. 82A and 82B show a typical structure of a tri-gate transistor.

  When the cap insulating layer 8 that is sufficiently thicker than the gate insulating film is provided on the semiconductor layer 3, the thickness of the cap insulating layer 8 is typically more than five times the thickness of the gate insulating film, and more typically. In the case of 10 times or more, almost no channel is formed above the semiconductor layer 3, and when the transistor is turned on, the channels formed on both side surfaces of the semiconductor layer 3 are mainly responsible for electrical conduction. This structure is called a double gate structure. 83A and 83B show a typical cross-sectional shape of a double-gate transistor. They are respectively drawn in the A-A ′ section of FIG. 81 and the B-B ′ section of FIG. 81.

  Further, an adverse effect on transistor characteristics due to electric field concentration in the upper corner portion 34 of the semiconductor layer 3 (one of the upper corner portions 34 is surrounded by a broken line in FIGS. 82A and 83A) is prevented. For the purpose, a structure in which the upper corner portion of the semiconductor layer 3 is rounded has also been proposed (Japanese Patent Laid-Open No. 2002-118255: FIG. 28 of Patent Document 1 and related description). This is shown in FIG. Such a structure is formed, for example, by thermally oxidizing the upper corner of the semiconductor layer. FIG. 85 shows a cross-sectional view at the same position as FIG.

The ratio of the thickness of the cap insulating layer 8 to the thickness of the gate insulating film 4 used in the description of the difference between the double gate structure and the trigate structure is based on the case where both have the same dielectric constant. Yes. When the dielectric constants of the two are different, the product obtained by dividing the respective film thicknesses by the respective dielectric constants and multiplying the obtained quotients by a common constant (for example, the dielectric constant of the SiO ₂ film) is used as the equivalent film thickness. The above comparison may be performed.

  On the other hand, Japanese Patent Application Laid-Open No. 2002-270850 (Patent Document 2) aims to suppress a decrease in operation performance due to an increase in parasitic capacitance due to position mismatch or a variation in parasitic resistance, and a source / drain region and a channel. There is disclosed a field effect transistor having an island-like semiconductor crystal layer having a region and a gate electrode provided on each opposite side surface portion of the channel region portion via a gate insulating film. As an embodiment, a configuration in which the width of the island-shaped semiconductor crystal layer in the channel region portion (portion between both gate electrodes) is reduced for the purpose of further suppressing the short channel effect is described. The insulating film on the upper part of the island-like layer has a shape protruding from the side surface of the island-like layer (FIG. 19 of Patent Document 2 and related description). However, in this field effect transistor, the gate electrode is provided separately and insulated on both sides of the island layer.

[Prior art issues]
The problem in the conventional FinFET will be described using an n-channel transistor as an example. Here, an n-channel transistor will be described. However, in a p-channel transistor, if the polarity is reversed (for example, a potential increase in an n-channel transistor can be read as a potential decrease in a p-channel transistor. A decrease in threshold voltage can be read as an increase in threshold voltage in a p-channel transistor.) A similar argument holds.

(First issue)
FIG. 84A and FIG. 84B show the simulation results of the potential distribution at the upper end of the semiconductor layer 3 in the section AA ′ in FIG. 84A shows the case of the tri-gate structure, which corresponds to the cross section of FIG. 82A, and FIG. 84B shows the case of the double gate structure, which corresponds to the cross section of FIG. Is. Contour lines in the figure are equipotential lines based on intrinsic semiconductor silicon, and are −0.4V, −0.2V, 0.0V, 0.2V, 0.4V from the center of the semiconductor layer to the outside. is there. The impurity concentration of the channel region is 8 × 10 ¹⁸ cm ⁻³ , the gate voltage is zero volts, and the gate oxide film thickness is 2 nm. Since the potential is based on intrinsic semiconductor silicon, the potential of n ⁺ -type silicon that is zero-biased is 0.56V, and the potential of the gate that is zero-biased is 0.56V. Note that the simulation results for each element structure shown in this specification are performed under the same conditions as described above unless otherwise specified.

  In both the double gate structure and the trigate structure, the equipotential line is curved at the upper corner portion of the semiconductor layer. This indicates that in the upper corner portion, the electric field from the gate electrode toward the impurity ions concentrates, so that the potential is higher than in other portions of the semiconductor layer. When the potential at the upper corner increases, a parasitic transistor having a low threshold voltage is formed at the upper corner. When the parasitic transistor is formed, there arises a problem that the subthreshold current increases and the off-current increases as shown in FIG.

Such electric field concentration is caused by the electric field from the gate electrode toward the impurity ions, and therefore becomes prominent when the impurity concentration in the channel region is high, typically 5 × 10 ¹⁷ cm ⁻³ or more.

  Such electric field concentration is caused by the electric field from the gate located on the side surface of the semiconductor layer, the electric field from the gate electrode above the semiconductor layer, and the electric field from the side surface of the gate electrode extending above the upper end of the semiconductor layer. This occurs by concentrating on the upper corner of the layer (FIGS. 92A and 92B). 92 (a) and 92 (b) are cross-sectional views at positions corresponding to the upper portion of the semiconductor layer in the cross sections of FIGS. 82 (a) and 83 (a), respectively. An arrow (symbol 46) indicates a gate electric field that causes electric field concentration.

  Therefore, there is a demand for a technology that suppresses the potential increase at the upper corner portion of the semiconductor layer and reduces the influence of the parasitic transistor.

(Second issue)
In addition, as shown in FIG. 85, the upper corner portion 34 of the semiconductor layer 3 is processed into a rounded shape by performing a rounding process such as thermal oxidation, thereby relaxing the electric field at the corner portion and suppressing parasitic transistors. How to do is known.

  However, in this case, the rounded corner portion 9 exposes a crystal plane having a different plane orientation from either the semiconductor side surface or the semiconductor upper surface where the channel is originally formed. On the other hand, the thickness, carrier mobility, and interface state density of the gate insulating film formed by thermal oxidation depend on the plane orientation. Since the basic characteristics of the transistor such as the threshold voltage and the drain current strongly depend on the thickness of the gate insulating film, the carrier mobility, and the interface state density, the rounded corner portion 9 is different from the semiconductor side surface and the semiconductor upper surface. A new parasitic transistor having different characteristics appears, and the characteristics of the FinFET change. In particular, when the radius of curvature of the corner portion is increased in order to strongly suppress the parasitic transistor described in the first problem, the second problem becomes more prominent.

  Therefore, there is a demand for a technique that can suppress a potential increase in a corner portion and suppress a parasitic transistor in a state where the corner portion has a small radius of curvature without rounding the corner portion or even when the corner portion is rounded.

  An object of the present invention is to provide a FinFET having improved element characteristics by preventing the formation of a parasitic transistor at a corner portion of a semiconductor layer protruding from the plane of the FinFET substrate.

  According to the present invention, the following field effect transistor and a method for manufacturing the same can be provided.

(1) A semiconductor layer protruding upward from the plane of the substrate, a gate electrode extending on opposite side surfaces from the upper part so as to straddle the semiconductor layer, and interposed between the gate electrode and the side surface of the semiconductor layer A gate insulating film, a cap insulating layer provided on the semiconductor layer and positioned under the gate electrode, and a source / drain region formed in a region of the semiconductor layer not covered by the gate electrode,
The cap insulating layer has a projecting portion projecting from the surface of the gate insulating film in a direction parallel to the substrate plane and perpendicular to a channel length direction connecting a pair of source / drain regions. Field effect transistor.

  (2) The field effect transistor according to invention 1, wherein the overhanging portion has an overhanging width of 5 nm or more with respect to the surface of the gate insulating film.

  (3) The field effect transistor according to invention 1, wherein the projecting portion has a projecting width of 5 nm or more and 20 nm or less with respect to the surface of the gate insulating film.

  (4) The field effect transistor according to invention 1, 2, or 3, wherein the overhanging portion has an overhanging width with respect to the surface of the gate insulating film that is not less than 2.5 times the thickness of the gate insulating film.

  (5) The field effect transistor according to invention 1, 2, or 3, wherein the overhanging portion has an overhanging width with respect to the surface of the gate insulating film that is not less than 2.5 times and not more than 10 times the thickness of the gate insulating film.

  (6) The electric field according to any one of inventions 1 to 5, wherein the projecting portion projects from the surface of the gate insulating film at a position where the width in the direction parallel to the substrate plane of the semiconductor layer and perpendicular to the channel length direction is the widest. Effect transistor.

(7) A method of manufacturing a field effect transistor according to any one of inventions 1 to 6,
Forming a cap insulating layer on the semiconductor layer, patterning the semiconductor layer and the cap insulating layer to form a semiconductor layer protruding upward from a substrate plane, and forming a patterned cap insulating layer thereon;
Etching the side surface of the semiconductor layer so that the side surface of the semiconductor layer under the cap insulating layer recedes inward from the end of the cap insulating layer; and
And a step of forming a gate insulating film on a side surface of the semiconductor layer.

(8) depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode;
The method of manufacturing a field effect transistor according to invention 7, further comprising a step of forming a source / drain region by introducing impurities into the semiconductor layer.

(9) A semiconductor layer protruding upward from the substrate plane, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer, and the gate A source / drain region formed in a region not covered by the electrode,
The field effect transistor further comprises a low dielectric constant region having a dielectric constant lower than that of SiO _{2 at a} position lower than the upper end of the gate electrode above the semiconductor layer.

(10) The field effect transistor according to invention 9 having a low dielectric constant region having a dielectric constant lower than that of SiO _{2 in} contact with the upper portion of the semiconductor layer.

(11) A protective insulating film having a higher dielectric constant than SiO ₂ or SiO ₂ is provided in contact with the upper portion of the semiconductor layer, and a low dielectric constant region having a lower dielectric constant than SiO ₂ is formed on the protective insulating film. The field effect transistor of invention 9 which has.

  (12) The field effect transistor according to any one of inventions 9 to 11, wherein the low dielectric constant region comprises a cavity.

(13) The field effect transistor according to any one of inventions 9 to 12, wherein a low dielectric constant region having a dielectric constant lower than that of SiO ₂ is provided below the semiconductor layer.

(14) The invention has a low dielectric constant region having a dielectric constant lower than that of SiO ₂ below the semiconductor layer, and no low dielectric constant region having a dielectric constant lower than that of SiO ₂ below the gate electrode. The field effect transistor of any one of 9-12.

  (15) The field effect transistor according to invention 13 or 14, wherein the low dielectric constant region provided under the semiconductor layer comprises a cavity.

(16) The semiconductor layer is provided on the first insulating layer via a second insulating layer made of a material different from the first insulating layer,
The field effect transistor according to any one of inventions 9 to 12, wherein the gate electrode has a portion directly in contact with the first insulating layer without passing through the second insulating layer on the first insulating layer.

(17) The field effect transistor according to invention 16, wherein the second insulating layer is made of a material having a dielectric constant lower than that of SiO ₂ .

  (18) The field effect transistor according to invention 16, wherein the second insulating layer comprises a cavity.

(19) The field effect transistor according to any one of inventions 1 to 6, wherein at least a part of the cap insulating layer is made of a low dielectric constant material having a dielectric constant lower than that of SiO ₂ .

  (20) The field effect transistor according to any one of inventions 1 to 6, wherein a cavity is provided in at least a part of the cap insulating layer.

(21) The field effect transistor according to invention 20, comprising a protective insulating film having a dielectric constant higher than that of SiO ₂ or SiO ₂ between the semiconductor layer and the cavity.

(22) The field effect transistor according to any one of inventions 1 to 6, wherein a low dielectric constant region having a dielectric constant lower than that of SiO ₂ is provided below the semiconductor layer.

(23) The invention has a low dielectric constant region having a dielectric constant lower than that of SiO ₂ below the semiconductor layer, and does not have a low dielectric constant region having a dielectric constant lower than that of SiO ₂ below the gate electrode. The field effect transistor of any one of 1-6.

  (24) The field effect transistor according to invention 22 or 23, wherein the low dielectric constant region comprises a cavity.

(25) A method for producing a field effect transistor according to invention 9,
Depositing a material having a lower dielectric constant than SiO ₂ on the semiconductor layer to form a low dielectric constant film;
A field effect transistor having a step of patterning the semiconductor layer and the low dielectric constant film to form a semiconductor layer protruding from the plane of the substrate and a low dielectric constant region comprising the low dielectric constant film patterned thereon Manufacturing method.

(26) forming a gate insulating film on a side surface of the protruding semiconductor layer;
Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
26. The method of manufacturing a field effect transistor according to invention 25, further comprising the step of forming a source / drain region by introducing impurities into the semiconductor layer.

(27) A method for producing a field effect transistor according to invention 9,
Forming a dummy layer on the semiconductor layer;
Patterning the semiconductor layer and the dummy layer to form a semiconductor layer protruding from the substrate plane and a patterned dummy layer thereon;
Removing the dummy layer and forming a cavity as the low dielectric constant region above the semiconductor layer.

(28) forming a gate insulating film on a side surface of the protruding semiconductor layer;
Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
A step of forming a source / drain region by introducing impurities into the semiconductor layer;
28. The method of manufacturing a field effect transistor according to claim 27, wherein the low dielectric constant region comprising the cavity is formed by removing the dummy layer after forming the gate electrode.

(29) The method for manufacturing a field effect transistor according to invention 27 or 28, further comprising a step of filling the cavity with a material having a dielectric constant lower than that of SiO ₂ .

  (30) The method for producing a field effect transistor according to invention 27 or 28, further comprising a step of filling the cavity with a porous material.

(31) A semiconductor layer protruding upward from the substrate plane, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer,
A source / drain region formed in a region not covered by the gate electrode of the semiconductor layer,
A field effect transistor having an end insulator region thicker than the gate insulating film on a side surface of the upper portion of the semiconductor layer and a gate electrode.

(32) A semiconductor layer protruding upward from the substrate plane, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer, and the semiconductor A source / drain region formed in a region of the layer not covered by the gate electrode,
The semiconductor layer includes a semiconductor layer upper region in which the width W of the semiconductor layer in the direction parallel to the substrate plane in a plane perpendicular to the channel length direction connecting the pair of source / drain regions is smaller than the width of the lower portion thereof, and the semiconductor layer A semiconductor layer lower region located below the upper region, wherein the width W of the semiconductor layer is larger than the width of the upper region of the semiconductor layer;
The semiconductor layer upper region has an end insulator whose side surface of the semiconductor layer recedes from the side surface of the semiconductor layer in the lower region of the semiconductor layer, and is thicker than the gate insulating film between the receded side surface and the gate electrode. A field effect transistor having a region.

  (33) The field effect transistor according to invention 32, wherein the upper width W of the semiconductor layer is constant.

  (34) The field effect transistor according to invention 32, wherein the width W of the upper portion of the semiconductor layer is continuously changed, and the thickness of the end insulator region is also changed accordingly.

  (35) The width W of the upper portion of the semiconductor layer gradually decreases with a certain gradient toward the upper end of the semiconductor layer, and accordingly, the thickness of the end insulator region increases toward the upper end of the semiconductor layer. The field effect transistor according to invention 32 which gradually increases.

  (36) The width W of the upper portion of the semiconductor layer gradually decreases so that the side surface of the semiconductor layer has a curvature toward the upper end of the semiconductor layer, and the thickness of the end insulator region is accordingly reduced. The field effect transistor according to invention 32, which gradually increases toward the upper end of the semiconductor layer.

  (37) The field effect transistor according to invention 31, wherein the width W of the semiconductor layer is constant from the lower end to the upper end of the semiconductor layer.

(38) A semiconductor layer protruding upward from a substrate plane, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer, and the semiconductor A source / drain region formed in a region of the layer not covered by the gate electrode,
The semiconductor layer includes a semiconductor layer upper region in which the width W of the semiconductor layer in the direction parallel to the substrate plane in a plane perpendicular to the channel length direction connecting the pair of source / drain regions is smaller than the width of the lower portion thereof, and the semiconductor layer A semiconductor layer lower region located below the upper region, wherein the width W of the semiconductor layer is larger than the width of the upper region of the semiconductor layer;
The upper region of the semiconductor layer has a transition region in which the width W of the semiconductor layer continuously changes in a portion connected to the lower region of the semiconductor layer, and the width W extends from the end of the transition region to the upper end of the semiconductor layer. Constant,
A field effect transistor having an end insulator region thicker than the gate insulating film between the semiconductor layer upper region and the gate electrode.

  (39) The field effect transistor according to any one of inventions 31 to 38, wherein a cap insulating layer thicker than the gate insulating film is provided on the semiconductor layer.

  (40) The field effect transistor according to invention 39, wherein the end insulator region is made of a material different from that of the cap insulating layer.

(41) said end insulator region is one of the field-effect transistor constituted invention 31-39 by SiO _2.

(42) The field effect transistor according to any one of inventions 31 to 39, wherein at least a part of the end insulator region is made of a material having a dielectric constant lower than that of SiO ₂ .

  (43) The field effect transistor according to any one of inventions 31 to 39, wherein at least a part of the end insulator region is made of a porous material.

  (44) The field effect transistor according to any one of inventions 31 to 39, wherein at least a part of the end insulator region is constituted by a cavity.

(45) A method for producing a field effect transistor according to invention 32, comprising:
Depositing a first insulating film on the semiconductor layer, and patterning the first insulating film and the upper portion of the semiconductor layer to a predetermined width;
Depositing and etching back the second insulating film to form an end insulator region made of the second insulating film on the side surface of the patterned first insulating film and the side surface of the semiconductor layer;
Etching the semiconductor layer using the end insulator region and the patterned first insulating film as a mask;
And a step of forming a gate insulating film on a side surface of the semiconductor layer exposed by the etching.

(46) depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
The method for manufacturing a field effect transistor according to invention 45, further comprising the step of forming a source / drain region by introducing an impurity into the semiconductor layer.

(47) A method for producing a field effect transistor according to invention 32, comprising:
Depositing a cap insulating layer on the semiconductor layer, and patterning the cap insulating layer and the upper portion of the semiconductor layer to a predetermined width;
Depositing and etching back a dummy layer, forming a corner dummy layer made of the dummy layer on the side surface of the patterned cap insulating layer and the side surface of the semiconductor layer;
Etching the semiconductor layer using the corner dummy layer and the patterned cap insulating layer as a mask;
Forming a gate insulating film on a side surface of the semiconductor layer exposed by the etching;
And a step of forming an end insulator region made of a cavity by removing the corner dummy layer.

(48) A method for producing a field effect transistor according to invention 32, comprising:
Depositing a cap insulating layer on the semiconductor layer, and patterning the cap insulating layer and the upper portion of the semiconductor layer to a predetermined width;
Depositing and etching back the first dummy layer to form a first corner dummy layer made of the first dummy layer on the side surface of the patterned cap insulating layer and the side surface of the semiconductor layer;
Depositing and etching back the second dummy layer to form a second corner dummy layer made of the second dummy layer on the side surface of the first corner dummy layer;
Etching the semiconductor layer using the first and second corner dummy layers and the patterned cap insulating layer as a mask;
Forming a gate insulating film on a side surface of the semiconductor layer exposed by the etching;
And removing the first corner dummy layer to form a cavity end insulator region.

(49) depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode;
A step of forming a source / drain region by introducing impurities into the semiconductor layer;
The method for manufacturing a field effect transistor according to invention 47 or 48, wherein an end insulator region comprising the cavity is formed after forming the gate electrode.

(50) After forming the cavity by removing the corner dummy layer, the cavity is filled with a low dielectric constant material having a dielectric constant lower than that of SiO ₂ to form an end insulator region made of the low dielectric constant material. A method for producing a field effect transistor according to invention 47 or 48, further comprising the step of:

(51) A method for producing a field effect transistor according to invention 35,
Forming a first insulating film on the semiconductor layer and patterning the first insulating film;
Etching the upper part of the semiconductor layer with the patterned first insulating film as a mask so that the width W of the semiconductor layer gradually decreases toward the upper end;
Depositing and etching back the second insulating film, and forming an end insulator region made of the second insulating film on the side surface of the patterned first insulating film and the tapered side surface of the semiconductor layer;
Etching the semiconductor layer using the end insulator region and the patterned first insulating film as a mask;
And a step of forming a gate insulating film on a side surface of the semiconductor layer exposed by the etching.

(52) The method further comprises a step of exposing the upper surface of the semiconductor layer by removing the patterned first insulating film and the second insulating film on the side surface portion thereof,
The method of manufacturing a field effect transistor according to invention 51, wherein in the step of forming the gate oxide film, a gate oxide film is formed on the exposed upper surface in addition to the side surface of the semiconductor layer.

(53) depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
52. The method of manufacturing a field effect transistor according to invention 51, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.

(54) A method for producing a field effect transistor according to invention 36,
Forming an oxidant-permeable cap insulating layer on the semiconductor layer;
Patterning the cap insulating layer and the semiconductor layer to form a semiconductor layer protruding from the plane of the substrate and a patterned cap insulating layer thereon;
At the interface between the semiconductor layer and the cap insulating layer, the semiconductor layer is oxidized in an oxidant atmosphere so that the side surface of the semiconductor layer recedes inward from the end of the cap insulating layer, and the semiconductor layer A method of manufacturing a field effect transistor, comprising: forming a semiconductor layer upper region whose upper width W gradually decreases toward the upper end of the semiconductor layer; and a step of forming an end insulating region whose thickness gradually increases accordingly .

(55) forming a gate insulating film on a side surface of the semiconductor layer;
Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
56. The method of manufacturing a field effect transistor according to invention 54, further comprising the step of forming a source / drain region by introducing impurities into the semiconductor layer.

(56) removing the cap insulating layer to expose an upper surface of the semiconductor layer;
Forming a gate insulating film on an upper surface and a side surface of the semiconductor layer;
Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
56. The method of manufacturing a field effect transistor according to invention 54, further comprising the step of forming a source / drain region by introducing impurities into the semiconductor layer.

(57) A semiconductor layer protruding upward from the substrate plane, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer, and the semiconductor A source / drain region formed in a region of the layer not covered by the gate electrode,
The upper side surface of the semiconductor layer has a first end insulator region thicker than the gate insulating film between the gate electrode and the gate electrode,
A field effect transistor having a second end insulator region thicker than the gate insulating film on a side surface of the lower portion of the semiconductor layer between the gate electrode and the gate electrode.

(58) a semiconductor layer protruding upward from the substrate plane, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer,
A source / drain region formed in a region not covered by the gate electrode of the semiconductor layer,
The semiconductor layer includes a semiconductor layer upper region in which the width W of the semiconductor layer in the direction parallel to the substrate plane in a plane perpendicular to the channel length direction connecting the pair of source / drain regions is smaller than the width of the lower portion thereof, and the semiconductor layer A semiconductor layer main portion region located below the upper region and having a width W of the semiconductor layer larger than the width of the semiconductor layer upper region, and located below the semiconductor layer main portion region, the width W of the semiconductor layer being A semiconductor layer lower region smaller than the width of the semiconductor layer main region,
The semiconductor layer upper region has a first end whose side surface of the semiconductor layer is recessed from the side surface of the semiconductor layer in the main region of the semiconductor layer, and is thicker than the gate insulating film between the retracted side surface and the gate electrode. A partial insulator region,
The semiconductor layer lower region has a second end whose side surface of the semiconductor layer recedes from the side surface of the semiconductor layer in the main region of the semiconductor layer, and is thicker than the gate insulating film between the receded side surface and the gate electrode. A field effect transistor having a partial insulator region.

  (59) The field effect transistor according to invention 57 or 58, wherein a cap insulating layer thicker than the gate insulating film is provided on the semiconductor layer.

(60) A method for producing a field effect transistor according to invention 58, comprising:
Preparing a substrate provided with a semiconductor layer on an oxidant-permeable first insulating film;
Forming an oxidant-permeable second insulating film on the semiconductor layer;
Patterning the second insulating film and the semiconductor layer to form a semiconductor layer protruding from the plane of the substrate and a patterned second insulating film thereon;
At the interface between the semiconductor layer and the second insulating film and at the interface between the semiconductor layer and the first insulating film, the semiconductor layer is oxidized in an oxidant atmosphere so that the side surface of the semiconductor layer recedes inward,
A semiconductor layer upper region in which the width W of the upper portion of the semiconductor layer gradually decreases toward the upper end of the semiconductor layer, and a first end insulating region in which the thickness gradually increases accordingly,
Field effect type having a step of forming a semiconductor layer lower region where the width W of the lower portion of the semiconductor layer is gradually reduced toward the lower end of the semiconductor layer, and a second end insulating region whose thickness is gradually increased accordingly. A method for manufacturing a transistor.

(61) removing the second insulating film to expose the upper surface of the semiconductor layer;
Forming a gate insulating film on an upper surface and a side surface of the semiconductor layer;
Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
The method of manufacturing a field effect transistor according to invention 60, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.

  (62) The field effect according to any one of inventions 1 to 6, 9 to 24, and 31 to 44, wherein the semiconductor substrate has a supporting substrate under the protruding semiconductor, and the semiconductor layer is integrally connected to the supporting substrate. Type transistor.

  (63) Inventions 1 to 6, 9 to 24, 31 to 44 having a supporting substrate under the protruding semiconductor, and the semiconductor layer being provided on the supporting substrate through a buried insulating film, The field effect transistor according to any one of 57 to 59.

  (64) The field effect transistor according to invention 1, wherein the overhanging portion has an overhanging width of 2 nm or more with respect to the surface of the gate insulating film.

  (65) The field effect transistor according to invention 1, wherein the overhanging portion has an overhanging width of 20 nm or less with respect to the surface of the gate insulating film.

  (66) The field effect transistor according to invention 1, 2, or 3, wherein the overhanging portion has an overhanging width with respect to the surface of the gate insulating film that is not more than 10 times the thickness of the gate insulating film.

(67) A semiconductor layer protruding upward from a substrate plane, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer, and the gate A source / drain region formed in a region not covered by the electrode,
The semiconductor layer is provided on the first insulating layer via a second insulating layer made of a material different from that of the first insulating layer,
The gate electrode is a field effect transistor having a portion on the first insulating layer directly in contact with the first insulating layer without passing through the second insulating layer.

  In the present invention, the gate electrode has a shape extending on opposite side surfaces from the upper part so as to straddle the semiconductor layer from the standpoint of ease of manufacture or formation of a tri-gate structure. Is preferred.

  In the present invention, the “base surface” means an arbitrary plane parallel (horizontal) to the substrate.

  According to the present invention, in a field effect transistor in which a channel is formed on the side surface of a semiconductor layer, an increase in potential at the upper corner of the semiconductor layer can be reduced and the influence of the parasitic transistor can be reduced.

  According to the present invention, even if the corner portion is not rounded, the potential increase at the corner portion can be suppressed and the parasitic transistor can be suppressed. Or according to this invention, the rounding amount of a corner part required in order to suppress the electrical potential rise of a corner part can be decreased.

  According to the present invention, it is possible to prevent the electric field from the drain region from entering the channel portion through the cap insulating layer or the buried insulating film and deteriorating the characteristics of the short channel transistor.

  According to the present invention, it is possible to provide a method for manufacturing a transistor capable of obtaining the above-described effects.

Sectional drawing explaining 1st embodiment Sectional drawing explaining 1st embodiment Sectional drawing and top view explaining 1st embodiment Sectional drawing and top view explaining 1st embodiment Sectional drawing and top view explaining 1st embodiment Sectional drawing explaining 1st embodiment Sectional drawing explaining 1st embodiment Plan view for explaining the first embodiment Explanatory drawing of structure and effect of the first embodiment Sectional drawing explaining 2nd embodiment Sectional drawing explaining 2nd embodiment Sectional drawing explaining 2nd embodiment Sectional drawing explaining 2nd embodiment Sectional drawing explaining 2nd embodiment Sectional drawing explaining 2nd embodiment Sectional drawing explaining 2nd embodiment Sectional drawing explaining 2nd embodiment Sectional drawing and top view explaining 2nd embodiment Sectional drawing and top view explaining 2nd embodiment Sectional drawing explaining 2nd embodiment Plan view for explaining the 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embodiment Sectional drawing explaining 3rd embodiment Sectional drawing explaining 3rd embodiment Sectional drawing explaining 3rd embodiment Sectional drawing explaining 3rd embodiment Sectional drawing explaining 3rd embodiment Sectional drawing and top view explaining 3rd embodiment Sectional drawing and top view explaining 3rd embodiment Sectional drawing and top view explaining 3rd embodiment Sectional drawing and top view explaining 3rd embodiment Sectional drawing explaining 3rd embodiment Sectional drawing explaining 3rd embodiment Explanatory drawing of the effect of the third embodiment Explanatory drawing of the effect of 2nd embodiment and 3rd embodiment Sectional drawing explaining 3rd embodiment Sectional drawing explaining 4th embodiment Sectional drawing explaining 4th embodiment Sectional drawing explaining 4th embodiment Sectional drawing explaining 4th embodiment Sectional drawing explaining 4th embodiment Sectional drawing and top view explaining 4th embodiment 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technology Sectional drawing explaining conventional technology Explanatory drawing of problems in conventional technology Sectional drawing explaining conventional technology Explanatory drawing of problems in conventional technology Sectional drawing explaining other embodiment of invention Sectional drawing explaining other embodiment of invention Sectional drawing explaining other embodiment of invention Sectional drawing explaining other embodiment of invention Sectional drawing explaining other embodiment of invention Cross-sectional view explaining problems of conventional technology Cross-sectional view explaining problems of conventional technology Sectional drawing explaining other embodiment of invention Sectional drawing explaining other embodiment of invention Sectional drawing explaining other embodiment of invention Sectional drawing explaining other embodiment of invention Sectional drawing explaining other embodiment of invention Sectional drawing explaining other embodiment of invention Explanatory drawing of the effect of the first embodiment

(First embodiment)
[Construction]
In a FinFET having a double gate structure in which a cap insulating layer 8 is provided on the semiconductor layer 3 protruding upward from the substrate, and the gate electrode 5 is formed so as to cover the semiconductor layer 3 and the cap insulating layer 8, the cap insulating layer 8 is horizontally disposed. Direction (a direction perpendicular to the channel length direction in a plane perpendicular to the direction in which the semiconductor layer 3 protrudes from the substrate. In the cross section of FIG. 1, the direction in which the cap insulating layer 8 and the semiconductor layer 3 are in contact with each other). And the cap insulating layer 8 has a protruding portion protruding from the surface of the gate insulating film 4. An example is shown in FIG. Symbol Wext indicates the width of the cap insulating layer 8 protruding in the horizontal direction from the surface of the gate insulating film 4, that is, the overhang width. Note that the “channel length direction” refers to a direction connecting a pair of source / drain regions.

  A gate electrode 5 is provided on a side surface of the semiconductor layer via a gate insulating film 4. The gate electrode 5 is patterned to an appropriate size, and a source / drain region 6 into which a first conductivity type impurity is introduced at a high concentration is formed in a semiconductor layer at a position not covered by the gate electrode. In the channel formation region 7, which is a semiconductor layer covered with the gate electrode 5, a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. A wiring is connected to the gate electrode 5 and the source / drain region 6 through a contact region.

  1A is a cross-sectional view taken along the line A-A ′ of FIG. 1B, and is a cross-sectional view at a position corresponding to the cross-section A-A ′ of FIG. 81 showing the conventional example. In the plan view of FIG. 1B, the source / drain region 6 is originally covered with the cap insulating layer 8 and the source / drain region 6 cannot be seen, but the source / drain region is shown for easy understanding of the structure. The position of the region 6 is shown in perspective.

  In this specification, the conductivity type of the source / drain region is referred to as the first conductivity type, and the conductivity type different from the source / drain region is referred to as the second conductivity type.

[Production method]
(First manufacturing method of the first embodiment)
An example of the manufacturing method will be described with reference to FIGS. 3A, FIG. 4A, FIG. 5A, and FIG. 7A are plan views, respectively, FIG. 3C, FIG. 4C, FIG. 5C, and FIG. 8 is a cross-sectional view taken along line AA ′ of FIG. 8, and FIG. 3B, FIG. 4B, FIG. 5B, and FIG. It is sectional drawing of the BB 'cross section in (c), FIG.5 (c), and FIG. FIGS. 6A and 6B are cross-sectional views showing the shape of the DD ′ cross section of FIG. 5C. Further, the position of the AA ′ cross section of each drawing explaining the present embodiment is the position of the AA ′ cross section of FIG. 81 showing the conventional example, and the position of the BB ′ cross section of each drawing explaining the present embodiment. The positions correspond to the positions of the BB ′ cross section of FIG. 81 showing the conventional example.

  In order to manufacture the field effect transistor according to the first embodiment, after forming the cap insulating layer 8 on the semiconductor layer 3 (FIG. 2), the semiconductor layer 3 and the cap insulating layer 8 are patterned into an appropriate shape. (FIG. 3) The side surface of the semiconductor layer 3 is etched so that the side surface of the semiconductor layer 3 recedes inward from the end of the cap insulating layer 8, and the semiconductor layer 3 is thinned (FIG. 4). Then, the gate insulating film 4 is formed on the side surface of the semiconductor layer, and after depositing the gate electrode material, the gate electrode material is patterned by RIE (reactive ion etching) or the like to form the gate electrode 5. A source / drain region 6 is formed by introducing a high-concentration first conductivity type impurity into a region not covered with the gate electrode 5 (FIG. 5). Thereafter, an interlayer insulating film 16 is deposited, and contacts 17 and wirings 18 are formed by a normal method (FIGS. 7 and 8). When the gate electrode is formed by processing by an etching process such as RIE, an excessive gate electrode material remaining under the projected cap insulating layer 8 is etched at least in the second half of the etching process. It is desirable to add a step of removing 26 (FIG. 6A).

  By employing such a manufacturing method, the element structure of the first embodiment can be formed.

(Second production method of the first embodiment)
An example of the manufacturing method will be described more specifically with reference to FIGS.

A cap insulating layer 8 is deposited on an SOI substrate in which a support substrate 1 made of silicon, a buried insulating layer 2 made of an insulator such as SiO ₂ , and a semiconductor layer 3 made of single crystal silicon are stacked thereon. . The cap insulating layer 8 is an SiO ₂ film deposited by, for example, a CVD method. Thereby, the form of FIG. 2 is obtained.

  Next, the cap insulating layer 8 and the semiconductor layer 3 are patterned and processed into an appropriate shape by a normal lithography process and a normal etching process such as RIE to form an element region. The shape obtained at this stage is shown in FIG. Both the cap insulating layer 8 and the semiconductor layer 3 may be patterned by etching using a photoresist as a mask, or only the cap insulating layer 8 is etched using the photoresist as a mask, and then the cap insulating layer 8 is formed. Patterning may be performed by etching the semiconductor layer 3 in a mask.

Next, by performing highly isotropic etching, the side surface of the semiconductor layer 3 is etched, and the side surface of the semiconductor layer 3 is processed into a shape that recedes from the side surface of the cap insulating layer 8. As a result, the shape of FIG. 4 is obtained. The highly isotropic etching is performed by performing RIE with a low bias voltage using, for example, an etching gas of Cl ₂ , HCl, CF _4, or HBr, or an etching gas in which these gases are mixed. . Alternatively, for example, an isotropic plasma etching apparatus using a gas such as CF ₄ is used.

  Next, after providing a gate insulating film 4 on the side surface of the semiconductor layer 3, polysilicon is deposited, and this is patterned by etching using a normal lithography process and an RIE process to form a gate electrode. By performing high-concentration ion implantation using the electrode as a mask and performing heat treatment, the source / drain region 6 is provided in the semiconductor layer 3 at a position not covered by the gate electrode, and the shape of FIG. 5 is obtained. When forming the gate electrode by etching the polysilicon to form the gate electrode, the polysilicon 26 is formed under the cap insulating layer 8 as shown in FIG. 6A in the DD ′ cross section of FIG. In order to prevent the residual silicon from remaining, if the isotropic etching is applied to the polysilicon after performing the normal RIE when etching the polysilicon, the cross section along the line DD ′ in FIG. As shown in FIG. 6B, a shape in which polysilicon does not remain under the cap insulating layer is obtained. The gate insulating film is provided, for example, by thermally oxidizing the semiconductor layer 3. The source / drain regions are formed by introducing impurities by an impurity introduction process such as vertical ion implantation, oblique ion implantation, or plasma doping.

Subsequently, an insulating film is deposited on the entire surface and etched back to provide a gate side wall 14. As the insulating film forming the gate side wall 14, for example, an insulating film such as a SiO ₂ single layer film, a Si ₃ N ₄ single layer film, or a multilayer film made of SiO ₂ and Si ₃ N ₄ is used. The insulating film forming the gate side wall 14 is formed by a film forming technique such as a CVD method. Subsequently, a metal is deposited on the source / drain region 6 and the gate electrode 5 and heat-treated, thereby forming a silicide layer 15 on the source / drain region 6 and the gate electrode 5. Subsequently, an interlayer insulating film 16 is deposited and planarized, and then a contact hole is formed in the upper part of the source / drain region 6 and the upper part of the gate electrode 5, and a contact 17 is formed by embedding a metal. The wiring 18 formed is connected to the contact 17 to obtain the shapes shown in FIGS. 7A shows the shape of the AA ′ cross section of FIG. 8, and FIG. 7B shows the shape of the BB ′ cross section of FIG. Note that the filling of the metal into the contact region and the deposition of the metal to be the wiring may be performed simultaneously. The contact 17 is located below the wiring 18, but the position is shown in a perspective manner in FIG. 8.

  By employing such a manufacturing method, the element structure of the first embodiment can be formed.

[effect]
FIG. 9B shows the result of simulating the potential distribution in the CC ′ cross section of FIG. In FIG. 9B, the vertical axis represents potential and the horizontal axis represents position, which indicates the depth from the upper end of the semiconductor layer. In this simulation, the impurity concentration in the semiconductor layer was set to 4 × 10 ¹⁸ cm ⁻³ . In addition, the potential reference is the source potential, and the potential of the source electrode is zero V. The left end of FIG. 9B corresponds to the surface of the semiconductor layer. The broken line shown as a double gate structure in the figure is the calculation result for the structure of FIG. 83, and the broken line shown as the trigate structure in the figure is the calculation result for the structure of FIG.

  For the structure of FIG. 1, the calculation results when Wext is 2 nm, 10 nm, and 30 nm are shown by solid lines. When Wext is 2 nm, 10 nm, or 30 nm, the increase in potential is moderated as compared with the normal double gate structure.

FIG. 100 shows a plot of simulation results with Wext on the horizontal axis and the maximum potential at the upper corner of the semiconductor layer on the vertical axis. The data in FIG. 100 (a) and FIG. 100 (b) are the same, FIG. 100 (a) shows the explanation about the lower limit of Wext, and FIG. 100 (b) shows the explanation about the upper limit of Wext. is there. However, in FIG. 100, the impurity concentration in the semiconductor layer is 4 × 10 ¹⁸ cm ⁻³ , the gate voltage is 0 V (in FIG. 100, the gate potential at this time is 0.56 V), and Wfin is 30 nm. The gate insulating film thickness is 2 nm.

  1 and 100, in the region where Wext is small, the potential at the upper corner portion decreases as Wext increases, and the effect of suppressing the potential increase is increased. However, as Wext increases, the potential does not change much even if Wext is increased.

  From FIG. 100, the half effect of the maximum effect is obtained when Wext is 2 nm or more, and the potential changes greatly in the range of Wext up to 5 nm, with a certain slope until Wext is up to 10 nm. The potential is changing. In the field-effect transistor of this embodiment, it is desirable that Wext be set to a size that can reduce the potential of the upper corner portion, so that a certain (specifically half) effect of the invention can be obtained. Wext is preferably 2 nm or more, Wext is preferably 5 nm or more for obtaining the effect of the invention, and 10 nm or more is preferred for obtaining the maximum effect.

  On the other hand, when Wext exceeds 10 nm, the change in potential becomes gradual, and when it exceeds 15 nm, the change in potential shows a saturation tendency. Even if Wext is increased in a region where the change in potential is saturated, the potential cannot be reduced only by increasing the burden on the manufacturing process. Therefore, it can be said that Wext is preferably 15 nm or less. Further, considering the variation of Wext due to a process cause, if a margin of 5 nm is seen with respect to 15 nm, Wext is preferably 20 nm or less.

  In view of the fact that if Wext is too large, it becomes difficult to process the gate electrode, Wext is preferably 20 nm or less, and more preferably 15 nm or less.

  In the calculation, since the thickness of the gate insulating film is set to 2 nm, Wext is preferably more than 1 times the thickness of the gate insulating film in order to obtain a certain effect of the invention. Wext is preferably 2.5 times or more of the gate insulating film thickness, and 5 times or more is preferable for obtaining the maximum effect. Similarly, Wext is preferably 10 times or less of the gate insulating film thickness, and Wext should be 7.5 times or less of the gate insulating film thickness if it is judged from the standpoint of pure effect while ignoring process variations. It is considered preferable.

(Second embodiment)
[Construction]
The second embodiment will be described with reference to FIGS. 10 to 16 and FIG. 26, which is a cross-sectional view at a position corresponding to the cross section AA ′ of FIG.

In the second embodiment, one of the upper and lower portions of the semiconductor layer 3 projecting upward from the substrate, or both the upper and lower portions of the semiconductor layer 3 projecting upward from the substrate are regions having a lower dielectric constant than SiO _2. A low dielectric constant region 10 is provided. A gate electrode 5 is provided on a side surface of the semiconductor layer via a gate insulating film 4. The gate electrode 5 is patterned to an appropriate size, and a source / drain region 6 into which a first conductivity type impurity is introduced at a high concentration is formed in a semiconductor layer at a position not covered by the gate electrode. In the channel formation region 7, which is a semiconductor layer covered with the gate electrode 5, a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. A wiring is connected to the gate electrode 5 and the source / drain region 6 through a contact region.

  The low dielectric constant region 10 provided on the upper portion of the semiconductor layer 3 and the low dielectric constant region 10 provided on the lower portion of the semiconductor layer 3 are parasitic transistors formed in the upper corner portion 34 and the lower corner portion 35 of the semiconductor layer, respectively. There is an action to suppress.

  Hereinafter, the structure of the second embodiment will be described in more detail with reference to FIGS. 10 to 16 and 26.

(Low dielectric constant region, cavity)
In a normal FinFET, the whole or a part of the cap insulating layer 8 formed on the semiconductor layer 3 is constituted by a low dielectric constant region 10 which is a region having a dielectric constant lower than that of SiO ₂ . (FIG. 10 (a)). Further, the low dielectric constant regions 10 are provided both above and below the semiconductor layer 3 (FIGS. 10B and 11A). Alternatively, a low dielectric constant region is provided only under the semiconductor layer 3 (FIGS. 11B and 11C, symbol 36 is a cap insulating layer made of SiO ₂ ). These low dielectric constant regions 10 are formed by cavities 12. The low dielectric constant material constituting the low dielectric constant region 10 has a relative dielectric constant lower than that of SiO ₂ . The relative dielectric constant of the low dielectric constant material is more preferably 3.0 or less.

  A part or all of the low dielectric constant region 10 is provided at a position lower than the upper end of the gate electrode (FIG. 94). In particular, when the gate electrode 5 straddles the semiconductor layer 3, the low dielectric constant region 10 is provided below the gate electrode (FIG. 10). With these forms, the electric field (a part of the electric field 46 shown in FIGS. 93 and 92B) from the side surface of the gate electrode extending above the semiconductor layer to the semiconductor layer, or the semiconductor layer from the lower surface of the gate electrode The effect of mitigating the influence of the electric field toward (part of the electric field 46 shown in FIG. 92B) and reducing the influence of the parasitic transistor can be obtained.

When a low dielectric constant region is provided below the semiconductor layer 3, a low dielectric constant region may also be provided below the gate electrode 5 in a region where the semiconductor layer 3 does not exist (FIG. 11). This structure has an advantage that the capacity between the lower portion of the gate electrode 5 and the support substrate can be reduced. Further, in a region where the semiconductor layer 3 does not exist, a structure in which a low dielectric constant region is not provided below the gate electrode 5 (FIG. 10B) may be used. This structure has an advantage that the element design is easy because the potential distribution inside the semiconductor layer 3 is vertically symmetrical. This structure also has the advantage that a low dielectric constant material, which is generally mechanically fragile compared to the SiO ₂ film, can reduce the area exposed to the surface during the manufacturing process.

Further, not only a region made of a material having a dielectric constant lower than that of SiO ₂ is provided on the semiconductor layer, but also a gate sidewall (for example, FIG. 20, FIG. 26, FIG. 28, FIG. A part or all of the portion (symbol 14 of 35) may be formed of a material having a dielectric constant lower than that of SiO ₂ .

(Protective insulation film)
A thin protective insulating film 13 formed by thermally oxidizing the semiconductor layer may be formed between the semiconductor layer 3 and the low dielectric constant region 10. The protective insulating film 13 has an effect of reducing defects such as interface states at the interface between the low dielectric region and the semiconductor layer. Protective insulating film 13 is equal to or SiO _2, or may have a higher dielectric constant than SiO _2. The protective insulating film 13 may have a dielectric constant lower than that of SiO ₂ . The thickness of the protective insulating film is not particularly limited, but the thickness of the protective insulating film is the thickness of the low dielectric constant region (however, the thickness means the width in the direction perpendicular to the substrate plane. For example, in the cross section of FIG. Is the width in the vertical direction.) If it is thinner, it is desirable for the effect of suppressing parasitic transistors. Further, if the thickness of the protective insulating film is three times or less than that of the gate insulating film, it is more desirable for the effect of suppressing the parasitic transistor. FIG. 13 shows a structure in which a protective insulating film 13 is interposed between the semiconductor layer 3 and the low dielectric constant region 10 when the low dielectric constant region 10 is a cavity 12. FIG. 13A shows the case where the low dielectric constant region is provided on the upper portion of the semiconductor layer, and FIG. 13B shows the case where the low dielectric constant region is provided on the upper and lower portions of the semiconductor layer. Further, the protective insulating film 13 may be formed on the surface of the gate electrode in contact with the cavity (FIG. 26).

Further, a protective insulating film 13 may be provided between the semiconductor layer 3 and the low dielectric constant region below the semiconductor layer. The protective insulating film 13 provided under the semiconductor layer is shown as a buried protective insulating film 39 in FIG. The purpose of providing the buried protective insulating film 39 is the same as the purpose of providing the protective insulating film 13 provided on the semiconductor, and is to reduce defects such as interface states at the interface between the low dielectric constant region and the semiconductor layer. Further, the buried protective insulating film 39 is equal to or SiO _2, or may have a higher dielectric constant than SiO _2, may have a lower dielectric constant than SiO ₂ points to also as the protective insulating film 13 provided on the semiconductor layer upper It is the same.

(Combination of the first embodiment and the second embodiment)
The second embodiment may be implemented in combination with the first embodiment.

  For example, in the first embodiment, all or part of the cap insulating layer 8 on the semiconductor layer may be constituted by the low dielectric constant region 10 which is a region made of a low dielectric constant material or a cavity. This has an effect of further suppressing the parasitic transistor in the upper corner portion of the semiconductor layer by further adding the effect of the second embodiment to the effect of the first embodiment.

  In the first embodiment, part or all of the insulator below the semiconductor layer may be constituted by a low dielectric constant region made of a low dielectric constant material or a cavity. That is, the various configurations of the first embodiment may be applied to the upper portion of the semiconductor layer, and the second embodiment may be applied to the lower portion of the semiconductor layer. This suppresses the parasitic transistor in the upper corner portion of the semiconductor layer according to the first embodiment and the parasitic transistor in the lower corner portion 35 of the semiconductor layer according to the second embodiment.

  Examples thereof are shown in FIGS. 15 and 16. These are all sectional views in the same cross section as FIG. 15A shows a case where the cap insulating layer is formed of the low dielectric constant region 10 in the structure of FIG. 1, and FIG. 15B shows a low dielectric constant region 10 of the structure shown in FIG. In this case, the protective insulating film 13 is used. The protective insulating film 13 is provided to protect the interface between the semiconductor layer 3 and the cavity 12. 16A shows a low dielectric constant region 10 provided in the lower part of the semiconductor layer 3 in the structure of FIG. 1, and FIG. 16B shows a low dielectric constant formed of a cavity 12 in the lower part of the semiconductor layer 3 in the structure of FIG. This is a case where the rate region 10 is provided and the protective insulating film 13 is provided at the interface between the cavity 12 and the semiconductor layer 3 and at the interface between the cavity 12 and the gate electrode 5.

  In addition, you may combine 1st embodiment and 2nd embodiment in the form different from what was shown in FIG. 15, FIG.

[Production method]
(First manufacturing method of the second embodiment)
A manufacturing method in the case where the low dielectric constant region 10 is provided on the semiconductor layer 3 will be described with reference to FIGS. FIGS. 18 (a), 19 (a), and 20 (a) are cross-sectional views taken along the line AA ′ in FIG. 21, which is a plan view. FIGS. 18 (b) and 19 (b). FIG. 20B is a cross-sectional view taken along the line BB ′ in FIG. 21, which is a plan view.

An example of the manufacturing method will be described. In order to manufacture the field effect transistor of the second embodiment, the low dielectric constant film 30 made of a material having a dielectric constant lower than that of SiO _{2 serving} as the low dielectric constant region 10 as the cap insulating layer 8 on the semiconductor layer 3. Is deposited (FIG. 17), and the semiconductor layer 3 and the low dielectric constant film 10 are patterned into appropriate shapes (FIG. 18). After forming the gate insulating film 4 on the semiconductor side surface and depositing the gate electrode material, the gate electrode material is patterned by RIE or the like to form the gate electrode 5, which is covered with the gate electrode 5 in the semiconductor layer 3. A source / drain region 6 is formed by introducing a high-concentration first-conductivity-type impurity into the non-existing region (FIG. 19). Thereafter, an interlayer insulating film is deposited, and contacts 17 and wirings 18 are formed by a normal method (FIGS. 20 and 21).

  By employing such a manufacturing method, the element structure of the second embodiment can be formed.

(Second production method of the second embodiment)
A manufacturing method in the case where the low dielectric constant region 10 is provided above the semiconductor layer 3 will be described in more detail with reference to FIGS.

On the SOI substrate in which the supporting substrate 1 made of silicon, the buried insulating layer 2 made of SiO ₂ thereon, and the semiconductor layer 3 made of single crystal silicon thereon are laminated, the low dielectric constant region 10 is made of SiO ₂ . A low dielectric constant insulating film 30 made of a material having a low dielectric constant is deposited.
The low dielectric constant insulating film 30 is a SiOF film deposited by, for example, a CVD method. Thereby, the form of FIG. 17 is obtained.

  Next, the low dielectric constant film 30 and the semiconductor layer 3 are patterned by a normal lithography process and a normal etching process such as RIE to obtain the shape of FIG. The low dielectric constant film 30 and the semiconductor layer 3 may both be patterned by etching using a photoresist as a mask, or only the low dielectric constant film 30 may be etched using the photoresist as a mask, followed by low dielectric constant. Patterning may be performed by etching the semiconductor layer 3 using the film 30 as a mask.

  Next, after providing a gate insulating film 4 on the side surface of the semiconductor layer 3, polysilicon is deposited, and this is patterned by etching using a normal lithography process and an RIE process to form a gate electrode. By performing high-concentration ion implantation using the electrode as a mask and performing heat treatment, the source / drain region 6 is provided in the semiconductor layer 3 at a position not covered by the gate electrode, and the shape of FIG. 19 is obtained.

Subsequently, an insulating film is deposited on the entire surface and etched back to provide a gate side wall 14. The insulating film forming the gate side wall 14 is made of, for example, a SiO ₂ or Si ₃ N ₄ multilayer film, or a multilayer film made of SiO ₂ and Si ₃ N ₄ . The insulating film forming the gate side wall 14 is formed by a film forming technique such as a CVD method. Subsequently, a metal is deposited on the source / drain region 6 and the gate electrode 5 and heat-treated, thereby forming a silicide layer 15 on the source / drain region 6 and the gate electrode 5. Subsequently, an interlayer insulating film 16 is deposited and planarized, and then a contact hole is formed in the upper part of the source / drain region 6 and the upper part of the gate electrode 5, and a contact 17 is formed by embedding a metal. The wiring 18 formed is connected to the contact 17 to obtain the shapes shown in FIGS. Note that the filling of the metal into the contact region and the deposition of the metal to be the wiring may be performed simultaneously. The contact 17 is located below the wiring 18, but the position is shown in FIG. 21. The low dielectric constant film 30 forms the low dielectric constant region 10.

  By employing such a manufacturing method, the element structure of the second embodiment can be formed.

(Third production method of the second embodiment)
In the case where the low dielectric constant region 10 is provided below the semiconductor layer 3, the following changes are made in the first manufacturing method of the second embodiment or the second manufacturing method of the second embodiment. All or part of the buried insulating layer is formed by the low dielectric constant film 30. The cap insulating layer 8 may be a low dielectric constant film or may not be a low dielectric constant film. Further, without forming the cap insulating layer 8, a gate insulating film is formed on the side surface and the upper surface of the semiconductor, a gate electrode material is deposited, and then the gate electrode material is patterned by RIE or the like to obtain a tri-layer as shown in FIG. A gate structure may be formed. Further, when patterning the semiconductor layer 3 and the low dielectric constant film 10 into an appropriate shape, by etching a part or all of the low dielectric constant film below the semiconductor layer 3 in a region not covered by the semiconductor layer 3, A shape as shown in FIG. 10B may be formed. FIG. 10B uses an SOI substrate in which the upper region of the buried insulating film is formed of a low dielectric constant film, and the low dielectric constant film below the semiconductor layer 3 is etched in a region not covered by the semiconductor layer 3. This is the shape obtained.

  By employing such a manufacturing method, the element structure of the second embodiment can be formed.

(Fourth manufacturing method of the second embodiment)
A manufacturing method in which a low dielectric constant region 10 including a cavity 12 is provided on the semiconductor layer 3 and a low dielectric constant material having a dielectric constant lower than that of SiO ₂ after the cavity 12 is once provided on the semiconductor layer 3. A manufacturing method for providing the low dielectric constant region 10 on the upper portion of the semiconductor layer 3 by backfilling with reference to FIG. 14 and FIG. 22 to FIG. 28 will be described.

  23 (a), FIG. 24 (a), FIG. 25 (a), FIG. 26 (a), and FIG. 28 (a) are plan views, respectively, FIG. 23 (c), FIG. 24 (c), and FIG. It is sectional drawing of the AA 'cross section in FIG.25 (c) and FIG. 27, FIG.23 (b), FIG.24 (b), FIG.25 (b), FIG.26 (b), FIG.28 (b) is respectively It is sectional drawing of the BB 'cross section in FIG.23 (c) which is a top view, FIG.24 (c), FIG.25 (c), and FIG.

  A dummy layer 11 is deposited on the semiconductor layer 3 (FIG. 22), the semiconductor layer 3 and the dummy layer 11 are patterned into an appropriate shape (FIG. 23), a gate insulating film is formed on the semiconductor side surface, and a gate electrode material is deposited. After that, the gate electrode material is patterned by RIE or the like to form the gate electrode 5 so as to cover the semiconductor layer 3, the gate insulating film 4, and the dummy layer 11, and the gate electrode 5 in the semiconductor layer 3 is covered. A source / drain region 6 is formed by introducing a high-concentration first-conductivity-type impurity into the non-existing region (FIGS. 24 and 14A). Subsequently, the dummy layer 11 is removed by etching to form a cavity 12 in a region on the semiconductor layer 3 covered with the gate electrode 5 (FIGS. 25 and 14B). Thereafter, an interlayer insulating film is deposited, and contacts and wirings are formed by a normal method (FIGS. 26 and 27).

  Alternatively, the low dielectric constant region 10 may be formed by refilling the cavity 12 on the semiconductor layer 3 covered with the gate electrode 5 with a low dielectric constant material.

For example, a Si ₃ N ₄ film deposited by CVD is used for the dummy layer 11, and in order to form a cavity, the Si ₃ N ₄ film of the dummy layer 11 is removed by an etching process such as wet etching using phosphoric acid. .

  By employing such a manufacturing method, the element structure of the second embodiment can be formed.

(Fifth manufacturing method of the second embodiment)
A manufacturing method in which a low dielectric constant region 10 including a cavity 12 is provided above the semiconductor layer 3, and a low dielectric constant material is backfilled in the cavity 12 provided above the semiconductor layer 3, and the low dielectric constant region is provided above the semiconductor layer 3. The manufacturing method for providing the reference numeral 10 will be described in more detail with reference to FIGS.

A dummy layer 11 is deposited on an SOI substrate in which a support substrate 1 made of silicon, a buried insulating layer 2 made of SiO ₂ thereon, and a semiconductor layer 3 made of single crystal silicon are stacked thereon. The dummy layer 11 is, for example, a Si ₃ N ₄ film deposited by the CVD method. Thereby, the form of FIG. 22 is obtained. Note that a pad insulating film made of an insulating film different from the dummy layer 11, for example, a pad insulating film made of a SiO ₂ film formed by thermal oxidation, may be formed between the dummy layer 11 and the semiconductor layer 3.

  Next, the dummy layer 11 and the semiconductor layer 3 are patterned by a normal lithography process and a normal etching process such as RIE to obtain the shape of FIG. Both the dummy layer 11 and the semiconductor layer 3 may be patterned by etching using a photoresist as a mask, or only the dummy layer 11 is etched using the photoresist as a mask, and then the semiconductor is formed using the dummy layer 11 as a mask. The semiconductor layer 3 may be patterned by etching the layer 3. When a pad insulating film is provided between the dummy layer 11 and the semiconductor layer 3, the pad insulating film is also patterned at the same time.

  Next, after providing the gate insulating film 4 on the side surface of the semiconductor layer 3, polysilicon is deposited, and this is patterned by a normal lithography process and an RIE process to form a gate electrode. Subsequently, high concentration ion implantation is performed using the gate electrode as a mask, and heat treatment is performed, thereby providing the source / drain region 6 in the semiconductor layer 3 at a position not covered by the gate electrode, thereby obtaining the shape of FIG. The gate insulating film is provided, for example, by thermally oxidizing the semiconductor layer 3. The source / drain regions are formed by introducing impurities by an impurity introduction process such as vertical ion implantation, oblique ion implantation, and plasma doping.

Subsequently, the dummy layer 11 is replaced with the cavity 12 by selectively removing the dummy layer 11 by etching. At this time, the dummy layer 11 below the gate electrode is removed by the intrusion of the etching solution or the etching gas in the lateral direction as indicated by an arrow in FIG. When the dummy layer 11 is a Si ₃ N ₄ film, phosphoric acid may be used as an etching solution. Further, for the purpose of protecting the surface of the semiconductor layer 3 and the gate electrode 5 adjacent to the cavity 12 or preventing the generation of interface states at the interface adjacent to the cavity, the interface adjacent to the cavity 12 of the semiconductor layer 3. Alternatively, a protective insulating film may be provided at the interface adjacent to the cavity 12 of the gate electrode 5. FIG. 25 shows a structure in which the protective insulating film 13 is provided by thermally oxidizing the interface adjacent to the cavity 12 of the semiconductor layer 3 or the interface adjacent to the cavity 12 of the gate electrode 5. Note that in FIG. 25C, the protective insulating film 13 is omitted (the entire structure is covered with the protective insulating film 13, and thus the structure is unclear when the protective insulating film 13 is drawn).

Subsequently, an insulating film is deposited on the entire surface and etched back to provide a gate side wall 14. The insulating film forming the gate side wall 14 is made of, for example, a SiO ₂ or Si ₃ N ₄ multilayer film, or a multilayer film made of SiO ₂ and Si ₃ N ₄ . The insulating film forming the gate side wall 14 is formed by a film forming technique such as a CVD method. Subsequently, a metal is deposited on the source / drain region 6 and the gate electrode 5 and heat-treated, thereby forming a silicide layer 15 on the source / drain region 6 and the gate electrode 5. Subsequently, an interlayer insulating film 16 is deposited and planarized, and then a contact hole is formed in the upper part of the source / drain region 6 and the upper part of the gate electrode 5, and a contact 17 is formed by embedding a metal. The wiring 18 formed is connected to the contact 17 to obtain the shapes shown in FIGS. However, FIG. 26A shows the shape of the AA ′ cross section of FIG. 27, and FIG. 26B shows the shape of the BB ′ cross section of FIG. Note that the filling of the metal into the contact region and the deposition of the metal to be the wiring may be performed simultaneously. The contact 17 is located below the wiring 18, but the position is shown in FIG. 27.

  In this manufacturing method, the cavity may be backfilled with a low dielectric constant material. Here, the low dielectric constant material filled in the cavity may be a continuous film such as SiOF, or may be a porous material. After removing the dummy layer 11 to form a cavity, or after forming a cavity and a protective insulating film in the cavity, a low dielectric constant material is embedded in the cavity by CVD or spin coating. When etched back, the low dielectric constant material remains only in the portion covered by the gate electrode. This structure is shown in FIG.

  In addition, after finishing a high-temperature heat treatment process such as a heat treatment for activating impurities implanted into the source / drain regions, a process for filling the cavity with a low dielectric constant material is performed, or after these high-temperature heat treatment processes are finished. Thereafter, the formation of the cavity and the process of filling the cavity with the low dielectric constant material can prevent the high temperature heat treatment from causing a chemical or physical change to the low dielectric constant material.

  By employing such a manufacturing method, the element structure of the second embodiment can be formed.

(Sixth manufacturing method of the second embodiment)
A manufacturing method in which a low dielectric constant region 10 including a cavity 12 is provided below the semiconductor layer 3, and a low dielectric constant material is buried in the cavity 12 provided below the semiconductor layer 3, so that a low dielectric constant is provided below the semiconductor layer 3. A manufacturing method for providing the region 10 will be described with reference to FIGS.

  30 (a), 31 (a), and 34 are cross-sectional views taken along the line AA ′ of FIGS. 30 (c), 31 (c), and 36, respectively, which are plan views, and FIG. 30 (b). 31 (b) and FIG. 35 are cross-sectional views taken along the line BB ′ of FIGS. 30 (c), 31 (c), and 36, which are plan views, respectively. 32 (a) and 33 (a) are cross-sectional views of the cross-sectional view of FIG. 30 (a) in a state where the process has proceeded, and FIGS. 32 (b), 33 (b), and 37 are illustrated in FIG. It is sectional drawing in the state which the process advanced in the cross section of ().

  A substrate in which a dummy layer 11 is provided also on the buried insulating layer and the dummy layer 11 (20) is provided below the semiconductor layer 3 is prepared (FIG. 29). Then, when the semiconductor layer 3 is patterned into an appropriate shape, the dummy layer below the semiconductor layer is also etched simultaneously (FIGS. 30 and 31). Thereafter, a gate electrode material is formed, and the gate electrode material film is patterned by RIE or the like to form the gate electrode 5, and a high concentration first layer is formed in a region of the semiconductor layer 3 that is not covered with the gate electrode 5. Source / drain regions 6 are formed by introducing conductive impurities (FIG. 32). Subsequently, the dummy layer 11 is removed by etching to form a cavity 12 in a region below the semiconductor layer 3 (FIG. 33). Thereafter, an interlayer insulating film is deposited, and contacts and wiring are formed by a normal method (FIGS. 34, 35, and 36).

  If a dummy layer is provided below the semiconductor layer and the dummy layer below the semiconductor layer is removed, a structure having a cavity below the semiconductor can be obtained. Further, by providing dummy layers above and below the semiconductor layer 3 and removing the dummy layers above and below the semiconductor layer, a structure having cavities above and below the semiconductor can be obtained.

Note that in order to prevent the semiconductor layer from being peeled off from the substrate when the cavity is provided in the lower portion of the semiconductor layer, the side surface of the dummy layer is provided in a region such as the source / drain region where it is not necessary to provide the cavity in the lower portion of the semiconductor layer. Is preferably covered with a material that is not etched in the dummy layer removing step (for example, SiO ₂ when phosphoric acid is used to remove the dummy layer).

Alternatively, the low dielectric constant region 10 may be formed below the semiconductor layer 3 by filling the dummy layer provided below the semiconductor layer 3 with a low dielectric constant material having a dielectric constant lower than that of SiO ₂ .

  By employing such a manufacturing method, the element structure of the second embodiment can be formed.

(Seventh manufacturing method of the second embodiment)
An example of a manufacturing method for forming the low dielectric constant region 10 including the cavity 12 above and below the semiconductor layer 3 will be described more specifically with reference to FIGS.

  When a cavity or a low dielectric constant region is provided below the semiconductor layer, dummy layers 11 are provided above and below the semiconductor layer 3 as shown in FIG. 29 in the manufacturing method described with reference to FIGS. As shown in FIG. 30, the support insulating film 21 is provided on the side surface of the patterned semiconductor layer 3, and as shown in FIG. 31, the semiconductor layer 3 once covered with the support insulating film 21 is exposed in the channel formation region. A change that the second etching is performed on the layer 3 may be added.

  30 (a), 31 (a), and 34 are cross-sectional views taken along the line AA ′ of FIGS. 30 (c), 31 (c), and 36, respectively, which are plan views, and FIG. 30 (b). FIGS. 31 (b) and 34 (b) are cross-sectional views taken along the line BB ′ in FIGS. 30 (c), 31 (c), and 36, respectively. 32 (a) and 33 (a) are cross-sectional views of the cross-sectional view of FIG. 30 (a) in a state where the process has proceeded, and FIGS. 32 (b), 33 (b), and 37 are illustrated in FIG. It is sectional drawing in the state which the process advanced in the cross section of ().

An upper dummy layer is formed on an SOI substrate in which a support substrate 1 made of silicon, a buried insulating layer 2 made of SiO ₂ thereon, a lower dummy layer 20 thereon, and a semiconductor layer 3 made of single crystal silicon thereon are laminated. 19 is deposited. The upper dummy layer 19 and the lower dummy layer 20 are, for example, Si ₃ N ₄ films. Thereby, the form of FIG. 29 is obtained. When simply referring to the dummy layer 11, it refers to both the upper dummy layer 19 and the lower dummy layer 20.

  Next, the upper dummy layer 19, the semiconductor layer 3, and the lower dummy layer 20 are patterned by a normal lithography process and a normal etching process such as RIE. Next, a support insulating film 21 is deposited on the entire surface and etched back to obtain the shape shown in FIG. Next, a laminated structure of the upper dummy layer 19, the semiconductor layer 3, and the lower dummy layer 20 is formed around the region where the channel is formed so that the side surface of the semiconductor layer 3 is exposed in the region where the channel is formed. The portion adjacent to 21 is removed by etching. The shape obtained by this process is shown in FIG.

  Thereafter, the same steps as those described with reference to FIGS. 24 to 27 are performed to complete the transistor. 32 corresponds to FIG. 24, FIG. 33 corresponds to FIG. 25, and FIGS. 34, 35, and 36 correspond to FIGS. 26 (a), 26 (b), and 27, respectively. The shape formed by performing the process of forming a shape is shown.

  The characteristics in each process will be described. After forming a gate insulating film on the side surface of the semiconductor layer 3, a gate electrode material is deposited, the gate electrode material is processed to form a gate electrode, and impurities are introduced into the source / drain regions 6. In the introducing step, the upper dummy layer 19 is formed above the semiconductor layer, and the lower dummy layer 20 is formed below (FIG. 32). Further, the cavity 12 is formed above and below the semiconductor layer by removing the dummy layer to form the cavity 12. When the protective insulating film 13 is provided in the cavity, the protective insulating film 13 is formed above and below the semiconductor layer (FIGS. 33, 34, 35, and 37). 34, 35, 36, and 37 show a state in which the formation of the silicide layer, the interlayer insulating film, the contact, and the wiring is finished. In addition, the cavity may be formed over the entire semiconductor layer in the lower part of the semiconductor layer 3 (FIGS. 33 and 35), and a cavity is formed in the lower part of the semiconductor layer 3 only in a part of the area under the gate electrode. (FIG. 37). As a manufacturing method, the entire lower dummy layer may be removed, or the lower dummy layer may be removed only in a part of the region located below the gate electrode.

  The purpose of providing the support insulating film 21 is to support the semiconductor layer in a state where the lower dummy layer 20 below the semiconductor layer is removed and a cavity is formed. Therefore, when a cavity is formed in the lower part of the semiconductor layer 3 only in a partial region under the gate electrode (FIG. 37), or the semiconductor layer is supported by the connection at the contact surface between the gate electrode 5 and the buried insulating film 2. If sufficient mechanical strength is obtained, the support insulating film 21 may be omitted.

  By employing such a manufacturing method, the element structure of the second embodiment can be formed.

[effect]
In the present embodiment, a material having a dielectric constant lower than that of SiO _{2 in} a portion located above the semiconductor layer, a portion located below the semiconductor layer, or a portion located above and below the semiconductor layer. It is replaced by a low dielectric constant region, which is a region made up of. Since the low dielectric constant region has an action of relaxing the electric field between the gate electrode and the semiconductor layer, if a part of the portion located above the semiconductor layer is replaced by the low dielectric constant region, the upper corner portion 34 of the semiconductor layer (FIG. 82, FIG. 82). The potential increase in FIG. 83) is suppressed, the generation of parasitic transistors is suppressed, and the characteristics of the transistors are improved. Parasitic transistors also occur in the lower corner portion 35 (FIGS. 82 and 83). However, if a part of the lower portion of the semiconductor layer is replaced by a low dielectric constant region, the potential rise in the lower corner portion of the semiconductor layer is increased. The generation of parasitic transistors is suppressed, and the characteristics of the transistors are improved.

  As a more specific example, FIG. 39 shows the potential distribution when the upper portion of the FinFET semiconductor layer is a cavity.

  Compared to FIGS. 84 (a) and 84 (b), the curve of the equipotential lines at the corner is remarkably reduced, and the potential increase at the corner is suppressed. This indicates that the parasitic transistor at the corner is suppressed.

  FIG. 54 shows a plot of the potential distribution on the side surface of the semiconductor layer as in FIG. 9B. 54 (a) is the double gate structure of FIG. 83, FIG. 54 (b) is the trigate structure of FIG. 82, and FIG. 54 (c) is the structure of FIG. 10 (a). Is provided. The number in the figure is the amount of increase in potential at the upper end of the semiconductor layer, and is 63.4 mV in the structure of FIG. This value is small compared to the case of the normal double gate structure (186 mV) and the case of the normal trigate structure (358 mV), and the parasitic transistor suppressing effect according to the present embodiment is remarkable.

  Since the occurrence of parasitic transistors in the FinFET is more significant in the upper corner of the semiconductor layer than in the lower corner, a low dielectric constant region is provided in the upper portion of the semiconductor layer (FIGS. 10A and 10B). ), FIG. 11 (a), FIG. 12, and FIG. 13) are particularly desirable. In addition, since parasitic transistors are also generated at the lower corner, it is more desirable to provide a low dielectric constant region at both the upper and lower portions of the semiconductor layer (FIGS. 10B, 11A, and 13B). ).

  Further, when the cap insulating layer is formed of a low dielectric constant region or a part of the cap insulating layer is formed of a low dielectric constant material, an effect of suppressing an electric field from the drain to the channel through the cap insulating layer can be obtained. . Further, when the buried insulating film is replaced with a low dielectric constant region or a part of the buried insulating film is replaced with a low dielectric constant material, an effect of suppressing an electric field from the drain to the channel through the buried insulating film can be obtained.

  The electric field from the drain to the channel through the cap insulating layer or buried insulating film causes various characteristics deterioration in short channel transistors, including threshold voltage fluctuations called DIBL (Drain Induced Barrier Lowering, Drain Induced Barrier Lowering) Therefore, the present embodiment also has an effect of improving the characteristics of the short channel transistor, for example, suppressing threshold fluctuation due to DIBL.

In addition to forming the cap insulating layer 8 with a material having a dielectric constant lower than that of SiO ₂ , if the gate sidewall 14 is also formed of a material having a dielectric constant lower than that of SiO ₂ , the threshold fluctuation due to DIBL can be suppressed. The action of improving the characteristics of the short channel transistor can be further strengthened.

  When a cavity is provided below the FinFET, the following effects can be obtained as an effect of improving the performance of the transistor provided on the cavity, in addition to the effect of suppressing the parasitic transistor in the FinFET. In a conventional planar field effect transistor, a structure that aims to reduce parasitic capacitance and suppress a short channel effect by providing a cavity under a semiconductor layer has been proposed, but in the structure of the present invention, The gate electrode adjacent to the vertical channel reaches the buried insulating layer below the cavity. This has the advantage that heat generated in the channel region can easily escape to the support substrate side via the gate electrode. In addition, since the channel is on the semiconductor side surface, even when the channel width is large, the distance between the non-cavity region and the region where the gate electrode is in contact can be reduced, and the density of the non-cavity region and the region where the gate electrode is in contact can be increased. It becomes easy for the heat generated in the channel region to be released to the substrate side via the gate electrode. FIG. 38A shows the case of the planar type conventional structure, and FIGS. 38B and 38C show the case of the structure of the present invention. FIG. 38C shows a case where a plurality of semiconductor layers are arranged as shown in FIG. 38B is a cross-sectional view at a position corresponding to the cross section AA ′ in FIG. 36, FIG. 38B is a cross-sectional view at a position corresponding to the cross section AA ′ in FIG. (A) is a cross section in the channel width direction of the channel region covered with the gate electrode of the planar transistor. Note that an arrow (symbol 33) in FIG. 38 represents a heat flow, and a symbol 32 represents a field insulating film.

(Characteristics common to the third embodiment, the fourth embodiment, and the fifth embodiment)
[Construction]
Features common to the third embodiment, the fourth embodiment, and the fifth embodiment are shown in FIGS. 41, 55, 56, 57, 59, 60, 66, 67, 68, and 68. Reference is made to FIG. 41, 55, 56, 57, 59, 60, 66, 67, 68, and 69 are cross-sections at positions corresponding to the AA 'cross-section of FIG. 81 for explaining the conventional structure. It is a figure and is sectional drawing in the cross section corresponded in the cross section which shows Fig.82 (a) and FIG.83 (a) explaining a conventional structure.

  The semiconductor layer 3 of the FinFET of the third embodiment, the fourth embodiment and the fifth embodiment has a form protruding from the substrate surface, and a gate electrode is formed on both sides of the semiconductor layer 3 via the gate insulating film 4. Is provided.

  The semiconductor layer includes a semiconductor layer main region 43 and a semiconductor layer end region 44 provided in at least one of an upper part or a lower part of the semiconductor layer main region 43.

  The semiconductor layer main part region 43 is a region in which the width Wfin of the semiconductor layer in the plane perpendicular to the direction connecting the two source / drain regions is larger than the semiconductor layer end region 44.

  The semiconductor layer end region 44 is a region in which the width Wfin of the semiconductor layer in a plane perpendicular to the direction connecting the two source / drain regions is smaller than the width of the semiconductor layer main region 43 or two source / drain regions. The width Wfin of the semiconductor layer in a plane perpendicular to the connecting direction is smaller than the width of the semiconductor layer main part region 43 as the distance from the semiconductor layer main part region 43 is changed, and from one or both of the two regions This is a region in which an end insulator region 27 is provided between the semiconductor layer 3 and the gate electrode 5.

  The end insulator 27 is an insulator provided between the semiconductor layer 3 and the gate electrode 5 and having a maximum width Wei larger than the thickness of the gate insulating film 4.

  The gate electrode 5 is patterned to an appropriate size, and a source / drain region 6 into which a first conductivity type impurity is introduced at a high concentration is formed in a semiconductor layer at a position not covered by the gate electrode. In the channel formation region 7, which is a semiconductor layer covered with the gate electrode 5, a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. A wiring is connected to the gate electrode 5 and the source / drain region 6 through a contact region.

  The third embodiment, the fourth embodiment, and the fifth embodiment may be applied to a transistor having a double gate structure in which the upper interface of the semiconductor layer 3 hardly contributes as a channel (FIG. 41). The present invention may be applied to a transistor having a tri-gate structure (FIG. 42A) in which a channel is formed at the upper interface of the layer 3. 42A, when the symbols of the semiconductor layer end region 44 and the semiconductor layer main portion region 43 are omitted in the drawing, the side surface of the semiconductor layer 3 becomes the end insulator region 27. The contacted portion is the semiconductor layer end region 44, and the side surface of the semiconductor layer 3 is not in contact with the end insulator region 27, and the portion in contact with the gate insulating film is the semiconductor layer main portion region 43.

The end insulator region 27 may be a normal insulator such as SiO ₂ , a low dielectric constant material, or a cavity. FIG. 42B shows a case where a cavity is provided as the end insulator region 27. It is more preferable to use a material having a dielectric constant lower than that of SiO ₂ or a cavity for all or part of the end insulator region because the effect of relaxing the electric field concentration is increased.

  Further, the end insulator region 27 and the cap insulating layer may be made of the same material or different materials. Further, when the end insulator region 27 and the cap insulating layer are made of the same material, they may be integrally formed. An example in which the end insulator region 27 and the cap insulating layer are integrally formed is shown in FIG.

  Further, when the end insulator region 27 is made of a material different from that of the cap insulator 8 on the semiconductor layer 3 or is not formed integrally with the same material, the end insulator region 27 is formed on the semiconductor layer 3. A structure that penetrates into a partial region of the cap insulator 8 may be used. Further, when the end insulator region 27 is made of a material different from that of the gate insulating film 4 on the semiconductor layer 3 or is not formed integrally with the same material, the end insulator region 27 is formed on the semiconductor layer 3. A structure that penetrates into a partial region of the gate insulator 4 may also be used. FIG. 43A shows a structure in which the end insulator region 27 enters a part of the cap insulator 8 on the semiconductor layer 3.

  In the tri-gate transistor, the gate insulating film 4 may be formed so as to cover the semiconductor layer 3 and the end insulator region 27. This is a structure obtained, for example, when the gate insulating film is formed by a film deposition technique such as a CVD method after the end insulator region is formed. An example is shown in FIG.

  42 (a), 42 (b) and 42 (c), FIG. 43 (a) and FIG. 43 (b) are at positions corresponding to the AA ′ cross section of FIG. 81 for explaining the conventional structure. It is sectional drawing, and is sectional drawing in the cross section corresponded in the cross section which shows FIG. 82 (a) and FIG. 83 (a) explaining a conventional structure.

  The semiconductor layer main part region 43 has a region whose width changes, particularly in a part of the semiconductor layer main part region 43 such as an upper end or a lower end, due to processing accuracy (etching accuracy). Also good. In the semiconductor region 29, the width Wfin of the semiconductor layer may change within a certain limit (for example, within plus or minus 20%, more preferably within 10%) due to factors such as processing accuracy.

  In addition, as described in each drawing, the interface between the end insulator 27 and the gate electrode 5 and the interface between the gate insulating film 4 and the gate electrode 5 are in the same plane (same linear shape in the sectional view). Most preferable in processing the gate electrode.

  However, the effect of the present invention can be obtained even if the interface between the end insulator 27 and the gate electrode 5 is not in the same plane as the interface between the gate insulating film 4 and the gate electrode 5.

[effect]
In the third embodiment, the fourth embodiment, and the fifth embodiment, an end insulator which is an insulator thicker than the gate insulating film between the semiconductor layer and the gate electrode in the semiconductor layer end region. Since the region 27 is provided, a corner portion of the semiconductor layer is formed by the end insulator region 27 (when the end insulator region 27 is provided above the semiconductor layer, the upper corner portion and the end insulator region 27 are formed in the semiconductor layer. In the case of being provided at the lower part of the transistor, the potential rise in the lower corner part) is suppressed and the parasitic transistor is suppressed, so that the first problem is solved and the characteristics of the transistor are improved.

  Further, in the corner portion, a surface orientation greatly different from either the surface orientation of the upper surface of the semiconductor layer and the surface orientation of the side surface of the semiconductor layer is not formed, or even if formed, the surface is covered with an end insulator, so that the semiconductor A new parasitic transistor having a plane orientation that is significantly different from both the plane orientation of the upper surface of the layer and the plane orientation of the side surface of the semiconductor layer is not formed, and the second problem does not occur, so that the transistor characteristics are good. can get.

  Note that the effect of suppressing the parasitic transistor at the corner portion of the semiconductor layer 3 by the end insulator region 27 is that the electric field due to the thick insulating film is more effective when applied to a double gate structure having the cap insulating layer 8 on the semiconductor layer 3. Since the relaxation effect is greater, it is greater than when applied to a tri-gate structure. However, the tri-gate structure is superior to the double gate structure in that the drain current is large because a channel is also formed on the upper portion of the semiconductor layer.

(Third embodiment)
[Construction]
The field effect transistor according to the third embodiment includes a part of the semiconductor layer end region 44 (preferably a semiconductor layer) in addition to the features common to the third embodiment, the fourth embodiment, and the fifth embodiment. 50% or more of the height of the end region 44), or the width Wtop of the semiconductor layer is substantially constant in the entire semiconductor layer end region 44 (preferably the variation amount of the semiconductor width is plus or minus 20% or less, more preferably the semiconductor The variation amount of the width is plus or minus 10% or less).

  A semiconductor layer end region 44 is provided above the semiconductor layer main region 43, the semiconductor layer main region 43 forms the semiconductor layer lower region 29, and the semiconductor layer end region 44 forms the semiconductor layer upper region 28. As an example, the structure of the field effect transistor according to the third embodiment is shown in FIGS. 40A is a sectional view taken along the line AA ′ in FIG. 40C, and FIG. 40B is a sectional view taken along the line BB ′ in FIG. 40C. 41 and 41 are cross-sectional views enlarging and drawing FIG.

  The semiconductor layer of the FinFET according to the third embodiment includes a semiconductor layer upper region 28 which is a region where the width of the semiconductor layer is small in a plane perpendicular to the direction connecting the two source / drain regions, and a lower portion of the semiconductor layer upper region 28. The semiconductor layer lower region 29 is a region where the width of the semiconductor layer is large in a plane perpendicular to the direction connecting the two source / drain regions, and in the semiconductor layer upper region 28, the side surface of the semiconductor layer is lower than the semiconductor layer. The region 29 has a shape that is recessed from the side surface of the semiconductor layer. In FIG. 41, symbol Wtop is the width of the semiconductor layer upper region 28 in the plane perpendicular to the direction connecting the two source / drain regions, and symbol Wfin is the semiconductor layer in the plane perpendicular to the direction connecting the two source / drain regions. The width of the lower region 29 is shown.

  An end insulator region 27 is provided between the semiconductor layer upper region 28 and the gate electrode 5. A gate insulating film 4 is provided between the semiconductor layer upper region 29 and the gate electrode 5. The width Wei of the end insulator region 27 is larger than the thickness of the gate insulating film.

  The gate electrode 5 is patterned to an appropriate size, and a source / drain region 6 into which a first conductivity type impurity is introduced at a high concentration is formed in a semiconductor layer at a position not covered by the gate electrode. In the channel formation region 7, which is a semiconductor layer covered with the gate electrode 5, a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. A wiring is connected to the gate electrode 5 and the source / drain region 6 through a contact region.

  In order to solve the second problem, it is most desirable that the connection portion between the semiconductor layer upper region 28 and the semiconductor layer lower region 29 be as steep as possible. That is, it is most desirable that the widths of the semiconductor layer upper region 28 and the semiconductor layer lower region 29 change discontinuously at the connection portion therebetween.

  Note that the semiconductor layer upper region 28 and the semiconductor lower region 29 may include regions having different widths from Wtop and Wfin in some of the regions, depending on factors such as processing accuracy. For example, there may be a region where the width of the semiconductor layer changes at the upper end or lower end of the semiconductor layer upper region 28 and at the upper end or lower end of the semiconductor lower region 29.

  A transition region 40 may be provided in a region in contact with the semiconductor layer lower region 29 in the semiconductor layer upper region 28. An example of this is shown in FIG. The minimum transition area gradient 41 in the transition area 40 is preferably 45 degrees or less, and particularly preferably 25 degrees or less. 55 shows a cross-sectional view in the same cross section as FIG. The minimum gradient 41 of the transition region refers to an angle formed by the semiconductor layer interface in the transition region 40 and the substrate surface at a position where the angle formed by the semiconductor layer interface in the transition region 40 and the substrate surface is minimized.

  In addition, in the semiconductor layer upper region 28, in the region where the width of the semiconductor layer is constant, or in the semiconductor lower region 29, the width of the semiconductor layer is within a certain limit due to factors such as processing accuracy (for example, within plus or minus 20% of Wtop) , Wfin may be within ± 20%, more preferably within Wtop plus / minus 10%, and Wfin within ± 10%.

  Further, FIG. 42A shows a form in which the third embodiment is applied to a tri-gate transistor. FIG. 42B shows a case where a cavity is provided as the end insulator region 27 in the third embodiment. An example in which the end insulator region 27 and the cap insulating layer are integrally formed is shown in FIG. FIG. 43A shows a structure in which the end insulator region 27 enters a part of the cap insulator 8 on the semiconductor layer 3. An example of a structure obtained when the gate insulating film is formed by a film deposition technique such as a CVD method is shown in FIG. 42 (a), FIG. 42 (b), FIG. 42 (c), FIG. 43 (a) and FIG. 43 (b) are positions corresponding to the AA ′ cross section of FIG. 81 for explaining the conventional structure. It is sectional drawing in FIG. 82, It is sectional drawing in the cross section corresponded to the cross section which shows FIG. 82 (a) and FIG. 83 (a) explaining a conventional structure.

  In addition, the case where the thickness of the end insulator 27 in the position where the width of the semiconductor layer is constant in the semiconductor layer upper region 28 is mainly described, but the thickness of the end insulator 27 is If the maximum value is thicker than the gate insulating film, it may not be constant. However, in order to increase the effect of the invention, in the region where the thickness of the end insulator 27 is constant, the thickness of the end insulator 27 is not less than 5 nm and not less than three times the gate insulating film thickness. Preferably, the end insulator 27 has a thickness of 5 nm or more and more preferably 5 times or more the gate insulating film thickness.

  In this specification, the thickness of the gate insulating film 4 or the thickness of the end insulator 27 refers to the thickness in the vertical direction from the interface between the gate electrode 5 and each insulating film, which is the origin of the electric field. Therefore, in FIG. 80 (a), which is an enlarged view of the upper right corner portion of the semiconductor layer 3 in FIG. 85, it indicates the thickness t1, not the thickness t2, and is an enlarged view of the upper right corner portion of FIG. 80 (b) indicates the thickness t3, not the thickness t4.

  Therefore, if the interface between the gate electrode 5 and the end insulator region 27 is vertical as shown in FIGS. 66 and 80B, the term width Wei of the end insulator region 27 and the end insulator region 27 The term thickness is synonymous.

[Production method]
(First manufacturing method of the third embodiment)
An example of the manufacturing method in 3rd embodiment is demonstrated with reference to FIG. FIG. 44 shows the shape at a position corresponding to the AA ′ cross section of FIG. 81 for explaining the conventional example step by step.

A cap insulating layer 8 (an insulating film layer such as SiO ₂ ) is deposited on the semiconductor layer 3, and the upper portions of the cap insulating layer 8 and the semiconductor layer 3 are processed to a desired width by a normal lithography and RIE process (FIG. 44 (FIG. 44)). a)). Next, an insulator film such as a SiO ₂ film is deposited and etched back to form an end insulator region 27 on the side surface of the cap insulating layer and the side surface of the semiconductor layer 3 (FIG. 44B). Subsequently, the semiconductor layer 3 is etched using the cap insulating layer 8 and the end insulator region 27 as a mask (FIG. 44C). After the gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this process, and subsequently the gate electrode material is deposited, the gate electrode material is processed by a normal lithography and RIE process to form the gate electrode 5.

  Subsequently, a source / drain region 6 is formed by introducing a high-concentration first conductivity type impurity into a region of the semiconductor layer 3 that is not covered with the gate electrode 5. Thereafter, an interlayer insulating film is deposited, and contacts 17 and wirings 18 are formed by a normal method.

At this time, a cap insulating layer 8 (an insulating film layer such as SiO ₂ ) is deposited on the semiconductor layer 3, and the upper portions of the cap insulating layer 8 and the semiconductor layer 3 are processed to a desired width by a normal lithography and RIE process. In the step of FIG. 44A, when the top surface of the exposed semiconductor layer is not horizontal, a form having a cross section as shown in FIG. 55 is formed, but the effect of the invention can be obtained. There is no substitute.

  By employing such a manufacturing method, the element structure of the third embodiment can be formed.

(Second production method of the third embodiment)
An example of a manufacturing method in the case where the end insulator region 27 is made hollow and a manufacturing method in which the cavity of the end insulator region 27 is backfilled with an insulator will be described with reference to FIG. FIG. 45 shows the shape at a position corresponding to the AA ′ cross section of FIG.

A cap insulating layer 8 (an insulating film layer such as SiO ₂ ) is deposited on the semiconductor layer 3, and the upper portions of the cap insulating layer 8 and the semiconductor layer 3 are processed to a desired width by a normal lithography and RIE process (FIG. 45 ( a)). Next, a corner dummy layer material such as a Si ₃ N ₄ film is deposited and etched back to provide a corner dummy layer 22 composed of Si ₃ N ₄ sidewalls 37 on the side surfaces of the cap insulating layer and the semiconductor layer 3. Subsequently, the second sidewall material such as SiO ₂ film is deposited and etched back to form the SiO ₂ sidewall 38 on the side surface of the corner dummy layer 22 (FIG. 45B). Subsequently, the semiconductor layer 3 is etched using the cap insulating layer, the corner dummy layer made of the Si ₃ N ₄ side wall 37, and the _second side wall made of the SiO ₂ side wall 38 as a mask (FIG. 45C). After the gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this process, and subsequently the gate electrode material is deposited, the gate electrode material is processed by a normal lithography and RIE process to form the gate electrode 5. Subsequently, if the corner dummy layer 22 made of the Si ₃ N ₄ side wall 37 is removed, the end insulator region 27 made of the cavity 12 is formed in the region where the semiconductor layer has receded from the gate electrode. Next, a source / drain region 6 is formed by introducing a high-concentration first conductivity type impurity into a region of the semiconductor layer 3 that is not covered with the gate electrode 5. Thereafter, an interlayer insulating film is deposited, and contacts 17 and wirings 18 are formed by a normal method.

The second sidewall is formed by depositing and etching back SiO ₂ following the deposition and etching back of Si ₃ N ₄ to form the second sidewall by the sacrificial oxide film removing process and the cleaning process for the semiconductor layer. by being removed, enters the inside from the side surface of the semiconductor layer is Si ₃ N ₄ sidewall, it is to prevent the overhang shape the upper the Si ₃ N ₄ sidewall and projecting horizontally is formed, SiO ₂ If a second side wall made of a film is provided, the second side wall also recedes at the same time in the step of removing the sacrificial oxide film, so that it does not have an overhang shape. Note that in the case where an overhang shape is allowed by adding isotropic etching to the step of forming the gate electrode, the step of forming the second sidewall may be omitted.

  Alternatively, the cavity may be backfilled with a low dielectric constant material to form the end insulator region 27 made of the low dielectric constant material. Here, the low dielectric constant material filled in the cavity may be a continuous film such as SiOF, or may be a porous material.

  In addition, after finishing a high-temperature heat treatment process such as a heat treatment for activating impurities implanted into the source / drain regions, a process for filling the cavity with a low dielectric constant material is performed, or after these high-temperature heat treatment processes are finished. Thereafter, the formation of the cavity and the process of filling the cavity with the low dielectric constant material can prevent the high temperature heat treatment from causing a chemical or physical change to the low dielectric constant material.

  By employing such a manufacturing method, the element structure of the third embodiment can be formed.

(Third manufacturing method of the third embodiment)
An example of the manufacturing method of the third embodiment will be described more specifically with reference to FIGS. 46 to 52. 47 (a), FIG. 48 (a), FIG. 49 (a), and FIG. 50 (a) are plan views. FIG. 47 (c), FIG. 48 (c), FIG. 49 (c), and FIG. 47A, 47B, 48B, 49B, and 50B are plan views, and FIGS. 47C and 48C. , FIG. 49 (c), and FIG. 50 (c) are cross-sectional views taken along the line BB ′. 51 (a) and 52 are cross-sectional views in the same cross section as FIG. 20 (a), and FIG. 51 (b) is a cross-sectional view in the same cross section as FIG. 20 (b).

A cap insulating layer 8 is deposited on an SOI substrate in which a support substrate 1 made of silicon, a buried insulating layer 2 made of SiO ₂ thereon, and a semiconductor layer 3 made of single crystal silicon are further laminated thereon. A cross section in this state is shown in FIG.

  Next, the upper part of the cap insulating layer 8 and the semiconductor layer 3 is patterned by a normal lithography process and a normal etching process such as RIE to obtain the shape of FIG. Both the cap insulating layer 8 and the semiconductor layer 3 may be patterned by etching using a photoresist as a mask, or only the cap insulating layer 8 is etched using the photoresist as a mask, and then the cap insulating layer 8 is formed. Patterning may be performed by etching the semiconductor layer 3 in a mask. Here, the cap insulating layer 8 is patterned so that the width thereof is substantially the same as the width Wtop of the semiconductor layer upper region 28 (see FIG. 41) and is narrower than the width Wfin of the semiconductor layer lower region 29. The depth at which the semiconductor layer 3 is etched is substantially equal to the height Htop of the semiconductor layer upper region 28. This state is shown in FIG.

Next, a corner dummy layer 22 is provided on the side surface of the cap insulating layer and the exposed side surface of the semiconductor layer by depositing a material to be the corner dummy layer and etching it back. The material of the corner dummy layer 22 is, for example, Si ₃ N ₄ . The form obtained by this process is shown in FIG.

  Subsequently, the semiconductor layer 3 is patterned by an etching process such as RIE using the cap insulating layer 8 and the corner dummy layer 22 as a mask to form an element region. The form obtained by this step is shown in FIG. Next, a gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this process, and after depositing a gate electrode material, the gate electrode material is processed by a normal lithography and RIE process to form the gate electrode 5. This state is shown in FIG.

  Subsequently, a source / drain region 6 is formed by introducing a high-concentration first conductivity type impurity into a region of the semiconductor layer 3 that is not covered with the gate electrode 5.

  Subsequently, the corner dummy layer 22 is removed by etching to provide a cavity 24 that becomes the end insulator region 23.

  Subsequently, by depositing and etching back an insulating film, a gate side wall 14 is provided on the side surface of the gate electrode, an interlayer insulating film is then deposited, and a contact 17 and a wiring 18 are formed by a normal method. This state is shown in FIG.

In addition, after forming the shape of FIG. 47, instead of depositing a material to be a corner dummy layer and etching it back, depositing a material to be the end insulator region 23 and etching it back, a cap is obtained. The end insulator region 23 may be provided on the side surface of the insulating layer and the side surface exposed by etching of the semiconductor layer. The material of the end insulator region 23 is, for example, SiO ₂ . Alternatively, the material of the end insulator region 23 is a low dielectric constant material such as SiOF. In this case, the semiconductor layer 3 is subsequently patterned by an etching process such as RIE using the cap insulating layer 8 and the end insulator region 23 as a mask to form an element region. Thereafter, the gate electrode, the source / drain region, the wiring, and the contact are formed by performing the same process as the case where the corner dummy layer 22 is provided except that the corner dummy layer 22 is removed by etching. The shape obtained in this case is shown in FIG. FIG. 52 is a cross-sectional view in the same cross section as FIG. 51A, and an end SiO ₂ region 25 is formed instead of the cavity 24 in FIG.

  By employing such a manufacturing method, the element structure of the third embodiment can be formed.

[effect]
In this embodiment, a part of the semiconductor layer upper region located at the end is replaced by the end insulator region 27. Since the end insulator region 27 has an action of relaxing the electric field between the gate electrode and the semiconductor layer, an increase in potential at the upper corner portion of the semiconductor layer is suppressed, generation of a parasitic transistor is suppressed, and characteristics of the transistor are improved. .

  As a more specific example, FIG. 53 shows a potential distribution in the structure of FIG. 42B in which a cavity is formed in a region where the semiconductor layer is recessed from the gate electrode. Note that the upper end of the semiconductor layer serving as a channel is a portion adjacent to the lower end of the cavity. Compared to FIGS. 84 (a) and 84 (b), the curve of the equipotential lines at the corner portion at the bottom of the cavity is remarkably reduced, and the potential increase at the corner portion is suppressed. This indicates that the parasitic transistor at the corner is suppressed.

  FIG. 54 (d) shows a plot of the potential distribution on the side surface of the semiconductor layer as in FIG. 9 (b). The left end of the figure is the upper end of the semiconductor layer at the bottom of the cavity. The potential rise is reduced to 30.8 mV, and this embodiment suppresses the potential rise at the corner portion, and the effect of suppressing the parasitic transistor at the corner portion is remarkable.

  Note that it is preferable that the surface of the end insulator region and the surface of the gate insulating film 4 (the interface on the gate electrode side is referred to as the surface) are aligned because the gate electrode can be easily processed.

  However, even if one of them protrudes to the gate electrode side from the other due to process reasons, the potential rise at the upper corner of the semiconductor layer is suppressed and the effect of suppressing the parasitic transistor can be obtained. For example, in the structure of FIG. 49A, the side surface of the semiconductor layer 3 recedes from the gate electrode side with respect to the corner dummy layer 22 by the sacrificial oxidation process and the wet etching process for the sacrificial oxide film, resulting in the structure of FIG. In this case, the surface of the gate insulating film 4 recedes as compared with the surface of the end insulator region 23.

  Further, even if the side surface of the semiconductor layer upper region 28 does not recede from the side surface of the semiconductor layer lower region 29 and the end insulator region 27 thicker than the gate insulating film 4 protrudes toward the gate electrode side. In addition, it is possible to obtain an effect of suppressing a potential increase in the upper corner portion of the semiconductor layer and suppressing a parasitic transistor. An example of the structure is shown in FIG. 44, for example, in the step of FIG. 44, after forming the structure of FIG. 44 (c), as in the step of FIG. 4 (a) of the first embodiment, the cap insulating layer 8 and This is obtained when the semiconductor layer 3 is selectively thinned with respect to the end insulator region 27. FIG. 90 and FIG. 91 show the forms in the process in the order of the processes. These are drawn with respect to the same cross section as FIG. 44, and FIG. 90 (a), FIG. 90 (b), FIG. 90 (c) and FIG. 91 (b) are respectively shown in FIG. It corresponds to the process of b), FIG.44 (c), and FIG.44 (d).

(Fourth embodiment)
[Construction]
In the field effect transistor according to the fourth embodiment, in addition to the features common to the third embodiment, the fourth embodiment, and the fifth embodiment, the width of the semiconductor layer 3 is in the semiconductor layer end region 44. It has the feature of not having a certain area. The semiconductor layer end region 44 of the field effect transistor according to the fourth embodiment has a form in which the width of the semiconductor layer becomes narrower as the distance from the connection portion with the semiconductor layer main region 43 increases. In addition, the end insulator region 27 provided between the semiconductor layer end region 44 and the gate electrode 5 becomes thicker as the distance from the connection portion between the semiconductor layer end region 44 and the semiconductor layer main region 43 is increased. The maximum value of the film thickness of the end insulator region 27 is thicker than the gate insulating film thickness.

  An example in which the semiconductor layer end region 44 is provided above the semiconductor layer main portion region 43, the semiconductor layer main portion region 43 forms the semiconductor layer lower region 29, and the semiconductor layer end region 44 forms the semiconductor layer upper region. FIG. 56, FIG. 57, FIG. 59, and FIG. 60 show the structure of the field effect transistor according to the fourth embodiment. 56, 57, 59, and 60 are cross-sectional views at positions corresponding to the AA ′ cross section of FIG. 81 for explaining the conventional structure, and FIGS. 82 (a) and 83 for explaining the conventional structure. It is sectional drawing in the cross section corresponded to the cross section which (a) shows. The symbol Wtop is the minimum width of the semiconductor layer end region, the symbol Wei is the maximum width of the end insulator region, and the symbol Wfin is the width of the semiconductor layer main region.

  56 and 57, when the width of the semiconductor upper region 28 located under the cap insulating layer 8 is reduced toward the upper part with a certain gradient, the forms of FIGS. 59 and 60 are different from those in the cap insulating layer 8. This is a case where the semiconductor upper region 28 located in the lower part of the semiconductor layer is reduced with curvature toward the upper part. 56 and 59 show the case where the fourth embodiment is applied to a double gate transistor having a cap insulating layer 8, and FIGS. 57 and 60 show the gate at the upper interface of the semiconductor layer without the cap insulating layer 8. This is a case where the fourth embodiment is applied to a tri-gate transistor having an insulating film 4. 56, 57, 59, or 60, the end insulator region 27 is provided between the semiconductor upper region 28 and the gate electrode 5, and the position of at least a part of the end insulator region 27 is provided. , The width Wei of the end insulator region 27 is thicker than that of the gate insulating film 4.

(First manufacturing method of the fourth embodiment)
As an example of the manufacturing method according to the fourth embodiment, a method of manufacturing the embodiment of FIG. 56 will be described with reference to FIG. FIG. 58 shows the shape at a position corresponding to the AA ′ cross section of FIG.

A cap insulating layer 8 (an insulating film layer such as SiO ₂ ) is deposited on the semiconductor layer 3, the cap insulating layer 8 is processed by a normal lithography and RIE process, and the upper portion of the semiconductor layer 3 is tapered. (FIG. 58A). Next, an insulator film such as a SiO ₂ film is deposited and etched back to form end insulator regions 27 on the side surfaces of the cap insulating layer and the semiconductor layer 3 (FIG. 58B). Subsequently, the semiconductor layer is etched using the cap insulating layer 8 and the end insulator region 27 as a mask (FIG. 58C). After the gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this process, and subsequently the gate electrode material is deposited, the gate electrode material is processed by a normal lithography and RIE process to form the gate electrode 5.

In order to etch the upper portion of the semiconductor layer 3 so as to have a taper, for example, a taper etching technique of mixing a gas containing carbon at the time of performing RIE is used. For example, by mixing CH ₄ with Cl ₂ , a carbon compound is gradually deposited during etching, and a taper shape is formed by utilizing the fact that etching does not proceed at the position where the carbon compound is deposited.

  Subsequently, a source / drain region 6 is formed by introducing a high-concentration first conductivity type impurity into a region of the semiconductor layer 3 that is not covered with the gate electrode 5. Thereafter, an interlayer insulating film is deposited, and contacts 17 and wirings 18 are formed by a normal method.

If the cap insulating layer 8 is removed by an etching process such as RIE after the step of forming the shape of FIG. 58C is completed, the gate insulating film 4 is formed, and the subsequent steps are performed as shown in FIG. Such a trigate structure is obtained. FIG. 57 shows the case where the upper portion of the end insulating film is simultaneously etched when the cap insulating layer 8 is removed by RIE. When the cap insulating layer 8 is removed by an etching process such as RIE, if the thickness of the buried insulating layer 2 is larger than that of the cap insulating layer 8, the etching of the buried insulating layer proceeds simultaneously with the etching of the cap insulating layer. However, even if the cap insulating layer is removed, a part of the embedded insulating film remains and the support substrate is not exposed, which is preferable. In addition, if a material that is resistant to etching of the cap insulating layer, for example, Si ₃ N _4, is used for the entire buried insulating layer, the surface, or a layer at a certain depth, for example, Si ₃ N ₄ , This is preferable because a form in which part of the substrate remains and the support substrate is not exposed is obtained.

  In addition, the trigate structure as shown in FIG. 57 can be obtained by using the process of not depositing the cap insulating layer 8 in the process of FIG. In this case, the semiconductor layer 3 is tapered and etched using a resist as a mask, and after forming a shape without the cap insulating layer 8 in FIG. 58A, the same manufacturing method as that for manufacturing a transistor with a double gate structure is used. Just do it.

(Second manufacturing method of the fourth embodiment)
An example of the manufacturing method will be described with reference to FIGS. 61 (a), 62 (a), 63 (a), and 64 (a) are plan views, respectively, FIG. 61 (c), FIG. 62 (c), FIG. 63 (c), and FIG. FIG. 61B is a cross-sectional view taken along the line AA ′ in FIG. 65, and FIGS. 61B, 62B, 63B, and 64B are plan views, respectively. FIG. 66C is a cross-sectional view taken along the line BB ′ in FIG. Further, the position of the AA ′ cross section of each drawing explaining the present embodiment is the position of the AA ′ cross section of FIG. 81 showing the conventional example, and the position of the BB ′ cross section of each drawing explaining the present embodiment. The positions correspond to the positions of the BB ′ cross section of FIG. 81 showing the conventional example.

In order to manufacture the field effect transistor according to the fourth embodiment, a cap insulating layer 8 made of, for example, SiO ₂ is formed on the semiconductor layer 3 on the buried insulating layer 2 (the configuration at this time is shown in FIG. 2). The semiconductor layer 3 and the cap insulating layer 8 are patterned into appropriate shapes (the configuration at this point is the same as in FIG. 3). Subsequently, at the interface between the semiconductor layer 3 and the cap insulating layer, and at the interface between the semiconductor layer 3 and the buried insulating layer 2, the side surface of the semiconductor layer 3 recedes inward from the position of the end of the cap insulating layer 8. The semiconductor layer 3 is thermally oxidized. At this time, the oxide film formed thick at the upper and lower corners of the semiconductor layer becomes the end insulator region 27 (FIG. 61). This form is formed because the oxidant such as oxygen gas diffuses to the upper and lower surfaces of the semiconductor layer via the cap insulating layer 8 and the buried insulating film, and the oxidant is on both sides of the semiconductor layer. This is due to the fact that the upper and lower corners of the semiconductor layer are oxidized into a rounded shape because they diffuse more near the surface. At this time, a sacrificial oxide film layer 44 is formed on the side surface of the semiconductor layer 3. Next, the sacrificial oxide film layer 44 is removed from the side surface of the semiconductor layer 3 by an etching process such as wet etching to obtain the configuration shown in FIG. Subsequently, a gate insulating film 4 is provided on the side surface of the semiconductor layer (FIG. 63), and after depositing a gate electrode material, the gate electrode material is processed by ordinary lithography and RIE processes to form the gate electrode 5. Subsequently, a source / drain region is formed by introducing a high-concentration first conductivity type impurity into a region of the semiconductor layer 3 that is not covered with the gate electrode 5. Thereafter, an interlayer insulating film is deposited, and contacts and wirings are formed by a normal method (FIGS. 64 and 65).

61, after the step of forming the shape of FIG. 61 is completed, the cap insulating layer 8 is removed by an etching process such as RIE at a certain stage before the gate insulating film is formed, and the subsequent process is performed. For example, a trigate structure as shown in FIG. 60 is obtained. When the cap insulating layer 8 is removed by an etching process such as RIE, if the thickness of the buried insulating layer 2 is larger than that of the cap insulating layer 8, the etching of the buried insulating layer proceeds simultaneously with the etching of the cap insulating layer. Even if the cap insulating layer is removed, a portion of the embedded insulating film remains and the support substrate is not exposed, which is preferable. Further, if a material that is resistant to etching of the cap insulating layer, for example, Si ₃ N _4, is used for the entire buried insulating layer, the surface, or a layer at a certain depth, for example, Si ₃ N ₄ , even if the cap insulating layer is removed, the buried insulating film This is preferable because a form in which part of the substrate remains and the support substrate is not exposed is obtained.

  When forming a tri-gate structure, even if round oxidation is performed in the absence of a cap insulating layer, the structure shown in FIG. 85 of the conventional example is obtained, and it is thicker than the gate insulating film. Since the end insulator region 27 is not formed, the effect of the invention cannot be obtained. Moreover, when the structure shown in FIG. 85 of the conventional example is simply combined with the normal double gate transistor structure, the structure shown in FIG. 70 is obtained, and a structure having the end insulator region 27 thicker than the gate insulating film is obtained. Therefore, the effect of the present invention cannot be obtained.

In this manufacturing method, when the buried insulating layer easily diffuses the oxidizing agent, specifically, when the buried insulating layer is SiO ₂ , the end insulator region 27 is also formed below the semiconductor layer. The When the buried insulating layer hardly diffuses the oxidizing agent, specifically, when the buried insulating layer is Si ₃ N ₄ , or when the buried insulating layer is SiO ₂ and the film thickness is extremely thin (for example, 10 nm or less) In this case, the end insulator region 27 is not formed below the semiconductor layer.

  By employing such a manufacturing method, the element structure of the fourth embodiment can be formed.

(effect)
The fourth embodiment has an advantage that the height of the semiconductor layer end region 44 can be reduced as compared with the third embodiment. For example, in the semiconductor layer upper region 28 of FIG. 55, this corresponds to a form in which the semiconductor layer above the transition region 40 is removed, and the structure becomes simple, so that the height of the semiconductor layer is reduced. Further, the end insulator region 27 can be formed only by thermally oxidizing the semiconductor layer 3 in the region in contact with the cap insulating layer 8, and the manufacturing method is easy.

  In the fourth embodiment, the width of the upper region of the semiconductor layer and the width of the lower region of the semiconductor layer do not change steeply in the form shown in FIGS. The effect of solving the second problem is slightly inferior to that of the embodiment. However, compared to the conventional example of FIG. 85, in this embodiment, the end of the upper portion of the semiconductor layer is thicker than the gate insulating film 4 between the semiconductor layer and the gate electrode. Since the partial insulator 27 is provided and a channel is hardly formed on the side surface of the upper region of the semiconductor layer, the second problem is sufficiently solved and sufficient device performance can be obtained. Further, since the end insulator 27 thicker than the gate insulating film 4 is provided between the semiconductor layer and the gate electrode above the semiconductor layer, the ability to solve the first problem is excellent as in the third embodiment. .

(Fifth embodiment)
[Construction]
The field effect transistor according to the fifth embodiment has a semiconductor layer end region 44 of the semiconductor layer main portion 43 in addition to the features common to the third embodiment, the fourth embodiment, and the fifth embodiment. An insulating film thicker than the gate insulating film 4 is provided between the gate electrode 5 and the semiconductor layer end region 44 (semiconductor layer lower end region 42) provided below the semiconductor layer main portion 43. An end insulator region 27 is provided.

  Further, the field effect transistor according to the fifth embodiment has a semiconductor layer end region 44 in which the semiconductor layer end region 44 is the main part of the semiconductor layer, in addition to the features common to the third embodiment, the fourth embodiment, and the fifth embodiment. 43 is provided both above the semiconductor layer main portion 43 and below the semiconductor layer main portion 43, between the semiconductor layer end region 44 provided above the semiconductor layer main portion 43 and the gate electrode 5, and below the semiconductor layer main portion 43. An end insulator region 27 that is an insulating film thicker than the gate insulating film 4 is provided between the provided semiconductor layer end region 44 and the gate electrode 5.

[Production method]
The structure of the fifth embodiment is manufactured by, for example, the second manufacturing method of the fourth embodiment. However, it is desirable that the buried insulating layer 2 is made of SiO ₂ that easily diffuses an oxidizing agent such as oxygen in order to form the end insulator region 27 below the semiconductor layer.

  If the cap insulating layer 8 is removed after the end insulating film 27 is formed, the form of FIG. 68 is formed, and if the cap insulating layer 8 is not removed, the form of FIG. 66 is formed.

[effect]
The fifth embodiment improves the transistor characteristics by suppressing a potential increase in the lower corner portion of the semiconductor layer (corner portion at the lower end of the semiconductor layer) and suppressing a parasitic transistor in the lower corner portion of the semiconductor layer. Has an effect.

  In the structure in which the end semiconductor regions are provided both above and below the main part of the semiconductor layer and the end insulator regions 27 are provided above and below the semiconductor layer, the potentials at both the upper corner portion and the lower corner portion of the semiconductor layer. Since the rise can be suppressed and the parasitic transistor can be suppressed in both the upper corner portion and the lower corner portion of the semiconductor layer, the effect of improving the characteristics of the transistor is remarkable.

(Sixth embodiment)
The first to fourth embodiments of the present invention may be applied not only to a FinFET in which a semiconductor layer is formed on an insulator but also to a FinFET that does not have a buried insulating layer. Examples of this are shown in FIGS. 71 (a), 71 (b), 72 (a), 72 (b), and 73. FIG. 1 (a), 10 (a), 13 (a), 41, and 60, the embedded insulating layer 2 is not used.

  The sixth embodiment uses a normal semiconductor substrate, typically a silicon substrate, instead of the SOI substrate, which is a substrate having a buried insulating layer, in the manufacturing method of the first to fourth embodiments. Formed when there was. A shape in the middle of the manufacturing process is shown in FIG. FIG. 74A corresponds to FIG. 18A when a substrate having no embedded insulating layer is used. 74 (b) and 74 (c) are diagrams in a state where source / drain regions are formed and a transistor structure is formed, and correspond to FIGS. 19 (a) and 19 (b), respectively. .

Further, in a form that does not have a buried insulating layer below the semiconductor layer in these channel formation regions, an insulating film under the gate electrode is provided below the gate electrode 5 in order to obtain insulation between the gate electrode 5 and the support substrate 1. It is desirable to provide 31. The gate electrode insulating film 31 is formed by, for example, processing a semiconductor substrate by etching to form a convex semiconductor layer 3 and then depositing an insulator such as SiO _{2 on} the entire surface by a film forming technique such as a CVD method. The deposited insulator is planarized by a planarization technique such as CMP, and then the deposited insulator is etched back until the thickness of the insulator at the bottom of the semiconductor layer 3 becomes an appropriate thickness. . After the formation of the insulating film 31 under the gate electrode, the same manufacturing method as that in which the buried insulating layer is provided is manufactured. Note that it is desirable that the gate electrode insulating film 31 be formed of a material having a dielectric constant lower than that of SiO _{2 in} terms of suppression of parasitic capacitance between the gate electrode and the support substrate. Further, if the insulating film 31 under the gate electrode is formed of a material having a dielectric constant lower than that of SiO _2, it is effective for suppressing electric field concentration at the lower corner 35 of the semiconductor layer 3.

  When the sixth embodiment is applied to the third embodiment, the fourth embodiment, or the fifth embodiment, the side surface of the semiconductor layer 3 is in contact with the end insulator region 27. The portion is the semiconductor layer end region 44. In addition, the side of the semiconductor layer 3 that is not in contact with the end insulator region 27 and the side of the semiconductor layer 3 that faces the gate electrode through the gate insulating film is the semiconductor layer main region 43.

(Other Embodiments of the Invention)
Each embodiment of the present invention is not limited to a FinFET formed on a single semiconductor region, and may be applied to a plurality of FinFETs in which a semiconductor layer forming a channel formation region is separated. That is, as shown in FIG. 75A, the present invention may be applied to a transistor composed of a plurality of semiconductor layers each having a channel formed therein, and each channel is formed as shown in FIG. 75B. The present invention may be applied to a transistor in which a plurality of semiconductor layers are connected to each other at a position away from the gate. The position indicated by AA ′ in FIGS. 75A and 75B corresponds to the position of the AA ′ cross section in each embodiment.

  In each embodiment of the present invention, one of the upper corner portion and the lower corner portion of the semiconductor layer 3 or both the upper corner portion and the lower corner portion of the semiconductor layer 3 may have a rounded shape. In the third embodiment, for example, in FIG. 41, the lower corner portion of the semiconductor layer 3, the corner portion located near the upper end of the end insulator region in the semiconductor layer 3, and the lower end portion of the end insulator region in the semiconductor layer 3. At least one of the positioned corners may have a rounded shape.

  FIG. 76 shows a form in which the upper corner portion is rounded in the form of FIG. 1 (a), FIG. 77 (a) shows a form in which the upper corner part is rounded in the form of FIG. 10 (a), and FIG. FIG. 77 (b) shows a configuration in which the upper corner portion and the lower corner portion are rounded in FIG. 77B, FIG. 78 (a) shows a configuration in which the upper corner portion is rounded in the configuration in FIG. 78 (b) shows a form in which the upper corner part and the lower corner part are rounded in the form of b), and the corner part located near the upper end of the end insulator region in the semiconductor layer 3 in the form of FIG. FIG. 79 shows a form in which both corner portions of the layer 3 located near the lower end of the end insulator region are rounded. These forms are formed by thermally oxidizing the semiconductor layer.

  In the first embodiment, the upper corner of the semiconductor layer may be rounded and the cap insulating layer 8 may be rounded (FIGS. 87 and 88). Such a form is formed by performing sacrificial oxidation and wet etching of the semiconductor layer prior to formation of the gate oxide film. In particular, when the oxide film thickness in the sacrificial oxidation process is thick and the wet etching required to remove the sacrificial oxide film takes a long time, the corners of the semiconductor layer are rounded by sacrificial oxidation, and the corners of the cap insulating layer are increased in the wet etching process. Formed when etched and rounded. In such a form, the gate insulating film surface (interface on the gate electrode side) at the position where the surface of the gate insulating film is most receded from the gate electrode side among the same height as the upper end of the semiconductor layer and lower than the upper end of the semiconductor layer. On the other hand, if at least a part of the cap insulating layer protrudes to the gate electrode side (the extension width is indicated as Wext in the drawing), the electric field relaxation effect at the upper corner portion is the same as in the first embodiment. Is obtained. The overhang width Wext may be set similarly to the first embodiment. Other actions and principles are the same as in the first embodiment. The manufacturing method is also the same as that of the first embodiment except for the features in the sacrificial oxidation and the subsequent wet etching process as described above. Note that, as shown in FIG. 87, the cap insulating layer protrudes closer to the gate electrode side than the surface of the gate insulating film in the position where the width of the semiconductor layer is the widest, in order to obtain the electric field relaxation effect in the upper corner portion. preferable. However, as shown in FIG. 88, even if the cap insulating layer recedes from the gate electrode side with respect to the surface of the gate insulating film at the position where the width of the semiconductor layer is the widest, if the overhang width Wext is not zero, The electric field relaxation effect can be obtained to some extent.

  In the case where there is almost no flat portion on the contact surface between the cap insulating layer 8 and the semiconductor layer 3 as in the structure of FIG. 88, or when there is no flat portion on the contact surface between the cap insulating layer 8 and the semiconductor layer 3. As shown in FIG. 88, the overhang width Wext is defined in the horizontal direction (in the plane perpendicular to the direction in which the semiconductor layer 3 protrudes from the substrate and in the direction perpendicular to the channel length direction).

  By rounding the corner portion, the second problem is not completely solved. However, when each embodiment of the present invention is combined with the process of rounding the corner portion, the corner portion is simply not combined with each embodiment of the present invention. As compared with the case of rounding, it is possible to reduce the rounding amount necessary for obtaining the electric field relaxation effect that can solve the first problem, and the radius of curvature of the corner portion can be reduced. Therefore, when each embodiment of the present invention is combined with the process of rounding the corner portion, the area having a curved surface is reduced. Therefore, even if the second problem cannot be completely eliminated, the second problem is greatly increased. Can be reduced.

(Specific examples of materials, dimensions, shapes, and process conditions in each embodiment)
Specific examples of materials, dimensions, shapes, and process conditions in (first embodiment) to (sixth embodiment) and (other embodiments) will be given.

(Support substrate)
The support substrate 1 is usually a single crystal silicon wafer, but a substrate other than a silicon substrate such as quartz, glass, sapphire, or a semiconductor other than silicon may be used.

(Embedded insulating layer 2)
The buried insulating layer 2 is usually made of SiO ₂ , but may be another insulator or a multilayer film made of a plurality of materials. The buried insulating layer may be a low dielectric constant material having a dielectric constant lower than that of SiO ₂ such as porous SiO ₂ or SiOF. Further, when the support substrate is an insulator such as quartz, glass, sapphire, the support substrate 1 may also serve as the buried insulating film 2. The thickness of the buried insulating layer 2 is usually about 50 nm to 2 μm, more typically 50 nm to 200 nm, but may be 50 nm or less or 2 μm or more as necessary.

  In the sixth embodiment, a structure without the buried insulating layer 2 is used.

(Semiconductor layer 3)
The semiconductor layer 3 is most preferably a single crystal from the viewpoint of improving the on-current and suppressing the off-current, but when the required on-current specification is low or the required off-current specification is large. A material other than a single crystal such as amorphous or polycrystalline may be used.

  The semiconductor layer 3 may be replaced with a semiconductor layer other than silicon. Further, it may be replaced by a combination of two or more kinds of semiconductors.

  The semiconductor layer has a shape protruding from the substrate surface. The substrate surface is generally the upper surface of the support substrate 1, but in the case of a structure in which the embedded insulating layer 2 and the support substrate are integrated, it is the upper surface of the embedded insulating layer 2. When the under-gate insulating film 31 is provided, it is the upper surface of the under-gate insulating film 31.

  The height Hfin of the semiconductor layer 3 (see FIGS. 82 (a), 83 (a), 71 (b), and 72 (b)) is typically 20 nm to 150 nm, more typically 50 nm to 100 nm. The width Wfin of the semiconductor layer (see FIGS. 82A, 83A, and 72B) is typically 5 nm to 100 nm, and more typically 15 nm to 50 nm. However, values outside this range may be used for both Hfin and Wfin. However, the semiconductor layer in the channel formation region is depleted in a state where a threshold voltage is applied to the gate electrode, and the characteristics of FinFET (such as a sharpening of ON-OFF characteristics represented by a reduction in S factor). It is desirable from the viewpoint of saving. In order to realize a fully depleted state in which depletion layers extending from both sides of the semiconductor layer are in contact with each other with a threshold voltage applied to the gate electrode, Wfin is usually 50 nm or less, more typically 30 nm or less. It is preferable to set to.

(Gate insulation film 4)
The gate insulating film 4 may be formed by thermal oxidation of silicon, or may be a SiO ₂ film formed by another method. For example, a SiO ₂ film formed by radical oxidation may be used. The gate insulating film may be replaced with an insulating material other than SiO ₂ . Further, it may be replaced with multi-layer film or a multilayer film between the insulation films other than SiO _2, the SiO ₂ and the other insulating film. The gate insulating film may be replaced with a high dielectric constant material such as HfO ₂ or HfSiO ₄ .

The equivalent oxide thickness of the gate insulating film is typically 1.2 nm to 3 nm. However, the equivalent oxide thickness is obtained by multiplying the quotient obtained by dividing the thickness of the insulating film constituting the gate insulating film by the dielectric constant of the gate insulating film by the dielectric constant of SiO ₂ . When the gate insulating film is a multilayer film, the oxide film equivalent film thickness is obtained for each layer by the above method, and these are added together.

(Gate electrode 5)
The gate electrode 5 may be a polycrystalline semiconductor such as polysilicon, or may be a conductor other than a polycrystalline semiconductor such as a metal or a metal compound. When the gate electrode 5 is made of a polycrystalline semiconductor such as polysilicon, typically, a first conductivity type impurity having the same conductivity type as the channel is introduced into the polysilicon of the gate electrode 5 at a high concentration. . Further, the gate electrode may be formed by a replacement gate (also called a replacement gate) process. That is, the shape of the gate electrode is once formed with a dummy material, the first conductivity type impurity is introduced into the source / drain region at a high concentration, the dummy material is covered with an insulating film, and then the dummy material is removed. You may form by the process of burying a gate electrode or a gate insulating film, and a gate electrode in the formed cavity.

  In the case where the gate electrode material is formed of a semiconductor such as polysilicon or polycrystalline silicon-germanium mixed crystal, the introduction of impurities into the gate may be performed simultaneously with the introduction of impurities into the source / drain. Further, it may be performed simultaneously with the deposition of the gate electrode material. Alternatively, it may be performed before the gate electrode material is deposited and processed into the shape of the gate electrode.

  The gate electrode usually has a structure straddling the semiconductor layer. According to the present invention, a gate electrode is disposed above a semiconductor layer and on a side surface of the semiconductor layer. In a transistor in which electric field concentration occurs due to an electric field from the gate above the semiconductor layer and an electric field from the gate on the side surface of the semiconductor layer, Especially effective for mitigating.

  Further, although the gate electrode is not disposed above the semiconductor layer, FinFET (FIG. 93. FIG. 93 is located at the same position as FIG. 92) is caused by electric field from the side surface of the gate electrode extending above the upper end of the semiconductor layer. The present invention may be applied to a corresponding sectional view. FIG. 94 shows a case where the second embodiment is applied to a FinFET in which no gate electrode is arranged above the semiconductor layer, and FIG. 95 shows a case where the third embodiment is applied. 94 is a cross-sectional view corresponding to FIG. 10, and FIG. 95 is a cross-sectional view corresponding to FIG.

(Source / drain region 6)
Impurities of the first conductivity type are introduced into the source / drain regions 6 at a high concentration. Note that in this specification, the source / drain regions include all regions called shallow source / drain regions (also referred to as extension regions) and regions called deep source / drain regions in a bulk transistor. In FinFET, the definitions of extension regions and deep source / drain regions are not generally clarified. For example, in FIG. 75B, the source / drain regions formed in a strip-shaped region adjacent to the gate are separated from the gate. It is assumed that both the areas where the strip-like areas are connected to each other at the positions are included. In addition, in order to reduce the parasitic resistance of the source / drain region, a semiconductor such as silicon is epitaxially grown on a part of the source / drain region, thereby increasing the size of the semiconductor layer forming the source / drain region upward or in the in-plane direction. It is also possible to combine techniques for enlarging.

  In the present invention, source / drain regions are provided in a portion of the semiconductor layer 3 that is not covered with the gate electrode. However, in addition to the source / drain regions provided in the portion not covered with the gate electrode, the source / drain regions that have penetrated into the region covered with the gate electrode in the semiconductor layer 3 may be provided. When the source / drain region penetrates into the region covered with the gate electrode in the semiconductor layer 3, it is provided in the source / drain region provided in the portion not covered with the gate electrode and the portion covered with the gate electrode in the semiconductor layer 3. The source / drain regions are usually connected continuously.

  In addition, a source / drain region may be provided with an offset region having a certain width from the semiconductor layer covered with the gate electrode. In this case, since the parasitic resistance is increased, the drain current is reduced, but the electric field strength at the end of the source / drain region is reduced, so that the leakage current is reduced. This structure is preferably applied to a DRAM (Dynamic Random Access Memory) cell transistor in which reduction of leakage current is given priority over the magnitude of drain current.

(Channel formation region 7)
A low concentration of acceptor or donor impurities is introduced into the channel formation region 7. When the gate electrode is polysilicon of the first conductivity type, a low-concentration second conductivity type impurity is typically introduced into the channel formation region because it is necessary to set the threshold voltage to an appropriate value. However, even when the first conductivity type polysilicon or the material having the same work function as the first conductivity type polysilicon is used for the gate electrode, the threshold voltage is set low, or the gate electrode is made of metal, metal When a material having a work function different from that of the first conductivity type polysilicon such as silicide is used, no impurity is introduced into the channel forming region 7 or a low concentration first conductivity type impurity is introduced. Also good.

  Further, the second conductivity type impurity is introduced into the channel formation region adjacent to the source / drain region covered with the gate electrode slightly higher than the portion not adjacent to the source / drain region covered with the gate electrode. Alternatively, a halo region may be provided.

  Further, by increasing the concentration of the second conductivity type impurity in the upper or lower portion of the semiconductor layer 3 forming the channel formation region, the potential increase in the upper corner portion or the lower corner portion of the semiconductor layer 3 and the accompanying parasitics, respectively. A method for suppressing the transistor may be used in combination.

  FIG. 96 shows the case where the technique for increasing the concentration of the second conductivity type impurity in the upper part of the semiconductor layer 3 forming the channel formation region is applied to the first embodiment, and FIG. 97 shows the case where it is applied to the second embodiment. FIG. 98 and FIG. 99 show a case where the present invention is applied to the third embodiment. 96 corresponds to FIG. 1, FIG. 97 corresponds to FIG. 10, FIG. 98 and FIG. 99 correspond to FIG. Symbol 47 in the figure is a region where the concentration of the second conductivity type impurity is high.

  Japanese Patent Application Laid-Open No. 6-302817 discloses a technique for providing a high-concentration portion on the top of a FinFET semiconductor layer in order to suppress the parasitic transistor. However, by using each embodiment of the present invention in combination, the parasitic transistor The impurity concentration in the upper part of the semiconductor layer, which is necessary for suppressing the above, can be set low. If the impurity concentration at the upper part of the semiconductor layer is set lower, the electric field strength between the edge of the source / drain region and the higher concentration part at the upper part of the semiconductor layer becomes smaller, so Leakage current with the part is reduced.

(Cap insulation layer 8)
The cap insulating layer 8 is provided on the semiconductor layer 3. In the structure in which the gate electrode 5 straddles the semiconductor layer 3 (such as FIG. 1), the cap insulating layer 8 is provided under the gate electrode. The cap insulating layer 8 is disposed so that at least a part of the cap insulating layer 8 is placed at a position lower than the upper end of the gate electrode regardless of whether the gate electrode 5 straddles the semiconductor layer 3 or not. (A case where the gate electrode 5 does not straddle the semiconductor layer 3 is shown in FIGS. 94 and 95).

The cap insulating layer 8 may be a single-layer insulating film such as a SiO ₂ film or a Si ₃ N ₄ film, or may be a multilayer film made of an insulating film such as a SiO ₂ film or a Si ₃ N ₄ film. . Further, part or all of the cap insulating layer 8 may be made of a material having a dielectric constant lower than that of SiO ₂ . Moreover, a part or all of the cap insulating layer 8 may be formed of a cavity. The cap insulating layer 8 may be formed of a protective insulating film made of an insulator such as SiO ₂ provided around the cavity and the cavity.

The thickness of the cap insulating layer 8 is at least twice that of the gate insulating film, more typically at least five times the thickness of the gate insulating film. The thickness of the cap insulating layer 8 is typically 10 nm to 100 nm, more typically 10 nm to 50 nm. However, it is sufficient that the thickness of the cap insulating layer 8 is at least twice as large as the gate insulating film thickness. When the gate insulating film is thin, it may be 10 nm or less. The thickness of the cap insulating layer 8 is a thickness as viewed in a direction perpendicular to the upper surface of the semiconductor layer, and is usually a thickness in the vertical direction. When the gate insulating film and the cap insulating layer are made of different materials, the ratio of the thickness of the gate insulating film is the converted film thickness (the quotient obtained by dividing the physical film thickness by the dielectric constant (usually This is a comparison in (multiplied by the relative dielectric constant of SiO ₂ ).

(Low dielectric constant region 10)
The thickness of the low dielectric constant region 10 provided above or below the semiconductor layer is typically 10 nm to 100 nm, more typically 20 nm to 50 nm. In order to obtain a large effect, it is desirable to have a thickness of 10 nm or more.

The material in the low dielectric constant region is a material containing Si and having a lower dielectric constant than SiO ₂ , such as SiOF, porous SiO ₂ , porous siloxane, or a low dielectric constant material having a Si—O—Si skeleton. May be. These materials have the advantage that they are more resistant to heat treatment processes than low dielectric constant materials made of organic materials. The material of the low dielectric constant region may be a material containing C and having a lower dielectric constant than SiO ₂ , such as black diamond, amorphous carbon, or a low dielectric constant material made of an organic material. Since these materials generally have low resistance to heat treatment processes, transistors are manufactured under low temperature conditions such as deposition of gate insulating films by CVD instead of thermal oxidation and activation of source / drain regions by low-temperature solid phase growth. It is particularly desirable to be applied when implemented. The low dielectric constant region may be a cavity. Alternatively, the low dielectric constant region may be formed of a porous material, and the low dielectric constant region may include a large number of cavities.

(Dummy layer 11)
The corner dummy layer 22 may be any material that can be selectively removed in the manufacturing process. For example, when Si ₃ N ₄ is used for the corner dummy layer 22, the corner dummy layer 22 is selectively etched with phosphoric acid. When the gate insulating film and the buried insulating layer are made of a material that is not etched by hydrofluoric acid such as Si ₃ N ₄ , SiO ₂ is used for the corner dummy layer 22 and the corner dummy layer 22 is selectively formed by hydrofluoric acid. Etch.

(Cavity 12)
The inside of the cavity is a vacuum or an appropriate gas has entered. The cavity 12 is not filled with solid material.

(Gate side wall 14)
The gate sidewall 14 may be a single-layer insulating film such as a SiO ₂ film or a Si ₃ N ₄ film, or may be a multilayer film made of an insulating film such as a SiO ₂ film or a Si ₃ N ₄ film. The thickness of the gate side wall 14 is normally 20 nm to 150 nm, but may be 20 nm or less when the element needs to be miniaturized.

  When the cavity 12 is formed in the upper or lower portion of the semiconductor layer 3 and the gate sidewall 14 is provided after the formation of the cavity, the step of depositing the insulating film to be the gate sidewall 14 is performed by using a deposition technique with poor coverage. It is desirable not to be buried. For example, CVD is performed under conditions where the gas partial pressure is relatively high. When the gate sidewall 14 is a multilayer film, only the insulating film deposited first may be formed using a deposition technique that is inferior in coverage.

(Silicide layer 15)
The silicide layer 15 is typically made of a material such as titanium silicide, cobalt silicide, nickel silicide, or platinum silicide, but other silicides may be used. The silicide layer 15 is formed by depositing a metal such as titanium, cobalt, nickel, or platinum on the source / drain region by a deposition technique such as sputtering, and performing a heat treatment to cause a silicidation reaction between the metal and the silicon layer. To form.

(Contact 17 and wiring 18)
The contact 17 and the wiring 18 are formed by a normal contact formation process and a normal wiring process. The contact 17 and the wiring 18 are usually formed of a metal such as aluminum or copper, and other conductive materials such as TiN are appropriately combined.

(Support insulating film 21)
The supporting insulating film 21 is usually an insulating film such as SiO ₂ deposited by a film forming technique such as CVD, but may be a film formed by other methods as long as insulation can be obtained. A film other than SiO ₂ may be used.

(Corner dummy layer 22)
The corner dummy layer 22 may be any material that can be selectively removed in the manufacturing process. For example, when Si ₃ N ₄ is used for the corner dummy layer 22, the corner dummy layer 22 is selectively etched with phosphoric acid. When the gate insulating film and the buried insulating layer are made of a material that is not etched by hydrofluoric acid such as Si ₃ N ₄ , SiO ₂ is used for the corner dummy layer 22 and the corner dummy layer 22 is selectively formed by hydrofluoric acid. Etch.

(End insulator regions 23 and 27)
The end insulator regions (23, 27) may be any insulating material, and examples thereof include materials such as SiO ₂ and Si ₃ N ₄ . Further, from the viewpoint of alleviating electric field concentration, it is more preferable that the end insulator regions 23 and 27 are made of the same low dielectric constant material as that of the low dielectric constant region 10. For example, SiOF, a porous material, fluorinated carbon, a cavity, etc. are mentioned.

  The width Wei of the end insulator regions (23, 27) may be smaller than half the width Wfin of the entire semiconductor and thicker than the gate oxide film. A typical upper limit is about 15 nm, and more typically 5 nm to 10 nm. The height Htop of the end insulator region is not particularly limited, but is generally less than half of the total height of the semiconductor layer including the upper region 28, and more typically 5 nm to 25 nm. .

  The width Wei of the end insulator does not have to be constant, but at least at a position in contact with the upper end portion of the semiconductor layer 3, it is desirable that the thickness is larger than the thickness of the gate oxide film. When the width Wei of the end insulator is not constant, a typical upper limit of the maximum value of Wei is about 15 nm, and more typically 5 nm to 10 nm.

(Introduction of impurities)
In ion implantation, donor impurities or acceptor impurities of typically 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ are introduced into high concentration regions such as source / drain regions and gate electrodes. More typically, 3 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ of donor impurities or acceptor impurities are introduced. Impurities are introduced by, for example, ion implantation or gas phase diffusion. Typical doses during ion implantation are 1 × 10 ¹⁴ cm ⁻² to 3 × 10 ¹⁵ cm ⁻² , more typically 3 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² .

The net impurity concentration (absolute value of the difference between the first conductivity type impurity concentration and the second conductivity type impurity concentration) in a low concentration region such as a channel formation region is typically 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 6. ¹⁹ cm ⁻³ , more typically 5 × 10 ¹⁷ cm ⁻³ to 5 × 10 ¹⁸ cm ⁻³ . However, even in a transistor having these typical impurity concentrations in the main part of each region, these typical values may be locally exceeded depending on ion implantation conditions.

Further, the influence of the parasitic transistor is particularly remarkable when the net impurity concentration of the second conductivity type in the channel formation region is 1 × 10 ¹⁸ cm ⁻³ or more. This is particularly effective when applied to a field effect transistor having a net impurity concentration of 2 × 10 ¹⁸ cm ⁻³ or more. Moreover, electric field concentration is alleviated for reasons other than suppression of parasitic transistors (improved gate insulating film reliability, improved gate insulating film yield, and suppression of short channel effect as described in the second embodiment). In order to achieve this, a field effect transistor having a second conductivity type net impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or less in the channel formation region, and further, whether impurities are introduced into the channel formation region or the channel formation region However, each embodiment of the present invention may be applied to a field effect transistor of the first conductivity type.

  For the first conductivity type impurity introduced into the source / drain region and the first conductivity type impurity introduced into the source / drain region, in the case of an n channel transistor, a donor impurity having an n type conductivity type is used as a p channel transistor. In this case, an acceptor impurity having a p-type conductivity may be selected.

  As the second conductivity type impurity introduced into the halo region, an acceptor impurity having a p-type conductivity type may be selected for an n-channel transistor, and a donor impurity having an n-type conductivity type may be selected for a p-channel transistor. .

  Typical examples of n-type impurities are arsenic, phosphorus and antimony. Typical examples of p-type impurities are boron and indium.

  The ion-implanted impurity is activated by heat treatment such as annealing in an ordinary electric furnace or lamp annealing after ion implantation. Note that the heat treatment for activating the ions implanted into the channel region may be performed immediately after the ion implantation, or may be combined with the heat treatment for activating the impurities introduced into the source / drain regions.

  An impurity may be introduced into the source / drain region by a method of introducing the impurity into a region not covered with the gate electrode after the formation of the gate electrode. Before the formation of the gate electrode, the source / drain region may be introduced. A method in which impurities are introduced into a region to be formed in advance may be used.

(Arrangement of source / drain region 6, contact 17, and wiring 18)
The arrangement of each part constituting the semiconductor device such as the source / drain region 6, the interlayer insulating film 16, the contact 17, and the wiring 18 in each embodiment is the same as that of a normal FinFET. For example, the same arrangement as that shown in FIGS. 8 and 9 for explaining the first embodiment is adopted.

  In each embodiment, an n-channel transistor has been mainly described. However, in a p-channel transistor, if the polarity is reversed (for example, a potential increase in an n-channel transistor is read as a potential decrease in a p-channel transistor). In addition, a decrease in threshold voltage in an n-channel transistor can be read as an increase in threshold voltage in a p-channel transistor, and a statement that a voltage or potential is high can be read as a voltage or potential is low. The sign of the applied voltage such as the drain voltage is reversed.) A similar argument holds.

Claims (67)

A semiconductor layer projecting upward from the plane of the substrate, a gate electrode extending on opposite side surfaces from the top so as to straddle the semiconductor layer, and gate insulation interposed between the gate electrode and the side surface of the semiconductor layer A film, a cap insulating layer provided on the semiconductor layer and positioned under the gate electrode, and a source / drain region formed in a region of the semiconductor layer not covered by the gate electrode,
The cap insulating layer has a projecting portion projecting from the surface of the gate insulating film in a direction parallel to the substrate plane and perpendicular to a channel length direction connecting a pair of source / drain regions. Field effect transistor.   2. The field effect transistor according to claim 1, wherein the projecting portion has a projecting width of 5 nm or more with respect to the surface of the gate insulating film.   The field effect transistor according to claim 1, wherein the overhanging portion has an overhanging width of 5 nm or more and 20 nm or less with respect to the surface of the gate insulating film.   4. The field effect transistor according to claim 1, wherein the overhanging portion has an overhanging width with respect to the surface of the gate insulating film that is not less than 2.5 times the thickness of the gate insulating film.   4. The field effect transistor according to claim 1, wherein the overhanging portion has an overhanging width with respect to the surface of the gate insulating film that is not less than 2.5 times and not more than 10 times the thickness of the gate insulating film.   6. The overhanging portion according to claim 1, wherein the overhanging portion overhangs the surface of the gate insulating film at a position where the width in the direction parallel to the substrate plane of the semiconductor layer and perpendicular to the channel length direction is the widest. Field effect transistor. It is a manufacturing method of the field effect type transistor according to any one of claims 1 to 6,
Forming a cap insulating layer on the semiconductor layer, patterning the semiconductor layer and the cap insulating layer to form a semiconductor layer protruding upward from a substrate plane, and forming a patterned cap insulating layer thereon;
Etching the side surface of the semiconductor layer so that the side surface of the semiconductor layer under the cap insulating layer recedes inward from the end of the cap insulating layer; and
And a step of forming a gate insulating film on a side surface of the semiconductor layer. Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
8. The method of manufacturing a field effect transistor according to claim 7, further comprising a step of forming a source / drain region by introducing impurities into the semiconductor layer. A semiconductor layer protruding upward from the substrate plane, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer, and a cover covering the gate electrode A source / drain region formed in an undisclosed region,
The field effect transistor further comprises a low dielectric constant region having a dielectric constant lower than that of SiO _{2 at a} position lower than the upper end of the gate electrode above the semiconductor layer. 10. The field effect transistor according to claim 9, wherein the field effect transistor has a low dielectric constant region having a dielectric constant lower than that of SiO _{2 in} contact with an upper portion of the semiconductor layer. A protective insulating film having a higher dielectric constant than SiO ₂ or SiO ₂ is provided in contact with an upper portion of the semiconductor layer, and a low dielectric constant region having a lower dielectric constant than SiO ₂ is provided on the protective insulating film. 10. The field effect transistor according to 9.   The field effect transistor according to any one of claims 9 to 11, wherein the low dielectric constant region comprises a cavity. The field effect transistor according to claim 9, further comprising a low dielectric constant region having a dielectric constant lower than that of SiO ₂ below the semiconductor layer. The bottom of said semiconductor layer has a low dielectric constant region having a lower dielectric constant than SiO _2, the lower portion of the gate electrode, according to claim 9 having no low dielectric region having a lower dielectric constant than SiO ₂ 13. The field effect transistor according to any one of 12 above.   15. The field effect transistor according to claim 13, wherein the low dielectric constant region provided under the semiconductor layer is formed of a cavity. The semiconductor layer is provided on the first insulating layer via a second insulating layer made of a material different from that of the first insulating layer,
The field effect transistor according to any one of claims 9 to 12, wherein the gate electrode has a portion directly in contact with the first insulating layer without passing through the second insulating layer on the first insulating layer. The field effect transistor according to claim 16, wherein the second insulating layer is made of a material having a dielectric constant lower than that of SiO ₂ .   The field effect transistor according to claim 16, wherein the second insulating layer comprises a cavity. The field effect transistor according to claim 1, wherein at least a part of the cap insulating layer is made of a low dielectric constant material having a dielectric constant lower than that of SiO ₂ .   The field effect transistor according to claim 1, wherein at least a part of the cap insulating layer has a cavity. 21. The field effect transistor according to claim 20, further comprising a protective insulating film having a dielectric constant higher than that of SiO ₂ or SiO ₂ between the semiconductor layer and the cavity. The field effect transistor according to any one of claims 1 to 6, further comprising a low dielectric constant region having a dielectric constant lower than that of SiO ₂ below the semiconductor layer. The bottom of said semiconductor layer has a low dielectric constant region having a lower dielectric constant than SiO _2, the lower portion of the gate electrode, according to claim 1 having no low dielectric region having a lower dielectric constant than SiO ₂ The field effect transistor according to claim 6.   The field effect transistor according to claim 22 or 23, wherein the low dielectric constant region comprises a cavity. A method of manufacturing a field effect transistor according to claim 9,
Depositing a material having a lower dielectric constant than SiO ₂ on the semiconductor layer to form a low dielectric constant film;
A field effect transistor having a step of patterning the semiconductor layer and the low dielectric constant film to form a semiconductor layer protruding from the plane of the substrate and a low dielectric constant region comprising the low dielectric constant film patterned thereon Manufacturing method. Forming a gate insulating film on the side surface of the protruding semiconductor layer;
Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
26. The method of manufacturing a field effect transistor according to claim 25, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer. A method of manufacturing a field effect transistor according to claim 9,
Forming a dummy layer on the semiconductor layer;
Patterning the semiconductor layer and the dummy layer to form a semiconductor layer protruding from the substrate plane and a patterned dummy layer thereon;
Removing the dummy layer and forming a cavity as the low dielectric constant region above the semiconductor layer. Forming a gate insulating film on the side surface of the protruding semiconductor layer;
Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
A step of forming a source / drain region by introducing impurities into the semiconductor layer;
28. The method of manufacturing a field effect transistor according to claim 27, wherein the low dielectric constant region including the cavity is formed by removing the dummy layer after forming the gate electrode. Method of manufacturing a field effect transistor according to claim 27 or 28, wherein further comprising the step of backfilling said cavity with a material having a lower dielectric constant than SiO _2.   29. The method of manufacturing a field effect transistor according to claim 27, further comprising a step of filling the cavity with a porous material. A semiconductor layer projecting upward from the substrate plane; gate electrodes provided on both sides of the semiconductor layer; a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer; and the semiconductor layer A source / drain region formed in a region not covered by the gate electrode,
A field effect transistor having an end insulator region thicker than the gate insulating film on a side surface of the upper portion of the semiconductor layer and a gate electrode. A semiconductor layer projecting upward from the substrate plane; gate electrodes provided on both sides of the semiconductor layer; a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer; and the semiconductor layer A source / drain region formed in a region not covered by the gate electrode,
The semiconductor layer includes a semiconductor layer upper region in which the width W of the semiconductor layer in the direction parallel to the substrate plane in a plane perpendicular to the channel length direction connecting the pair of source / drain regions is smaller than the width of the lower portion thereof, and the semiconductor layer A semiconductor layer lower region located below the upper region, wherein the width W of the semiconductor layer is larger than the width of the upper region of the semiconductor layer;
The semiconductor layer upper region has an end insulator whose side surface of the semiconductor layer recedes from the side surface of the semiconductor layer in the lower region of the semiconductor layer, and is thicker than the gate insulating film between the receded side surface and the gate electrode. A field effect transistor having a region.   The field effect transistor according to claim 32, wherein a width W of the upper portion of the semiconductor layer is constant.   33. The field effect transistor according to claim 32, wherein the width W of the upper portion of the semiconductor layer is continuously changed, and the thickness of the end insulator region is continuously changed accordingly.   The width W of the upper part of the semiconductor layer gradually decreases with a certain gradient toward the upper end of the semiconductor layer, and accordingly, the thickness of the end insulator region gradually increases toward the upper end of the semiconductor layer. The field effect transistor according to claim 32.   The width W of the upper portion of the semiconductor layer is gradually decreased so that the side surface of the semiconductor layer has a curvature as it goes to the upper end of the semiconductor layer, and the thickness of the end insulator region is accordingly reduced. The field effect transistor according to claim 32, wherein the field effect transistor gradually increases toward the upper end of the transistor.   32. The field effect transistor according to claim 31, wherein the width W of the semiconductor layer is constant from the lower end to the upper end of the semiconductor layer. A semiconductor layer projecting upward from the substrate plane; gate electrodes provided on both sides of the semiconductor layer; a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer; and the semiconductor layer A source / drain region formed in a region not covered by the gate electrode,
The semiconductor layer includes a semiconductor layer upper region in which the width W of the semiconductor layer in the direction parallel to the substrate plane in a plane perpendicular to the channel length direction connecting the pair of source / drain regions is smaller than the width of the lower portion thereof, and the semiconductor layer A semiconductor layer lower region located below the upper region, wherein the width W of the semiconductor layer is larger than the width of the upper region of the semiconductor layer;
The upper region of the semiconductor layer has a transition region in which the width W of the semiconductor layer continuously changes in a portion connected to the lower region of the semiconductor layer, and the width W extends from the end of the transition region to the upper end of the semiconductor layer. Constant,
A field effect transistor having an end insulator region thicker than the gate insulating film between the semiconductor layer upper region and the gate electrode.   The field effect transistor according to any one of claims 31 to 38, wherein a cap insulating layer thicker than the gate insulating film is provided on the semiconductor layer.   40. The field effect transistor according to claim 39, wherein the end insulator region is made of a material different from that of the cap insulating layer. The field effect transistor according to any one of configured claim 31 to 39 wherein the end insulator region by SiO _2. At least a part of the field effect transistor according to any one of claims 31 to 39 composed of a material having a lower dielectric constant than SiO ₂ of the end insulator region.   The field effect transistor according to any one of claims 31 to 39, wherein at least a part of the end insulator region is made of a porous material.   The field effect transistor according to any one of claims 31 to 39, wherein at least a part of the end insulator region is constituted by a cavity. A method of manufacturing a field effect transistor according to claim 32, wherein
Depositing a first insulating film on the semiconductor layer, and patterning the first insulating film and the upper portion of the semiconductor layer to a predetermined width;
Depositing and etching back the second insulating film to form an end insulator region made of the second insulating film on the side surface of the patterned first insulating film and the side surface of the semiconductor layer;
Etching the semiconductor layer using the end insulator region and the patterned first insulating film as a mask;
And a step of forming a gate insulating film on a side surface of the semiconductor layer exposed by the etching. Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
46. The method of manufacturing a field effect transistor according to claim 45, further comprising a step of forming a source / drain region by introducing impurities into the semiconductor layer. A method of manufacturing a field effect transistor according to claim 32, wherein
Depositing a cap insulating layer on the semiconductor layer, and patterning the cap insulating layer and the upper portion of the semiconductor layer to a predetermined width;
Depositing and etching back a dummy layer, forming a corner dummy layer made of the dummy layer on the side surface of the patterned cap insulating layer and the side surface of the semiconductor layer;
Etching the semiconductor layer using the corner dummy layer and the patterned cap insulating layer as a mask;
Forming a gate insulating film on a side surface of the semiconductor layer exposed by the etching;
And a step of forming an end insulator region made of a cavity by removing the corner dummy layer. A method of manufacturing a field effect transistor according to claim 32, wherein
Depositing a cap insulating layer on the semiconductor layer, and patterning the cap insulating layer and the upper portion of the semiconductor layer to a predetermined width;
Depositing and etching back the first dummy layer to form a first corner dummy layer made of the first dummy layer on the side surface of the patterned cap insulating layer and the side surface of the semiconductor layer;
Depositing and etching back the second dummy layer to form a second corner dummy layer made of the second dummy layer on the side surface of the first corner dummy layer;
Etching the semiconductor layer using the first and second corner dummy layers and the patterned cap insulating layer as a mask;
Forming a gate insulating film on a side surface of the semiconductor layer exposed by the etching;
And removing the first corner dummy layer to form a cavity end insulator region. Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
A step of forming a source / drain region by introducing impurities into the semiconductor layer;
49. The method of manufacturing a field effect transistor according to claim 47, wherein an end insulator region comprising the cavity is formed after forming the gate electrode. After the corner dummy layer is removed to form a cavity, the cavity is filled with a low dielectric constant material having a dielectric constant lower than that of SiO _{2 and} an end insulator region made of the low dielectric constant material is formed. 49. The method of manufacturing a field effect transistor according to claim 47 or 48, further comprising: A method of manufacturing a field effect transistor according to claim 35, wherein
Forming a first insulating film on the semiconductor layer and patterning the first insulating film;
Etching the upper part of the semiconductor layer with the patterned first insulating film as a mask so that the width W of the semiconductor layer gradually decreases toward the upper end;
Depositing and etching back the second insulating film, and forming an end insulator region made of the second insulating film on the side surface of the patterned first insulating film and the tapered side surface of the semiconductor layer;
Etching the semiconductor layer using the end insulator region and the patterned first insulating film as a mask;
And a step of forming a gate insulating film on a side surface of the semiconductor layer exposed by the etching. Removing the patterned first insulating film and the second insulating film on the side surfaces thereof to expose the upper surface of the semiconductor layer;
52. The method of manufacturing a field effect transistor according to claim 51, wherein, in the step of forming the gate oxide film, a gate oxide film is formed on the exposed upper surface in addition to the side surface of the semiconductor layer. Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
52. The method of manufacturing a field effect transistor according to claim 51, further comprising the step of forming a source / drain region by introducing impurities into the semiconductor layer. A method of manufacturing a field effect transistor according to claim 36,
Forming an oxidant-permeable cap insulating layer on the semiconductor layer;
Patterning the cap insulating layer and the semiconductor layer to form a semiconductor layer protruding from the plane of the substrate and a patterned cap insulating layer thereon;
At the interface between the semiconductor layer and the cap insulating layer, the semiconductor layer is oxidized in an oxidant atmosphere so that the side surface of the semiconductor layer recedes inward from the end of the cap insulating layer, and the semiconductor layer A method of manufacturing a field effect transistor, comprising: forming a semiconductor layer upper region whose upper width W gradually decreases toward the upper end of the semiconductor layer; and a step of forming an end insulating region whose thickness gradually increases accordingly . Forming a gate insulating film on a side surface of the semiconductor layer;
Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
55. The method of manufacturing a field effect transistor according to claim 54, further comprising a step of forming a source / drain region by introducing impurities into the semiconductor layer. Removing the cap insulating layer to expose an upper surface of the semiconductor layer;
Forming a gate insulating film on an upper surface and a side surface of the semiconductor layer;
Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
55. The method of manufacturing a field effect transistor according to claim 54, further comprising a step of forming a source / drain region by introducing impurities into the semiconductor layer. A semiconductor layer projecting upward from the substrate plane; gate electrodes provided on both sides of the semiconductor layer; a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer; and the semiconductor layer A source / drain region formed in a region not covered by the gate electrode,
The upper side surface of the semiconductor layer has a first end insulator region thicker than the gate insulating film between the gate electrode and the gate electrode,
A field effect transistor having a second end insulator region thicker than the gate insulating film on a side surface of the lower portion of the semiconductor layer between the gate electrode and the gate electrode. A semiconductor layer projecting upward from the substrate plane; gate electrodes provided on both sides of the semiconductor layer; a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer; and the semiconductor layer A source / drain region formed in a region not covered by the gate electrode,
The semiconductor layer includes a semiconductor layer upper region in which the width W of the semiconductor layer in the direction parallel to the substrate plane in a plane perpendicular to the channel length direction connecting the pair of source / drain regions is smaller than the width of the lower portion thereof, and the semiconductor layer A semiconductor layer main portion region located below the upper region and having a width W of the semiconductor layer larger than the width of the semiconductor layer upper region, and located below the semiconductor layer main portion region, the width W of the semiconductor layer being A semiconductor layer lower region smaller than the width of the semiconductor layer main region,
The semiconductor layer upper region has a first end whose side surface of the semiconductor layer is recessed from the side surface of the semiconductor layer in the main region of the semiconductor layer, and is thicker than the gate insulating film between the retracted side surface and the gate electrode. A partial insulator region,
The semiconductor layer lower region has a second end whose side surface of the semiconductor layer recedes from the side surface of the semiconductor layer in the main region of the semiconductor layer, and is thicker than the gate insulating film between the receded side surface and the gate electrode. A field effect transistor having a partial insulator region.   59. The field effect transistor according to claim 57 or 58, wherein a cap insulating layer thicker than a gate insulating film is provided on the semiconductor layer. A method of manufacturing a field effect transistor according to claim 58, wherein
Preparing a substrate provided with a semiconductor layer on an oxidant-permeable first insulating film;
Forming an oxidant-permeable second insulating film on the semiconductor layer;
Patterning the second insulating film and the semiconductor layer to form a semiconductor layer protruding from the plane of the substrate and a patterned second insulating film thereon;
At the interface between the semiconductor layer and the second insulating film and at the interface between the semiconductor layer and the first insulating film, the semiconductor layer is oxidized in an oxidant atmosphere so that the side surface of the semiconductor layer recedes inward,
A semiconductor layer upper region in which the width W of the upper portion of the semiconductor layer gradually decreases toward the upper end of the semiconductor layer, and a first end insulating region in which the thickness gradually increases accordingly,
Field effect type having a step of forming a semiconductor layer lower region where the width W of the lower portion of the semiconductor layer is gradually reduced toward the lower end of the semiconductor layer, and a second end insulating region whose thickness is gradually increased accordingly. A method for manufacturing a transistor. Removing the second insulating film to expose an upper surface of the semiconductor layer;
Forming a gate insulating film on an upper surface and a side surface of the semiconductor layer;
Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
61. The method of manufacturing a field effect transistor according to claim 60, further comprising a step of forming a source / drain region by introducing impurities into the semiconductor layer.   The support substrate is provided under the protruding semiconductor, and the semiconductor layer is integrally connected to the support substrate. Field effect transistor.   A supporting substrate is provided under the protruding semiconductor, and the semiconductor layer is provided on the supporting substrate via a buried insulating film. 60. The field effect transistor according to any one of 59.   2. The field effect transistor according to claim 1, wherein the projecting portion has a projecting width of 2 nm or more with respect to the surface of the gate insulating film.   2. The field effect transistor according to claim 1, wherein the overhanging portion has an overhanging width of 20 nm or less with respect to the surface of the gate insulating film.   4. The field effect transistor according to claim 1, wherein the overhanging portion has an overhanging width with respect to the surface of the gate insulating film that is not more than 10 times the thickness of the gate insulating film. A semiconductor layer protruding upward from the substrate plane, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer, and a cover covering the gate electrode A source / drain region formed in an undisclosed region,
The semiconductor layer is provided on the first insulating layer via a second insulating layer made of a material different from that of the first insulating layer,
The gate electrode is a field effect transistor having a portion on the first insulating layer directly in contact with the first insulating layer without passing through the second insulating layer.

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