JPS6477172A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6477172A
JPS6477172A JP23233987A JP23233987A JPS6477172A JP S6477172 A JPS6477172 A JP S6477172A JP 23233987 A JP23233987 A JP 23233987A JP 23233987 A JP23233987 A JP 23233987A JP S6477172 A JPS6477172 A JP S6477172A
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
sio2
recrystallization
sio2 film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23233987A
Other languages
Japanese (ja)
Inventor
Michihiko Hasegawa
Masahiro Shirasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23233987A priority Critical patent/JPS6477172A/en
Publication of JPS6477172A publication Critical patent/JPS6477172A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/78654Monocrystalline silicon transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To eliminate abnormal impurity diffusion attributable to grain boundaries for a decrease in leak currents, to improve carriers in a channel region in terms of mobility, and to increase device operating speeds by a method wherein a gate electrode is built by self-alignment on a single-crystal region formed by laser-aided recrystallization. CONSTITUTION:An SiO2 film 12 is formed on a silicon substrate 11 and, on the film 12, a polycrystalline silicon film 13 is deposited for recrystallization and, on the film 13, an SiO2 film 16 and a reflection reducing Si3N4 film 16, both provided with an opening 17, are formed. The polycrystalline silicon is then exposed to laser for recrystallization, which results in a single-crystal region 18, free of grain boundaries, in the opening 17. The single-crystal region 18 is etched halfway, with the reflection reducing Si3N4 film 16 serving as a mask, for the formation of a recess 18a. Next, an SiO2 film 20 and a polycrystalline silicon film 19a are deposited, an SiO2 film 21 is placed by application, and then a flattening process is accomplished for the retention of the applied SiO2 film 21 in a recess in the polycrystalline silicon film 19a. The applied SiO2 film 21 in the recess serves as a mask in a next process wherein the polycrystalline silicon film 19a is vertically etched for the construction of a gate electrode 19.
JP23233987A 1987-09-18 1987-09-18 Manufacture of semiconductor device Pending JPS6477172A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23233987A JPS6477172A (en) 1987-09-18 1987-09-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23233987A JPS6477172A (en) 1987-09-18 1987-09-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6477172A true JPS6477172A (en) 1989-03-23

Family

ID=16937654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23233987A Pending JPS6477172A (en) 1987-09-18 1987-09-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6477172A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5120668A (en) * 1991-07-10 1992-06-09 Ibm Corporation Method of forming an inverse T-gate FET transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5120668A (en) * 1991-07-10 1992-06-09 Ibm Corporation Method of forming an inverse T-gate FET transistor

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