JPS6473969A - Picture reduction processor - Google Patents

Picture reduction processor

Info

Publication number
JPS6473969A
JPS6473969A JP62231431A JP23143187A JPS6473969A JP S6473969 A JPS6473969 A JP S6473969A JP 62231431 A JP62231431 A JP 62231431A JP 23143187 A JP23143187 A JP 23143187A JP S6473969 A JPS6473969 A JP S6473969A
Authority
JP
Japan
Prior art keywords
parallel
reduction
result
bit
instruction string
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62231431A
Other languages
Japanese (ja)
Other versions
JPH0732454B2 (en
Inventor
Hirohisa Shiojiri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62231431A priority Critical patent/JPH0732454B2/en
Publication of JPS6473969A publication Critical patent/JPS6473969A/en
Publication of JPH0732454B2 publication Critical patent/JPH0732454B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Image Processing (AREA)
  • Editing Of Facsimile Originals (AREA)

Abstract

PURPOSE:To attain high speed by outputting the result of reduction processing in parallel toward the LSB and packing the result into a word with a predetermined bit width while referencing the value of a bit counter. CONSTITUTION:A reduction bit instruction string and an image referenced in parallel and reduced by parallel reduction devices 3, 4 to reduce the image and the result is outputted toward the LSB. The result is packed into a word data with a predetermined bit width by pack circuits 7, 9 by using bit counters 5, 6 counting number of 1s in the reduction bit instruction string in parallel and adders 8, 10 summing the outputs. Thus, high speed of a multiple of W (W is the parallel data width) is attained in comparison with a conventional image reduction bit instruction string serial reference.
JP62231431A 1987-09-16 1987-09-16 Image reduction processor Expired - Lifetime JPH0732454B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62231431A JPH0732454B2 (en) 1987-09-16 1987-09-16 Image reduction processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62231431A JPH0732454B2 (en) 1987-09-16 1987-09-16 Image reduction processor

Publications (2)

Publication Number Publication Date
JPS6473969A true JPS6473969A (en) 1989-03-20
JPH0732454B2 JPH0732454B2 (en) 1995-04-10

Family

ID=16923454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62231431A Expired - Lifetime JPH0732454B2 (en) 1987-09-16 1987-09-16 Image reduction processor

Country Status (1)

Country Link
JP (1) JPH0732454B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001101387A (en) * 1999-09-30 2001-04-13 Tohoku Ricoh Co Ltd Method for controlling area designation sheet reading, image processor and stencil printing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001101387A (en) * 1999-09-30 2001-04-13 Tohoku Ricoh Co Ltd Method for controlling area designation sheet reading, image processor and stencil printing

Also Published As

Publication number Publication date
JPH0732454B2 (en) 1995-04-10

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