JPS645897B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a heartbeat counting circuit for digitally measuring a heartbeat cycle from the output of a heartbeat sensor that discards heartbeat timing from the surface potential of a human body and displaying a predetermined heartbeat rate.

Conventional heart rate counting circuits use pulses synchronized with heartbeats output from a heartbeat sensor (hereinafter referred to as heartbeat pulses) to measure the time width for each period or multiple fixed periods, and display the heartbeat conversion each time. There were known forms that did this.

However, for example, when displaying the heart rate equivalent for each cycle, the display changes quickly and seems to have a good response, but in reality, variations in the cycle for each beat appear on the display, making it difficult to view the heart rate display. It has the disadvantage that the value changes significantly and lacks authenticity. As a countermeasure for this, if a form is adopted in which heart rate conversion is displayed for each of a plurality of fixed frequencies, the heart rate display is more accurate than in the above form because the average value of a plurality of cycles is displayed. However, when a person wants to measure the heart rate, they are forced to wait for multiple heartbeat cycles, which makes them feel suspicious and irritated by the measuring device.

The present invention eliminates the above-mentioned drawbacks, and when the heart rate measurement starts, the converted value is displayed at a relatively low frequency, and the measurement person is reassured that the device is operating normally, and thereafter the converted value is displayed at a relatively low frequency. The purpose is to display the average converted value of the cycle and give authenticity to the measured value.

The present invention will be described in detail below based on the accompanying drawings.

FIG. 1 is a block diagram of an example of a circuit according to the present invention, in which a heartbeat pulse 17 is output from a heartbeat sensor.
is passed through a one-shot pulse generation circuit 8 for matching with the circuit of the present invention, and the shaped one-shot pulse 18 is input into a control circuit 9. The control circuit 9 outputs a count gate control signal 20 for controlling the timing of inputting the count clock, and inputs it to the count clock generation circuit 10 and the reset signal latch clock generation circuit 12. An initialization signal 19 is input to the control circuit 9, which is entered when the device is powered on, thereby notifying the control system of the start of measurement. In the measurement start state, the frequency select signal 23 is input to the clock frequency switching circuit 11 so that the count clock frequency becomes the specified frequency ₁ , and the clock frequency signal 24 is
Set frequency to ₁ . Furthermore, in order to apply a clock to the counter only at a relatively low frequency, the control circuit 9 receives a one-shot pulse 18 synchronized with the heartbeat pulse 17, and sends a count gate control signal 20 to open the count gate only at a relatively low frequency. is output to the counter 13 only while the count clock 21 has a frequency of ₁ and the count gate is open. Therefore, by looking at the count number on the counter 13, the time width during which the count gate is open can be determined, and then the heart rate conversion circuit 14 outputs a heart rate value corresponding to that time width, and the latch clock 22 protects the heart rate value. If the latch data 28 is then input to the heart rate display circuit, the first heart rate measurement at a relatively low cycle is completed. Each time the measurement is repeated in this way, the latch clock 22 is output, and after inputting the latch clock 22 a suitable number of times, the control system switches to displaying the heart rate as an average of relatively high cycles. At this time, for example, if the period of the heartbeat that opens the count gate is twice the previous relatively low period, the frequency select signal 23 will be 1/2 of the frequency _1.
2 , the frequency of the clock frequency signal 24 is ₂ . Counter 13 thus receives count clock 21 of frequency ₂ for a relatively low period. In this case, the relationship between the count number of the counter 13 and the heartbeat conversion value is the same regardless of whether the heartbeat period changes when the count gate is opened or not, so the heartbeat conversion circuit can be used in combination. By the way, if the measurement is continued for a while and then stopped midway, the count gate continues to open, so the count clock 21 is inputted to the counter 13 without limit, causing the counter to overflow. At this time, if the circuit is configured to output the overflow signal 29 to the control circuit 9, the control system will be set to the measurement start state, and when measurement is started again, it will be possible to start measurement in a form converted to a relatively low heartbeat cycle. Become. What is shown in Figure 2 is a timing diagram of a type in which the heart rate is displayed at a relatively low heartbeat cycle, for example, every heartbeat cycle.After heartbeat measurement start timing 1, heartbeat pulse 2 is first
When the count gate signal 3 reaches "H" level, the count gate signal 3 becomes "H" level, and the count gate is opened until the second heartbeat pulse is input. While the count gate is open, the count clock 21 is input to the counter 13, and after the count gate signal 3 becomes "L" level and the count gate is closed, the latch clock 4 is output. At this time, since the heart rate conversion data 27 corresponding to the count number of the counter 13 is output, the latch circuit 1
5 holds predetermined heart rate data. After outputting the latch clock 4, a reset signal 5 is output, thereby resetting the contents of the counter 13 in preparation for counting the incoming count clock 21 during the next heartbeat pulse period 6. From now on, we will repeat this calculation,
In this case, the time from the start of measurement to the first display is the quickest, and the response of subsequent displays is also quick, but variations in heartbeat intervals appear on the display as they are, resulting in unreliable heartbeats. It has the disadvantage of displaying numbers. FIG. 3 is a timing diagram of a type that displays the heart rate at a relatively high heartbeat cycle, for example, every two heartbeat cycles.
The content is the same as that explained in FIG. 2, except that the period in which the count gate signal 3 is at the "H" level is the second heartbeat cycle 7, and the frequency of the count clock 21 is halved. In this case, the heart rate is displayed as the average of two heartbeat pulse cycles, so a reliable heart rate is displayed, but it takes time to display the first time, causing unnecessary irritation to the person taking the measurement. It turns out. Figure 3 shows a timing diagram of the present invention. Immediately after the start of measurement, the heart rate is displayed at a relatively low heartbeat cycle, for example 6 heartbeats per cycle, to first show the operator the normal operation of the device. After giving reassurance and displaying the heart rate conversion at that cycle for a while, in this figure, after displaying the heart rate conversion for one heart rate, the control system is converted at a relatively high heart rate cycle, for example, 2 heartbeat cycles at 7. The frequency of the count clock 21 is changed to 1/2 of the first display, and the average value of 2 heartbeat cycles is displayed to give authenticity to the measured value. .

As described above, the present invention combines the advantages of the type that repeats the display every cycle and the type that repeats the display every multiple cycles, and does not cause unnecessary anxiety to the measurer, and the measured value itself Since it is also displayed as an average of multiple cycles, it has the effect of displaying a heart rate that is closer to the truth.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an example of a circuit according to the present invention, Fig. 2 is a timing diagram of a type that displays the heart rate every one heartbeat cycle, and Fig. 3 shows a heart rate display based on the average of two heartbeat cycles. FIG. 4 is a timing diagram of the type according to the present invention. 1... Heartbeat measurement start timing, 2... Heartbeat pulse, 3... Count gate signal, 4... Latch clock, 5... Reset signal, 6... One heartbeat cycle, 7... Two heartbeat cycles, 8... One-shot. Yotsuto pulse generation circuit, 9...control circuit, 10...
Count clock generation circuit, 11... Clock frequency switching circuit, 12... Reset signal latch clock generation circuit, 13... Counter, 14... Heart rate conversion circuit, 15... Latch circuit, 16... Heart rate display circuit, 17... Heartbeat pulse, 18... One shot pulse, 19... Initialize signal, 20... Count gate control signal,
21... Count clock, 22... Latch clock, 23... Frequency select signal, 24... Clock frequency signal, 25... Frequency ₁ , 26...
Count data, 27... Heart rate conversion data, 2
8...Latch data, 29...Overflow signal, 30...Frequency ₂ , 31...Reset signal.

Claims (1)

[Claims] 1. 1 of at least two or more types of clock frequencies.
In a heart rate counting circuit that has a control circuit for selecting one frequency and inputting the selected frequency to the counter, a counter, a heart rate conversion circuit, and a heart rate display circuit, the comparison is performed for a while after the start of heart rate measurement. The count gate is opened only for periods when the target heartbeat pulse is low, and the counter is clocked at a specified frequency to display the specified number of converted heartbeats.After that, the count gate is opened for periods when the heartbeat pulse is comparatively high, and the counter is clocked at the specified frequency. A heart rate counting circuit characterized by having a control circuit that includes a clock having a frequency different from the frequency and displays a predetermined heart rate equivalent number. 2. In the heart rate counting circuit according to claim 1, after the start of heart rate measurement, the count gate is opened for one period of the heartbeat pulse, and the counter is clocked at a specified frequency to display a predetermined number of converted heartbeats. After that, the control circuit was configured to open the relatively high period count gate of 2 or more heartbeat pulses, input a clock with a frequency different from the specified frequency to the counter, and display the predetermined number of converted heartbeats. Features a heart rate counting circuit. 3. In the heart rate counting circuit as set forth in claim 1, the count gate is opened for one heartbeat pulse period only the first time after the start of heart rate measurement, and a clock of a specified frequency is input to the counter to obtain a predetermined heart rate equivalent number. is displayed, and from the second time onwards, a relatively high period count gate of 2 or more heartbeat pulses is opened, a clock with a frequency different from the specified frequency is input to the counter, and a predetermined number of converted heartbeats is displayed. A heart rate counting circuit characterized by a circuit.