JPS6455295A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS6455295A
JPS6455295A JP62212101A JP21210187A JPS6455295A JP S6455295 A JPS6455295 A JP S6455295A JP 62212101 A JP62212101 A JP 62212101A JP 21210187 A JP21210187 A JP 21210187A JP S6455295 A JPS6455295 A JP S6455295A
Authority
JP
Japan
Prior art keywords
wiring
wiring circuit
external connection
substrate
flaw
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62212101A
Other languages
Japanese (ja)
Inventor
Tatsuo Kikuchi
Kenji Uenishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62212101A priority Critical patent/JPS6455295A/en
Publication of JPS6455295A publication Critical patent/JPS6455295A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Credit Cards Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To obtain an IC unit that allows electrical characteristic inspection without giving flaw to terminals for external connection by exposing a part of wiring circuit out of sealing resin. CONSTITUTION: A wiring substrate is formed of an insulating substrate 11, external connection terminals 12, a wiring circuit 13 and wiring conductors with through holes 14; an IC device 16 mounted on the insulating substrate 11 with an adhesive 15; and an I/O electrode of the IC device 16 and the wiring circuit 13 of wiring substrate have electrically been connected with metal leads 17. A sealing resin 18 protects the IC device 16, metal leads 17, the wiring circuit 13 and their connection from environment and mechanical force from exterior. By the way, a part 13a of the wiring circuit 13 has been exposed outside of it. Obtained by this way is IC unit with no chance to get flaw on the external connection terminals 12 in electrical characteristic inspection of IC units.
JP62212101A 1987-08-26 1987-08-26 Integrated circuit device Pending JPS6455295A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62212101A JPS6455295A (en) 1987-08-26 1987-08-26 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62212101A JPS6455295A (en) 1987-08-26 1987-08-26 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6455295A true JPS6455295A (en) 1989-03-02

Family

ID=16616899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62212101A Pending JPS6455295A (en) 1987-08-26 1987-08-26 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6455295A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113555636A (en) * 2020-04-02 2021-10-26 东电化电子元器件(珠海保税区)有限公司 Assembly for protecting SMD components against environmental influences

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113555636A (en) * 2020-04-02 2021-10-26 东电化电子元器件(珠海保税区)有限公司 Assembly for protecting SMD components against environmental influences

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