JPS6450154A - Dma control system - Google Patents

Dma control system

Info

Publication number
JPS6450154A
JPS6450154A JP20505687A JP20505687A JPS6450154A JP S6450154 A JPS6450154 A JP S6450154A JP 20505687 A JP20505687 A JP 20505687A JP 20505687 A JP20505687 A JP 20505687A JP S6450154 A JPS6450154 A JP S6450154A
Authority
JP
Japan
Prior art keywords
parameter
register
length
transfer control
parameter block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20505687A
Other languages
English (en)
Inventor
Toshiaki Ihi
Kazuyuki Mitsuishi
Isao Sasazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20505687A priority Critical patent/JPS6450154A/ja
Publication of JPS6450154A publication Critical patent/JPS6450154A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP20505687A 1987-08-20 1987-08-20 Dma control system Pending JPS6450154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20505687A JPS6450154A (en) 1987-08-20 1987-08-20 Dma control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20505687A JPS6450154A (en) 1987-08-20 1987-08-20 Dma control system

Publications (1)

Publication Number Publication Date
JPS6450154A true JPS6450154A (en) 1989-02-27

Family

ID=16500710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20505687A Pending JPS6450154A (en) 1987-08-20 1987-08-20 Dma control system

Country Status (1)

Country Link
JP (1) JPS6450154A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005078596A (ja) * 2003-09-03 2005-03-24 Hitachi Ltd データ転送装置の制御方法、データ転送装置、チャネル制御装置、及び記憶デバイス制御装置
JP2008204456A (ja) * 2007-02-16 2008-09-04 Arm Ltd 複雑な非線形データの転送制御システム

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005078596A (ja) * 2003-09-03 2005-03-24 Hitachi Ltd データ転送装置の制御方法、データ転送装置、チャネル制御装置、及び記憶デバイス制御装置
JP2008204456A (ja) * 2007-02-16 2008-09-04 Arm Ltd 複雑な非線形データの転送制御システム
US8112560B2 (en) 2007-02-16 2012-02-07 Arm Limited Controlling complex non-linear data transfers

Similar Documents

Publication Publication Date Title
EP0837397A3 (en) Data transfer apparatus and data transfer system for arbitrating a plurality of I/O ports in DMA
DE3853336D1 (de) Rechnergraphikgerät zur Verarbeitung von Beleuchtungsmodellinformation.
NO863950D0 (no) Anordning for matlagring, oppvarming og utdeling, til bruk i en salgsautomat.
GB2026736B (en) Calendar data display controller in electronic devices
JPS57178523A (en) Terminal controller
JPS6450154A (en) Dma control system
DE68924041D1 (de) Vektordatenübertragungssteuerung.
DK82186A (da) Cephalosporiner, fremgangsmaader til fremstilling deraf og deres anvendelse i laegemidler
DE3688543D1 (de) Anzeigedatenspeicher.
JPS52119143A (en) Distribution terminal register
EP0385136A3 (en) Microprocessor cooperating with a coprocessor
JPS5324238A (en) Data processing system for display system
EP0292791A3 (en) Microprogrammed systems software instruction undo
JPS54124902A (en) Data transmission-reception system
DE69023677D1 (de) DMA-Übertragung für Rechnersystem.
JPS5299736A (en) Data processing unit
JPS5786970A (en) Doubled computer system
JPS5439529A (en) Transfer control system for magnetic bubble element and the like
NO164682C (no) System for aa overfoere informasjon via radioboeyer og en boeye tilpasset for bruk i et slikt system.
DE3071822D1 (en) High performance i/o controller for transferring data between a host processor and multiple i/o units
JPS51144137A (en) Input/output data control unit
JPS5371773A (en) Sequence controller
JPS53105125A (en) Data processing system
JPS5421231A (en) Data input system
Cole et al. The Financial Model in the Advanced Utility Simulation Model (AUSM)