JPS6449313A - Flip-flop - Google Patents

Abstract

PURPOSE:To curtail the number of constituting transistors at the time of constituting a digital circuit, and also, to attain low power consumption by outputting a signal which is inputted to a master flip-flop, through a slave flip-flop and a beggar flip-flop. CONSTITUTION:As for an M-S-B.D type FF, when a terminal T is in a low level, a logic level of an input D is set to a master FF 100. Subsequently, in a leading edge of the terminal T, the master FF 100 goes to a holding state of its logic level, and in such a case, the logic level is copied to a slave FF 200, as well. Next, in a trailing edge of the terminal T, the slave FF 200 goes to a holding state, and also, the master FF 100 goes to a read-in state for setting the logic level of the D input. In such a way, a signal which is inputted to the master FF 100 is held successively by the master FF 100, the slave FF 200 and a beggar FF 300, as the terminal T rises and falls. Accordingly, when this flip-flop is applied to a digital circuit which requires a phase adjustment, it is unnecessary to execute the phase adjustment.