JPS6448467A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6448467A
JPS6448467A JP62205579A JP20557987A JPS6448467A JP S6448467 A JPS6448467 A JP S6448467A JP 62205579 A JP62205579 A JP 62205579A JP 20557987 A JP20557987 A JP 20557987A JP S6448467 A JPS6448467 A JP S6448467A
Authority
JP
Japan
Prior art keywords
diffusion
area
opening
corner sections
diffusion area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62205579A
Other languages
Japanese (ja)
Inventor
Shigemi Okada
Tadashi Natsume
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62205579A priority Critical patent/JPS6448467A/en
Publication of JPS6448467A publication Critical patent/JPS6448467A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Abstract

PURPOSE:To prevent a parasitic transistor from operating, by employing the opening of a gate electrode as both an ion implanting opening for a second diffusion area and an opening for reducing the capacitance. CONSTITUTION:An opposite conductivity type second diffusion area 15, which overlaps with the corner sections of an adjacent first diffusion area 9, is formed by diffusion with a gate electrode 7 as a mask. And, a second insulating film is formed with the diffusion opening 16 of the gate electrode being left. In such a manner, the four corner sections of the first diffusion area 9 and the corner sections of the second diffusion area 15 overlap each other, which results in the conductivity type of the corner sections of the area 15 being converted from N<-> type to P<+> type. As a result, all of the first diffusion area 9 are electrically connected each other through the respective second diffusion areas 15 with relatively heavy impurity concentration, thereby the resistance under a source area 11 can be reduced and the parasitic transistor thereof can be prevented from operating.
JP62205579A 1987-08-19 1987-08-19 Manufacture of semiconductor device Pending JPS6448467A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62205579A JPS6448467A (en) 1987-08-19 1987-08-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62205579A JPS6448467A (en) 1987-08-19 1987-08-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6448467A true JPS6448467A (en) 1989-02-22

Family

ID=16509218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62205579A Pending JPS6448467A (en) 1987-08-19 1987-08-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6448467A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4981519A (en) * 1984-12-11 1991-01-01 Nippon Kokan Kabushiki Kaisha Hydraulic hardening material and method of manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607764A (en) * 1983-06-13 1985-01-16 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607764A (en) * 1983-06-13 1985-01-16 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4981519A (en) * 1984-12-11 1991-01-01 Nippon Kokan Kabushiki Kaisha Hydraulic hardening material and method of manufacturing the same

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