JPS6447087U - - Google Patents
Info
- Publication number
- JPS6447087U JPS6447087U JP14287587U JP14287587U JPS6447087U JP S6447087 U JPS6447087 U JP S6447087U JP 14287587 U JP14287587 U JP 14287587U JP 14287587 U JP14287587 U JP 14287587U JP S6447087 U JPS6447087 U JP S6447087U
- Authority
- JP
- Japan
- Prior art keywords
- check
- circuit board
- laminated
- circuit
- check pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims description 8
- 239000002344 surface layer Substances 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Description
第１図は本考案の一実施例を示す要部側断面図
、第２図は本考案による積層チエツク回路の一配
置例を示す斜視図である。
図中、１は表面層チエツクパターン、２は裏面
層チエツクパターン、３は中間層チエツクパター
ン、５はビア、１１は表面層回路基板、１２は裏
面層回路基板、１３は中間層回路基板、１４はプ
リプレグ、２０は多層プリント板、をそれぞれ示
す。
FIG. 1 is a sectional side view of a main part showing an embodiment of the present invention, and FIG. 2 is a perspective view showing an example of the arrangement of a laminated check circuit according to the present invention. In the figure, 1 is a surface layer check pattern, 2 is a back layer check pattern, 3 is an intermediate layer check pattern, 5 is a via, 11 is a surface layer circuit board, 12 is a back layer circuit board, 13 is an intermediate layer circuit board, 14 2 indicates a prepreg, and 20 indicates a multilayer printed board, respectively.
Claims (1)
板の一部に形成される積層チエツク回路であつて
、 表面層回路基板１１上に形成された表面層チエ
ツクパターン１と、中間層回路基板１３上に形成
された中間層チエツクパターン３と、裏面層回路
基板１２上に形成された裏面層チエツクパターン
２と、 これら各チエツクパターン１，３、および２を
前記各回路基板１１，１３および１２の積層構成
に基づいて順次電気的に接続するビア５を有して
なることを特徴とする多層プリント板の積層チエ
ツク回路。[Claims for Utility Model Registration] A laminated check circuit formed on a part of a multilayer printed board formed by laminating a plurality of circuit boards, which includes a surface layer check pattern 1 formed on a surface layer circuit board 11. , an intermediate layer check pattern 3 formed on the intermediate layer circuit board 13, a back layer check pattern 2 formed on the back layer circuit board 12, and each of these check patterns 1, 3, and 2 for each of the circuits. A laminated check circuit for a multilayer printed board, characterized in that it has vias 5 that are sequentially electrically connected based on the laminated structure of substrates 11, 13, and 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14287587U JPS6447087U (en) | 1987-09-17 | 1987-09-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14287587U JPS6447087U (en) | 1987-09-17 | 1987-09-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6447087U true JPS6447087U (en) | 1989-03-23 |
Family
ID=31409195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14287587U Pending JPS6447087U (en) | 1987-09-17 | 1987-09-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6447087U (en) |
-
1987
- 1987-09-17 JP JP14287587U patent/JPS6447087U/ja active Pending
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