JPS6437057U - - Google Patents

Info

Publication number
JPS6437057U
JPS6437057U JP13264787U JP13264787U JPS6437057U JP S6437057 U JPS6437057 U JP S6437057U JP 13264787 U JP13264787 U JP 13264787U JP 13264787 U JP13264787 U JP 13264787U JP S6437057 U JPS6437057 U JP S6437057U
Authority
JP
Japan
Prior art keywords
reverse mounting
mounting prevention
integrated circuit
lead terminals
type integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13264787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13264787U priority Critical patent/JPS6437057U/ja
Publication of JPS6437057U publication Critical patent/JPS6437057U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の第1実施例を示す斜視図、第
2図は本考案の第2実施例の斜視図、第3図は本
考案の第3実施例の斜視図、第4図は従来例の斜
視図である。 1:集積回路パツケージ、2:リード端子、3
,4,5:逆実装防止部、9:プリント基板、1
0:孔、11:位置決め孔。
Fig. 1 is a perspective view of the first embodiment of the invention, Fig. 2 is a perspective view of the second embodiment of the invention, Fig. 3 is a perspective view of the third embodiment of the invention, and Fig. 4 is a perspective view of the third embodiment of the invention. It is a perspective view of a conventional example. 1: Integrated circuit package, 2: Lead terminal, 3
, 4, 5: Reverse mounting prevention section, 9: Printed circuit board, 1
0: hole, 11: positioning hole.

Claims (1)

【実用新案登録請求の範囲】 (1) プリント基板の孔にリード端子を挿入して
実装される集積回路のパツケージに、プリント基
板に設けた位置決め孔に挿入される逆実装防止部
を形成したことを特徴とする逆実装防止型集積回
路。 (2) 上記逆実装防止部が、リード端子の形状を
他のリード端子の形状と異ならせてなる実用新案
登録請求の範囲第1項記載の逆実装防止型集積回
路。 (3) 上記逆実装防止部が、リード端子間の間隔
を他のリード端子間の間隔と異ならせてなる実用
新案登録請求の範囲第1項記載の逆実装防止型集
積回路。 (4) 上記逆実装防止部が、リード端子と別に設
けたピン体からなる実用新案登録請求の範囲第1
項記載の逆実装防止型集積回路。
[Scope of Claim for Utility Model Registration] (1) An integrated circuit package that is mounted by inserting lead terminals into holes in the printed circuit board is provided with a reverse mounting prevention part that is inserted into positioning holes provided in the printed circuit board. A reverse mounting prevention integrated circuit featuring: (2) The reverse mounting prevention type integrated circuit according to claim 1, wherein the reverse mounting prevention portion has a lead terminal having a shape different from that of other lead terminals. (3) The reverse mounting prevention type integrated circuit according to claim 1, wherein the reverse mounting prevention section has a spacing between lead terminals that is different from a spacing between other lead terminals. (4) The above-mentioned reverse mounting prevention part consists of a pin body provided separately from the lead terminal.
Reverse mounting prevention type integrated circuit as described in .
JP13264787U 1987-08-31 1987-08-31 Pending JPS6437057U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13264787U JPS6437057U (en) 1987-08-31 1987-08-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13264787U JPS6437057U (en) 1987-08-31 1987-08-31

Publications (1)

Publication Number Publication Date
JPS6437057U true JPS6437057U (en) 1989-03-06

Family

ID=31389804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13264787U Pending JPS6437057U (en) 1987-08-31 1987-08-31

Country Status (1)

Country Link
JP (1) JPS6437057U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009157284A1 (en) * 2008-06-24 2009-12-30 国立大学法人九州工業大学 Organic field effect transistor
JP2018081863A (en) * 2016-11-18 2018-05-24 株式会社ノーリツ Electrical equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009157284A1 (en) * 2008-06-24 2009-12-30 国立大学法人九州工業大学 Organic field effect transistor
JP2018081863A (en) * 2016-11-18 2018-05-24 株式会社ノーリツ Electrical equipment

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