JPS6435677A - Testing device for ic card - Google Patents

Testing device for ic card

Info

Publication number
JPS6435677A
JPS6435677A JP62192130A JP19213087A JPS6435677A JP S6435677 A JPS6435677 A JP S6435677A JP 62192130 A JP62192130 A JP 62192130A JP 19213087 A JP19213087 A JP 19213087A JP S6435677 A JPS6435677 A JP S6435677A
Authority
JP
Japan
Prior art keywords
card
transmission block
inputs
contents
incoming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62192130A
Other languages
Japanese (ja)
Inventor
Kinichi Kidera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP62192130A priority Critical patent/JPS6435677A/en
Publication of JPS6435677A publication Critical patent/JPS6435677A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce software-like load by making the check bit of an incoming first transmission block forcedly into an error representing level, and informing difference or sameness from/to the contents of the sequentially incoming second transmission block. CONSTITUTION:An I/O 16, that is, an interface to an IC card supplies a power source voltage Vcc to the IC card, and at the same time, inputs a reset signal, a clock signal and data, etc. A shift register 10 fetches the data transmitted from the IC card to a microcomputer 15, and inputs it to a setter 11. The setter 11 inputs the data, as it is or after inverting it, to an AND circuit 12, and a signal generation circuit 13 makes the check bit of the first transmission block forcedly into the error representing level. The computer 15 compares the contents of the first transmission block with the contents of the sequentially incoming second transmission block, and lights an OK lamp 3 or an NG lamp 4. Thus, the IC card can be tested while the software-like load being lightened.
JP62192130A 1987-07-30 1987-07-30 Testing device for ic card Pending JPS6435677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62192130A JPS6435677A (en) 1987-07-30 1987-07-30 Testing device for ic card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62192130A JPS6435677A (en) 1987-07-30 1987-07-30 Testing device for ic card

Publications (1)

Publication Number Publication Date
JPS6435677A true JPS6435677A (en) 1989-02-06

Family

ID=16286178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62192130A Pending JPS6435677A (en) 1987-07-30 1987-07-30 Testing device for ic card

Country Status (1)

Country Link
JP (1) JPS6435677A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7293709B2 (en) * 2003-01-14 2007-11-13 Nxp B.V. Detection of tampering of a smart card interface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7293709B2 (en) * 2003-01-14 2007-11-13 Nxp B.V. Detection of tampering of a smart card interface

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