JPS6428818A - Formation of semiconductor integrated circuit - Google Patents

Formation of semiconductor integrated circuit

Info

Publication number
JPS6428818A
JPS6428818A JP62183295A JP18329587A JPS6428818A JP S6428818 A JPS6428818 A JP S6428818A JP 62183295 A JP62183295 A JP 62183295A JP 18329587 A JP18329587 A JP 18329587A JP S6428818 A JPS6428818 A JP S6428818A
Authority
JP
Japan
Prior art keywords
patterns
transferred
wafer
exposure device
fine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62183295A
Other languages
Japanese (ja)
Inventor
Shinya Nakagawa
Susumu Komoriya
Mitsuhiro Morita
Nobuyuki Irikita
Morio Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62183295A priority Critical patent/JPS6428818A/en
Publication of JPS6428818A publication Critical patent/JPS6428818A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To cut down the time required for a lithographic process by a method wherein fine patterns of four adjacent semiconductor integrated circuits are gathered around the central part to be simultaneously formed into a block by means of a contraction projection exposure device. CONSTITUTION:A reticle 22 holding patterns to be transferred corresponding to fine patterns of overall contracted fine pattern formation parts 11b is prepared. Then, the patterns to be transferred held on the reticle 22 are successively transferred to the resist on a wafer by step and repeat shifting process using a contracted projection exposure device. At this time, a full-size exposure mask holding the patterns excluding the fine pattern formation parts 11b i.e. the patterns to be transferred corresponding to all rough patterns A on the wafer is prepared. The patterns to be transferred held on the mask by the full-size exposure device are temporarily transferred to the resist on the wafer. Through these procedures, the time required for lithographic process can be cut down.
JP62183295A 1987-07-24 1987-07-24 Formation of semiconductor integrated circuit Pending JPS6428818A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62183295A JPS6428818A (en) 1987-07-24 1987-07-24 Formation of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62183295A JPS6428818A (en) 1987-07-24 1987-07-24 Formation of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6428818A true JPS6428818A (en) 1989-01-31

Family

ID=16133164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62183295A Pending JPS6428818A (en) 1987-07-24 1987-07-24 Formation of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6428818A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007228825A (en) * 2006-02-28 2007-09-13 Terada Seisakusho Co Ltd Cutting blade device of tea garden implement

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007228825A (en) * 2006-02-28 2007-09-13 Terada Seisakusho Co Ltd Cutting blade device of tea garden implement

Similar Documents

Publication Publication Date Title
EP0907111A3 (en) Exposure method and method of producing a photolithographic mask
EP0810475A3 (en) Pattern exposing method using phase shift and mask used therefor
JPS55129333A (en) Scale-down projection aligner and mask used for this
EP0121412A3 (en) Method of forming by projection an integrated circuit pattern on a semiconductor wafer
DE68924048D1 (en) Exposure mask for a semiconductor wafer and exposure method.
JPS57183031A (en) Method for wafer exposure and device thereof
JPS6474547A (en) Manufacture of semiconductor for compensating strain between pattern on semiconductor body and mask for obtaining pattern
JPS6428818A (en) Formation of semiconductor integrated circuit
GB9515230D0 (en) Method of manufacturing a photo mask for manufacturing a semiconductor device
DE69131157D1 (en) Method of manufacturing an integrated circuit by repeatedly exposing a semiconductor pattern
JPH01293616A (en) Manufacture of semiconductor integrated circuit
JPS5788451A (en) Photomask
JPS6442820A (en) Manufacture of semiconductor integrated circuit
JPS5484483A (en) Formation of circuit pattern
JPS5527656A (en) Method and device of sticking photomask and wafer together
JPS5339060A (en) Lot number marking method to wafers
JPS6473616A (en) Manufacture of semiconductor device
JPS5381083A (en) Focusing method of projection exposure apparatus
JPS57168250A (en) Exposing method
JPS57113224A (en) Manufacture of semiconductor integrated circuit
JPS57132008A (en) Measuring method for pattern size
JPS5359370A (en) Positioning method
JPS5687322A (en) Manufacture of semiconductor device
JPS5632142A (en) Multichip constitution reticle
JPH04348343A (en) Reticle for reduction stepper