JPS6428818A - Formation of semiconductor integrated circuit - Google Patents
Formation of semiconductor integrated circuitInfo
- Publication number
- JPS6428818A JPS6428818A JP62183295A JP18329587A JPS6428818A JP S6428818 A JPS6428818 A JP S6428818A JP 62183295 A JP62183295 A JP 62183295A JP 18329587 A JP18329587 A JP 18329587A JP S6428818 A JPS6428818 A JP S6428818A
- Authority
- JP
- Japan
- Prior art keywords
- patterns
- transferred
- wafer
- exposure device
- fine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
PURPOSE:To cut down the time required for a lithographic process by a method wherein fine patterns of four adjacent semiconductor integrated circuits are gathered around the central part to be simultaneously formed into a block by means of a contraction projection exposure device. CONSTITUTION:A reticle 22 holding patterns to be transferred corresponding to fine patterns of overall contracted fine pattern formation parts 11b is prepared. Then, the patterns to be transferred held on the reticle 22 are successively transferred to the resist on a wafer by step and repeat shifting process using a contracted projection exposure device. At this time, a full-size exposure mask holding the patterns excluding the fine pattern formation parts 11b i.e. the patterns to be transferred corresponding to all rough patterns A on the wafer is prepared. The patterns to be transferred held on the mask by the full-size exposure device are temporarily transferred to the resist on the wafer. Through these procedures, the time required for lithographic process can be cut down.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62183295A JPS6428818A (en) | 1987-07-24 | 1987-07-24 | Formation of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62183295A JPS6428818A (en) | 1987-07-24 | 1987-07-24 | Formation of semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6428818A true JPS6428818A (en) | 1989-01-31 |
Family
ID=16133164
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62183295A Pending JPS6428818A (en) | 1987-07-24 | 1987-07-24 | Formation of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6428818A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007228825A (en) * | 2006-02-28 | 2007-09-13 | Terada Seisakusho Co Ltd | Cutting blade device of tea garden implement |
-
1987
- 1987-07-24 JP JP62183295A patent/JPS6428818A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007228825A (en) * | 2006-02-28 | 2007-09-13 | Terada Seisakusho Co Ltd | Cutting blade device of tea garden implement |
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