JPS6424522A - Transmission system for control signal - Google Patents

Transmission system for control signal

Info

Publication number
JPS6424522A
JPS6424522A JP18025987A JP18025987A JPS6424522A JP S6424522 A JPS6424522 A JP S6424522A JP 18025987 A JP18025987 A JP 18025987A JP 18025987 A JP18025987 A JP 18025987A JP S6424522 A JPS6424522 A JP S6424522A
Authority
JP
Japan
Prior art keywords
control signal
control
basic frame
buffer
transponders
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18025987A
Other languages
Japanese (ja)
Inventor
Shinichi Fujiyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18025987A priority Critical patent/JPS6424522A/en
Publication of JPS6424522A publication Critical patent/JPS6424522A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To perform control which sends out a control signal in basic frame units as many times as the number of transponders by providing a TDMA basic frame counter to an address converting circuit provided externally to a control LSI which controls the control signal. CONSTITUTION:The control LSI 1 for a satellite communication TDMA device has a burst counter 8 and processing is performed, burst by burst, to control the transmission of the control signal, etc. A basic frame counter 6 counts basic frames of TDMA. A buffer 2 holds the control signal. The control LSI 1 access the high-order bits of the buffer 2 with the output of the basic frame counter 6 and also accesses the low-order bits of the buffer 2 with the output of the basic frame counter 6 to perform the control where in the control signal held in the buffer 2 is sent out in basic frame units as many times as the number of transponders. Consequently, the control signal is sent out as many times as the number of the transponders without increasing the circuit scale.
JP18025987A 1987-07-20 1987-07-20 Transmission system for control signal Pending JPS6424522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18025987A JPS6424522A (en) 1987-07-20 1987-07-20 Transmission system for control signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18025987A JPS6424522A (en) 1987-07-20 1987-07-20 Transmission system for control signal

Publications (1)

Publication Number Publication Date
JPS6424522A true JPS6424522A (en) 1989-01-26

Family

ID=16080127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18025987A Pending JPS6424522A (en) 1987-07-20 1987-07-20 Transmission system for control signal

Country Status (1)

Country Link
JP (1) JPS6424522A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6317585B1 (en) 1998-02-23 2001-11-13 Nec Corporation Mobile satellite communication system with quick retransmission determination function
US7004610B2 (en) 2000-09-25 2006-02-28 Mitsubishi Rayon Co., Ltd. Light source device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6317585B1 (en) 1998-02-23 2001-11-13 Nec Corporation Mobile satellite communication system with quick retransmission determination function
US7004610B2 (en) 2000-09-25 2006-02-28 Mitsubishi Rayon Co., Ltd. Light source device

Similar Documents

Publication Publication Date Title
JPS5438724A (en) Display unit
GB9004473D0 (en) Output buffer precharge circuit for dram
JPS6450152A (en) Communication controller
JPS5424532A (en) Reception unit for still picture signal
JPS6424522A (en) Transmission system for control signal
JPS5418247A (en) Data buffering device
JPS53101234A (en) Address converting device
JPS57191753A (en) Register controlling system
JPS547248A (en) Signal process system
JPS6410369A (en) Module address conversion system
JPS5760435A (en) Data transfer controlling system
Gaskell Novel aspects of the structure of glasses
JPS5255402A (en) Signal transmission/reception unit
JPS57100536A (en) Data buffer device
JPS5335442A (en) Transmission and reception method and unit for address signal
JPS5381020A (en) Error check method for memory unit
JPS57185543A (en) Microcomputer
JPS56147541A (en) Remote process input and output controller for computer
JPS644134A (en) Communication control equipment
JPS5759233A (en) Signal transmitting circuit
JPS55154853A (en) Data transmission system
JPS5745749A (en) Interrupting frame transmission system
JPS5421229A (en) Data fetch system
JPS5278326A (en) Buffer register control system
JPS5419615A (en) Control system for input and output unit