JPS6418746U - - Google Patents
Info
- Publication number
- JPS6418746U JPS6418746U JP1987111875U JP11187587U JPS6418746U JP S6418746 U JPS6418746 U JP S6418746U JP 1987111875 U JP1987111875 U JP 1987111875U JP 11187587 U JP11187587 U JP 11187587U JP S6418746 U JPS6418746 U JP S6418746U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor element
- attached
- electrode pattern
- pattern wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
第1図はこの考案の一実施例を適用して半導体
素子を取付けた回路基板の縦断面図、第2図は半
導体素子を回路基板に取付ける製造工程図、第3
図及び第4図はそれぞれ従来の半導体素子の取付
構造を示した縦断面図である。 1……回路基板、2……電極パターン配線、4
……樹脂材、5……半導体素子、6……バンプ電
極。
素子を取付けた回路基板の縦断面図、第2図は半
導体素子を回路基板に取付ける製造工程図、第3
図及び第4図はそれぞれ従来の半導体素子の取付
構造を示した縦断面図である。 1……回路基板、2……電極パターン配線、4
……樹脂材、5……半導体素子、6……バンプ電
極。
Claims (1)
- 【実用新案登録請求の範囲】 上面に電極パターン配線が形成された回路基板
と、 この回路基板の電極パターン配線に接続される
バンプ電極を有し前記回路基板の上面に取付けら
れる半導体素子と、 この半導体素子が取付けられた前記半導体素子
の下部領域の前記回路基板の上面に印刷形成され
て溶着され前記半導体素子を前記回路基板上に封
止固定する樹脂材とを具備してなる半導体素子の
取付構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987111875U JPS6418746U (ja) | 1987-07-23 | 1987-07-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987111875U JPS6418746U (ja) | 1987-07-23 | 1987-07-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6418746U true JPS6418746U (ja) | 1989-01-30 |
Family
ID=31350314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987111875U Pending JPS6418746U (ja) | 1987-07-23 | 1987-07-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6418746U (ja) |
-
1987
- 1987-07-23 JP JP1987111875U patent/JPS6418746U/ja active Pending